KR101624395B1 - 반도체 장치의 제조 방법, 기판 처리 장치 및 기록 매체 - Google Patents
반도체 장치의 제조 방법, 기판 처리 장치 및 기록 매체 Download PDFInfo
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- KR101624395B1 KR101624395B1 KR1020140036811A KR20140036811A KR101624395B1 KR 101624395 B1 KR101624395 B1 KR 101624395B1 KR 1020140036811 A KR1020140036811 A KR 1020140036811A KR 20140036811 A KR20140036811 A KR 20140036811A KR 101624395 B1 KR101624395 B1 KR 101624395B1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/36—Carbonitrides
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Abstract
Description
도 2는 본 발명의 제1 실시 형태에서 적절하게 사용되는 기판 처리 장치의 종형 처리로의 개략 구성도로, 처리로 부분을 도 1의 A-A선 단면도로 도시하는 도면.
도 3은 본 발명의 제1 실시 형태에서 적절하게 사용되는 기판 처리 장치의 컨트롤러의 개략 구성도로, 컨트롤러의 제어계를 블록도로 나타내는 도면.
도 4는 본 발명의 제1 실시 형태의 성막 시퀀스에 있어서의 성막 플로우를 나타내는 도면.
도 5의 (a)는 본 발명의 제1 실시 형태의 성막 시퀀스에 있어서의 가스 공급의 타이밍을 나타내는 도면, (b)는 그 변형예를 나타내는 도면.
도 6은 본 발명의 제1 실시 형태의 다른 변형예의 성막 시퀀스에 있어서의 성막 플로우를 나타내는 도면으로, (a)는 SiOC막 형성 공정을 나타내는 도면, (b)는 SiOC막 개질 공정을 나타내는 도면.
도 7은 본 발명의 제2 실시 형태의 성막 시퀀스에 있어서의 성막 플로우를 나타내는 도면.
도 8의 (a)는 본 발명의 제2 실시 형태의 성막 시퀀스에 있어서의 가스 공급 및 RF 전력 공급의 타이밍을 나타내는 도면, (b)는 그 변형예를 나타내는 도면.
도 9는 본 발명의 제3 실시 형태의 성막 시퀀스에 있어서의 성막 플로우를 나타내는 도면.
도 10의 (a)는 본 발명의 제3 실시 형태의 성막 시퀀스에 있어서의 가스 공급의 타이밍을 나타내는 도면, (b)는 그 변형예를 나타내는 도면.
도 11은 본 발명의 제3 실시 형태의 다른 변형예의 성막 시퀀스에 있어서의 성막 플로우를 나타내는 도면.
도 12의 (a)는 본 발명의 제3 실시 형태의 다른 변형예의 성막 시퀀스에 있어서의 가스 공급 및 RF 전력 공급의 타이밍을 나타내는 도면, (b)는 또 다른 변형예를 나타내는 도면.
도 13은 본 발명의 제1 실시 형태의 박막 형성 공정의 촉매 반응의 설명도로, (a)는 스텝 1a에 있어서의 설명도, (b)는 스텝 2a에 있어서의 설명도.
도 14는 촉매 가스로서 사용되는 각종 아민의 명칭, 화학 조성식, 화학 구조식 및 산 해리 상수를 나타내는 도면.
도 15의 (a)∼(e)는 원료 가스로서 사용되는 각종 실란의 화학 구조식을 나타내는 도면으로, 각각, BTCSM, BTCSE, TCDMDS, DCTMDS, MCPMDS의 화학 구조식을 나타내는 도면.
도 16은 본 발명의 실시예 및 비교예의 각종 조건하에서 성막된 박막의 습식 에칭률을 나타내는 그래프.
200 : 웨이퍼(기판)
201 : 처리실
202 : 처리로
203 : 반응관
207 : 히터
209 : 매니폴드
231 : 배기관
232a∼232j : 가스 공급관
244 : APC 밸브(압력 조정부)
Claims (20)
- 기판에 대해 실리콘, 탄소 및 할로겐 원소를 포함하고, Si-C 결합을 갖는 원료 가스와, 제1 촉매 가스를 공급하는 공정과,
상기 기판에 대해 산화 가스와 제2 촉매 가스를 공급하는 공정과,
상기 기판에 대해 탄소 및 질소 중 적어도 어느 하나를 포함하는 개질 가스를 공급하는 공정
을 포함하는 사이클을 소정 횟수 행함으로써, 상기 기판 상에, 실리콘, 산소 및 탄소를 포함하는 박막 또는 실리콘, 산소, 탄소 및 질소를 포함하는 박막을 형성하는 공정을 갖는 반도체 장치의 제조 방법. - 제1항에 있어서, 상기 원료 가스와 상기 제1 촉매 가스를 공급하는 공정과, 상기 산화 가스와 상기 제2 촉매 가스를 공급하는 공정은, 논 플라즈마의 분위기하에서 행해지는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 원료 가스와 상기 제1 촉매 가스를 공급하는 공정과, 상기 산화 가스와 상기 제2 촉매 가스를 공급하는 공정에서는, 상기 기판의 온도를 실온 이상 150℃ 이하의 온도로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 사이클은,
상기 원료 가스와 상기 제1 촉매 가스를 공급하는 공정과,
상기 산화 가스와 상기 제2 촉매 가스를 공급하는 공정
을 포함하는 세트를 소정 횟수 행함으로써, 상기 기판 상에, 실리콘, 산소 및 탄소를 포함하는 제1 박막을 형성하는 공정과,
상기 개질 가스를 공급하는 공정을 행함으로써, 상기 제1 박막을, 탄소를 더 포함하는 제2 박막, 질소를 더 포함하는 제2 박막 또는 탄소와 질소를 더 포함하는 제2 박막으로 개질하는 공정
을 포함하는 반도체 장치의 제조 방법. - 제4항에 있어서, 상기 제1 박막을 형성하는 공정 및 상기 제1 박막을 개질하는 공정은, 상기 기판을 동일한 처리실 내에 수용한 상태에서 행해지는 반도체 장치의 제조 방법.
- 제4항에 있어서, 상기 제1 박막을 형성하는 공정 및 상기 제1 박막을 개질하는 공정은, 상기 기판을 각각 서로 다른 처리실 내에 수용한 상태에서 행해지는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 사이클은,
상기 원료 가스와 상기 제1 촉매 가스를 공급하는 공정과,
상기 산화 가스와 상기 제2 촉매 가스를 공급하는 공정과,
상기 개질 가스를 공급하는 공정
을 이 순서대로 행하는 공정을 포함하는 반도체 장치의 제조 방법. - 제1항에 있어서, 상기 개질 가스를 공급하는 공정에서는, 상기 기판의 온도를, 상기 원료 가스와 상기 제1 촉매 가스를 공급하는 공정과, 상기 산화 가스와 상기 제2 촉매 가스를 공급하는 공정에 있어서의 상기 기판의 온도와 동등한 온도로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 개질 가스를 공급하는 공정에서는, 상기 기판의 온도를 실온 이상 500℃ 이하의 온도로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 개질 가스를 공급하는 공정에서는, 상기 기판의 온도를 200℃ 이상 900℃ 이하의 온도로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 개질 가스를 공급하는 공정은, 논 플라즈마의 분위기하에서 행해지는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 개질 가스를 공급하는 공정에서는, 플라즈마 상태로 여기된 상기 개질 가스를 상기 기판에 대해 공급하는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 원료 가스는, 실리콘, 탄소 및 염소를 포함하고 Si-C 결합을 갖는 반도체 장치의 제조 방법.
- 제13항에 있어서, 상기 원료 가스는, 알킬기 및 알킬렌기 중 적어도 어느 하나를 포함하는 반도체 장치의 제조 방법.
- 제13항에 있어서, 상기 원료 가스는, Si-C-Si 결합 및 Si-C-C-Si 결합 중 적어도 어느 하나를 갖는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 개질 가스는, 탄소 함유 가스, 질소 함유 가스 및 1분자 중에 탄소와 질소를 함유하는 가스 중 적어도 어느 하나를 포함하는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 개질 가스는, 탄화수소계 가스, 아민계 가스 및 비아민계 가스 중 적어도 어느 하나를 포함하는 반도체 장치의 제조 방법.
- 제1항에 있어서, 상기 제1 및 제2 촉매 가스는, 아민계 촉매 가스를 포함하는 반도체 장치의 제조 방법.
- 기판을 수용하는 처리실과,
상기 처리실 내에 실리콘, 탄소 및 할로겐 원소를 포함하고, Si-C 결합을 갖는 원료 가스를 공급하는 원료 가스 공급계와,
상기 처리실 내에 산화 가스를 공급하는 산화 가스 공급계와,
상기 처리실 내에 제1 및 제2 촉매 가스를 공급하는 촉매 가스 공급계와,
상기 처리실 내에 탄소 및 질소 중 적어도 어느 하나를 포함하는 개질 가스를 공급하는 개질 가스 공급계와,
상기 처리실 내의 기판에 대해 상기 원료 가스와 상기 제1 촉매 가스를 공급하는 처리와, 상기 처리실 내의 상기 기판에 대해 상기 산화 가스와 상기 제2 촉매 가스를 공급하는 처리와, 상기 처리실 내의 상기 기판에 대해 상기 개질 가스를 공급하는 처리를 포함하는 사이클을 소정 횟수 행함으로써, 상기 기판 상에, 실리콘, 산소 및 탄소를 포함하는 박막 또는 실리콘, 산소, 탄소 및 질소를 포함하는 박막을 형성하는 처리를 행하도록 상기 원료 가스 공급계, 상기 산화 가스 공급계, 상기 촉매 가스 공급계 및 상기 개질 가스 공급계를 제어하는 제어부
를 갖는 기판 처리 장치. - 처리실 내의 기판에 대해 실리콘, 탄소 및 할로겐 원소를 포함하고, Si-C 결합을 갖는 원료 가스와, 제1 촉매 가스를 공급하는 순서와,
상기 처리실 내의 상기 기판에 대해 산화 가스와 제2 촉매 가스를 공급하는 순서와,
상기 처리실 내의 상기 기판에 대해 탄소 및 질소 중 적어도 어느 하나를 포함하는 개질 가스를 공급하는 순서
를 포함하는 사이클을 소정 횟수 행함으로써, 상기 기판 상에, 실리콘, 산소 및 탄소를 포함하는 박막 또는 실리콘, 산소, 탄소 및 질소를 포함하는 박막을 형성하는 순서를 컴퓨터에 실행시키는 프로그램을 기록한 컴퓨터 판독 가능한 기록 매체.
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CN104425313A (zh) | 2015-03-18 |
US9698007B2 (en) | 2017-07-04 |
TW201511088A (zh) | 2015-03-16 |
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