KR101465134B1 - Voltage regulator, operation method thereof, and dynamic voltage frequency scaling system including the same - Google Patents

Abstract

A voltage regulator according to an embodiment of the present invention comprises: a power supply unit supplying an input voltage in response to a pulse width modulation (PWM) signal; an inductor receiving the input voltage from the power supply unit and connected between the power supply unit and a first node; a first capacitor connected between the first node and a ground terminal and charged by an inductor; a switching unit which performs switching between the first node and a second node in response to a control signal; an amplifier connected between the first node and the second node; a second capacitor connected between the second node and a ground terminal and charged by the amplifier according to operations of the switching unit; and a control circuit comparing a target voltage and a voltage of the first node to generate a PWM signal and a control signal.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a voltage regulator, a method of operating the same, and a dynamic voltage and frequency scaling system including the voltage regulator,

The present invention relates to a voltage regulator, and more particularly, to a voltage regulator with reduced tracking time, a method of operation thereof, and a dynamic voltage and frequency scaling system including the same.

The cores or multicore cores included in a computing system can process large amounts of computations as the operating frequency gets faster, thereby consuming a lot of power. As information processing technology develops, cores or multi-cores do not always need to operate at fast operating speeds. Accordingly, recently, a system supporting dynamic voltage and dynamic frequency frequency scaling (DVFS) for adjusting the operating voltage and the operating frequency has been provided.

The DVFS system uses a phase locked loop and a voltage regulator to adjust the operating voltage and operating frequency. At this time, the voltage regulator converts the input voltage to generate the operating voltage having the same level as the target voltage. The operation of this voltage regulator is called a tracking operation. The tracking operation greatly affects the performance and reliability of the DVFS system. Accordingly, voltage regulators are being developed to increase the speed of the tracking operation.

It is an object of the present invention to reduce the tracking time of the voltage regulator.

A power supply unit for supplying an input voltage in response to a pulse width modulation signal according to an embodiment of the present invention; An inductor coupled between the power supply and the first node for receiving the input voltage from the power supply; A first capacitor connected between the first node and a ground terminal, the first capacitor being charged by the inductor; A switching unit for switching between the first node and the second node in response to a control signal; An amplifier coupled between the first node and the second node; A second capacitor connected between the second node and the ground terminal, the second capacitor being charged by the amplifier according to the operation of the switching unit; And a control circuit for comparing the target voltage and the voltage of the first node to generate the pulse width modulated signal and the control signal.

In one embodiment, the power supply includes a pMOS transistor and an nMOS transistor, the source of the pMOS transistor receiving the input voltage, the drain of the pMOS transistor being coupled to the inductor, Width modulation signal, a source of the nMOS transistor is connected to the ground terminal, a drain of the nMOS transistor is connected to the inductor, and a gate of the nMOS transistor receives the pulse width modulation signal.

In an embodiment, the control circuit generates the control signal such that the switching section is turned off when the difference between the voltage of the first node and the voltage level of the target voltage is equal to or greater than a predetermined value.

In an embodiment, the switching unit may include a pMOS transistor, and the control circuit may control the control signal to turn on the control signal so that the pMOS transistor is turned off when the difference between the voltage of the first node and the voltage level of the target voltage is equal to or greater than a predetermined value. High.

In an embodiment, the amplifier is an operational amplifier, a first input terminal of the amplifier is connected to the first node, and an output terminal and a second input terminal of the amplifier are connected to the second node.

In one embodiment, the amplifier senses a difference between a voltage of the first node and a voltage of the second node, and the second node senses a difference between the voltage of the first node and the voltage of the second node, Adjust the voltage at the node.

In an embodiment, when the voltage level of the first node is equal to the level of the target voltage, the voltage of the first node is transmitted to the external device.

In an embodiment, when the difference between the target voltage and the voltage of the first node is equal to or less than a predetermined level, the control circuit generates the control signal so that the switching section is turned on.

In an embodiment, when the switching unit is turned on, the first capacitor and the second capacitor are connected in parallel.

According to another aspect of the present invention, there is provided a method of operating a voltage regulator for converting an input voltage to generate an operating voltage, the method comprising: receiving a changed target voltage; Determining whether a difference between the changed target voltage and the operating voltage is equal to or greater than a predetermined level; Decreasing an internal composite capacitance value when the difference between the changed target voltage and the operating voltage is equal to or greater than a predetermined level; And performing a tracking operation so that the level of the operating voltage becomes the level of the changed target voltage.

In an embodiment, the voltage regulator includes a first capacitor coupled between a first node and a ground terminal; A second capacitor coupled between the ground node and a second node; And

Wherein when the difference between the changed target voltage and the operating voltage is equal to or greater than a predetermined level, the step of decreasing the internal combined capacitance value comprises: And turning off the switching unit when the difference in the operating voltage is equal to or higher than a predetermined level.

The step of performing the tracking operation so that the level of the operating voltage may be the level of the changed target voltage may include the steps of turning on the switching unit when the voltage difference between the operating voltage and the changed target voltage is less than the predetermined level, And turning on the first capacitor and the second capacitor in parallel.

A dynamic voltage and frequency scaling system according to another embodiment of the present invention includes a core operating on an operating voltage and an operating frequency; And a dynamic voltage and frequency scaling controller for setting a target voltage and a target frequency according to an operating state of the core and generating the operating voltage and the operating frequency based on the set target voltage and the set target frequency, Wherein the dynamic voltage and frequency scaling controller comprises: a phase locked loop for generating the operating frequency based on the target frequency; And a voltage regulator for generating the operating voltage based on the target voltage, wherein the voltage regulator includes: a power supply for supplying an input voltage in response to a pulse width modulation signal; An inductor coupled between the power supply and the first node for receiving the input voltage from the power supply; A first capacitor connected between the first node and a ground terminal, the first capacitor being charged by the inductor; A switching unit for switching between the first node and the second node in response to a control signal; An amplifier coupled between the first node and the second node; A second capacitor connected between the second node and the ground terminal, the second capacitor being charged by the amplifier according to the operation of the switching unit; And a control circuit for comparing the target voltage and the voltage at the first node to generate the pulse width modulated signal and the control signal.

According to the present invention, it is possible to reduce the tracking time by reducing the internal capacitance value during the voltage regulator's tracking operation. Accordingly, there is provided a voltage regulator having improved performance, a method of operating the same, and a dynamic voltage and frequency scaling system including the same.

1 is a block diagram showing a dynamic voltage frequency conversion system.
2 is a graph for explaining the operation of the voltage regulator shown in FIG.
3 is a graph for explaining another operation of the voltage regulator shown in FIG. .
4 is a circuit diagram showing a voltage regulator according to an embodiment of the present invention.
5 to 7 are diagrams for explaining the operation of the voltage regulator shown in FIG.
8 is a flowchart showing the operation of the voltage regulator shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention. .

A voltage regulator according to an embodiment of the present invention receives an input voltage and converts the received input voltage to output an output voltage. At this time, the buck converter can perform the tracking operation so that the output voltage becomes the target voltage. The buck converter may compare the target voltage and the output voltage during the tracking operation to control the internal switches such that the capacity of the internal capacitor is reduced. Thus, the tracking speed of the buck converter is improved, so that a buck converter with improved performance is provided.

Figure 1 is a block diagram illustrating a dynamic voltage and frequency scaling (DVFS) system. Referring to FIG. 1, a DVFS system 100 includes a core 110 and a DVFS controller 120. The core 110 receives the operating frequency Fdd and the operating voltage Vdd from the DVFS controller 120 and can operate based on the received operating frequency Fdd and the operating voltage Vdd. The core 110 may process the requested operation through operation according to the operation request of the user program of the software layer. Illustratively, the user program may be an operating system program (OS) or an application program. Illustratively, the core 110 may be implemented as a multicore. Illustratively, core 110 may be provided to an application processor of a mobile system.

Illustratively, the core 110 may have different operating speeds depending on the operating frequency Fdd and the operating voltage Vdd. For example, in the normal mode, the core 110 may operate based on an operating frequency (Fdd) having a first frequency value and an operating voltage (Vdd) having a first voltage value. At this time, when the operating frequency Fdd has a second frequency value (the second frequency value is higher than the first frequency value) and the operating voltage Vdd is the second voltage value (the second voltage value is the first voltage value ≪ / RTI > In this case, the operating speed of the core 110 is faster than the operating speed of the normal mode, and the power consumption will increase. Alternatively, the operating frequency Fdd may be a third frequency value (the third frequency value is lower than the first frequency value), the operating voltage Vdd may be a third voltage value (the third voltage value may be a first voltage value ). ≪ / RTI > In this case, the operating speed of the core 110 is slower than that of the normal mode, and the power consumption will decrease.

The DVFS controller 120 includes a DVFS manager 121, a phase locked loop (PLL) 122, and a voltage regulator 123. The DVFS manager 121 can control the operating frequency Fdd and the operating voltage Vdd of the core 110. [ For example, under control of the core 120, the DVFS manager 121 may lower the operating frequency Fdd and the operating voltage Vdd to reduce power consumption. The DVFS manager 121 may increase the operating frequency Fdd and the operating voltage Vdd in order to improve the operating speed according to the control of the core 120. [ Illustratively, the DVFS manager 121 supplies the information of the target frequency Ftar and the information of the target voltage Vtar to the phase locked loop 122 and the voltage Vtar, respectively, in order to adjust the operating frequency Fdd and the operating voltage Vdd, To the regulator 123.

The phase locked loop 122 may receive the information of the target frequency Ftar from the DVFS manager 121 and may generate the operating frequency Fdd based on the information of the received target frequency Ftar. Illustratively, the operating frequency Fdd may be equal to the target frequency Ftar.

The voltage regulator 123 may receive the input voltage Vin and convert the received input voltage Vin to generate the operating voltage Vdd. The voltage regulator 123 can receive the information of the target voltage Vtar from the received DVFS manager 121. [ At this time, the voltage regulator 123 will generate the operating voltage Vdd so that the operating voltage Vdd becomes the target voltage Vtar. Illustratively, the voltage regulator 123 may be provided as a Buck Converter.

According to the embodiment of the present invention described above, the DVFS system can control the operation frequency and the operation voltage according to the operation mode. Thus, a DVFS system with improved performance and reduced power consumption is provided.

2 is a graph for explaining the operation of the voltage regulator shown in FIG. 1 and 2, the voltage regulator 123 may receive the input voltage Vin and convert the received input voltage Vin to generate the operating voltage Vdd. The voltage regulator 123 can receive the information of the target voltage Vtar from the DVFS manager 121. [ The voltage regulator 123 can increase the level of the operating voltage Vdd by the level of the target voltage Vtar. Illustratively, the operation of adjusting the level of the operating voltage Vdd such that the level of the operating voltage Vdd becomes the level of the target voltage Vtar is called a tracking operation. The time from when the target voltage Vtar has changed to when the operating voltage Vdd reaches the target voltage Vtar is called the tracking time. The voltage regulator 123 may perform a tracking operation so that the level of the operating voltage Vdd becomes the level of the target voltage Vtar.

3 is a graph for explaining another operation of the voltage regulator shown in FIG. 1 and 3, the target voltage Vtar may be changed before the operating voltage Vdd generated by the voltage regulator 123 is stabilized. For example, at the first time point t1 of the voltage regulator 123, the target voltage may be changed to the first target voltage Vtar1. At this time, the voltage regulator 123 will control the operating voltage Vdd such that the operating voltage Vdd becomes the level of the first target voltage Vtar1. Thereafter, the target voltage may be changed to the second target voltage Vtar2 at the second time point t2. At this time, the voltage regulator 123 will control the operating voltage Vdd so that the operating voltage Vdd becomes the second target voltage Vtar2. Thereafter, the target voltage may be changed to the third target voltage Vtar3 at the third time point t3. The operating voltage Vdd generated from the voltage regulator 123 at the third time point t3 does not reach the second target voltage Vtar2. Thereafter, the target voltage may be changed to the first target voltage Vtar1 at the fourth time point t4. At this time, the voltage regulator 123 will control the operating voltage Vdd so that the level of the operating voltage Vdd becomes the level of the first target voltage Vtar1.

The operation voltage Vdd generated from the voltage regulator 123 for the second to fourth times as shown in FIG. 3 will not reach the target voltage. That is, the target voltage is changed before the tracking operation of the voltage regulator 123 is completed, so that the stable operating voltage Vdd is not provided. This increases malfunction or power consumption. Accordingly, a reduction in the time required for the tracking operation of the voltage regulator 123 (hereinafter referred to as "tracking time") is required.

The switching frequency of the switches included in the voltage regulator 123 may be increased to reduce the tracking time of the voltage regulator 123. [ However, when the switching frequency is increased, the switching loss due to the parasitic capacitor component of the power transistors is increased, so that the voltage efficiency of the voltage regulator 123 is lowered.

4 is a circuit diagram showing a voltage regulator according to an embodiment of the present invention. 1 and 4, the voltage regulator 123 includes a first pMOS transistor Mp1, a first nMOS transistor Mn1, an inductor L1, a first capacitor C1, a second capacitor C2, An amplifier AMP, a second pMOS transistor Mp2, and a control circuit 123a.

The source of the first pMOS transistor Mp1 receives the input voltage Vin and the gate receives the PWM signal PWM from the control circuit 123a and the drain is connected to one end of the inductor L1. The gate of the first nMOS transistor Mn1 receives the PWM signal PWM from the control circuit 123a, the drain thereof is connected to one end of the inductor L1, and the source thereof is grounded. The first pMOS transistor Mp1 provides the input voltage Vin to the inductor L1 in response to the PWM signal PWM. The first nMOS transistor Mn1 may provide the power stored in the inductor L1 to the first capacitor C1 or the second capacitor C2 in response to the PWM signal PWM.

Although not shown in the figure, the first pMOS transistor Mp1 and the first nMOS transistor Mn1 may be provided as a power supply. The power supply unit includes a first pMOS transistor Mp1 and a first nMOS transistor Mn1 and may provide the input voltage Vin to the inductor L1 in response to the PWM signal PWM.

One end of the inductor L1 is connected to the drain of the first PMOS transistor Mp1 and the drain of the first nMOS transistor Mn1 and the other end is connected to the first node n1. One end of the first capacitor C1 is connected to the first node n1, and the other end is grounded. One end of the second capacitor C2 is connected to the second node n2, and the other end is grounded.

The inductor L1 receives the input voltage Vin through the first pMOS transistor Mp1 and supplies the charged voltage through the first nMOS transistor Mn1 to the first capacitor C1 or the second capacitor C2 .

The amplifier AMP is connected between the first node and the second node n1, n2. For example, the amplifier AMP may be an operational amplifier (OP-AMp). The first input terminal of the amplifier AMP may be connected to the first node n1, and the second input terminal and the output terminal may be connected to the second node n2. The amplifier AMP senses the voltage difference between the first node n1 and the second node n2 and controls the voltage of the second node n2 so that the voltages of the first node n1 and the second node n2 become equal to each other. The voltage can be adjusted.

The source of the second pMOS transistor Mp2 is connected to the first node n1 and the drain is connected to the second node n2 and the gate receives the control signal CTRL from the control circuit 123a. The second pMOS transistor Mp2 may connect or disconnect the first node and the second node n1, n2 with each other in response to the control signal CTRL.

The control circuit 123a receives the target voltage Vtar and the operation voltage Vdd and generates the PWM signal PWM and the control signal CTRL based on the received target voltage Vtar and the operation voltage Vdd do. For example, the target voltage Vtar may be higher than the operation voltage Vdd. In this case, the control circuit 123a can increase the duty ratio of the PWM signal PWM and output the control signal CTRL as a logic high so that the second pMOS transistor Mp2 is turned off. In other words, during the tracking operation of the voltage regulator 123, the second pMOS transistor Mp2 will be turned off. At this time, the first capacitor C1 is charged by the inductor L1 and the second capacitor C2 is charged by the amplifier AMP. That is, since the combined capacitance value by the first capacitor and the second capacitor (C1, C2) is reduced during the tracking operation of the voltage regulator 123, the charging speed of the first capacitor and the second capacitor (C1, C2) . Therefore, the tracking time of the voltage regulator 123 will be reduced.

Illustratively, the operating voltage Vdd may be the charging voltage of the first capacitor C1. Or the operating voltage Vdd may be the charging voltage of the combined capacitor in which the first capacitor C1 and the second capacitor C2 are combined. Or the operating voltage Vdd may be the voltage of the first node n1.

Illustratively, voltage regulator 123 may be a buck converter. The operation of the voltage regulator 123 is described in more detail with reference to the following figures.

According to the present invention described above, the tracking time can be shortened by reducing the internal capacitance value during the tracking operation of the voltage regulator 123. [ Thus, a voltage regulator with improved performance is provided.

5 to 7 are diagrams for explaining the operation of the voltage regulator shown in FIG. 4 to 7, the voltage regulator 123 includes a first pMOS transistor Mp1, a first nMOS transistor Mn1, an inductor L1, a first capacitor C1, a second capacitor C2, An amplifier AMP, a second pMOS transistor Mp2, and a control circuit 123a. The first pMOS transistor Mp1, the first nMOS transistor Mn1, the inductor L1, the first capacitor C1, the second capacitor C2, the amplifier AMP, the second pMOS transistor Mp2, Since the circuit 123a has been described with reference to FIG. 4, a detailed description thereof is omitted.

The voltage regulator 123 can output the operating voltage Vdd having the level of the first target voltage Vtar during the first interval I. [ Thereafter, the level of the target voltage Vtar may be changed in the second section II. At this time, the voltage regulator 123 can perform the tracking operation. During the second period II, the control signal CTRL may be logic high. In response to the logic high control signal CTRL during the second period II, the second pMOS transistor Mp2 will be turned off as shown in Fig. As the second pMOS transistor Mp2 is turned off, the first node and the second node n1 and n2 will be separated from each other as shown in Fig. Accordingly, the first capacitor C1 will be charged by the inductor L1 and the second capacitor C2 will be charged by the amplifier AMP.

For example, the first pMOS transistor Mp1 and the first nMOS transistor Mn1 will operate according to the PWM signal PMW. The first capacitor C1 will be charged to the voltage of the first node n1 by the power stored in the inductor L1 according to the operation of the first pMOS transistor Mp1 and the first nMOS transistor Mn1. And the second capacitor C2 will be charged with the voltage of the second node n2. At this time, when the voltage of the first node n1 becomes higher than the voltage of the second node n2, the amplifier AMP amplifies the voltages of the first and second nodes n1 and n2, (n2) can be adjusted. Therefore, when the second pMOS transistor Mp2 is turned off as compared with the case where the second pMOS transistor Mp2 is turned on, the capacitance value charged by the inductor L1 is reduced, (That is, the tracking speed of the voltage regulator 123) will increase.

Illustratively, the operating voltage Vdd may be charged to a predetermined value (e.g., 90% level of the target voltage Vtar). The voltage regulator 123 will transit the control signal CTRL to a logic low during the third period III and increase the voltage level such that the operating voltage Vdd is the target voltage Vdd. During the third period (III), the voltage regulator 123 will have the circuit configuration as shown in FIG. That is, as the control signal CTRL becomes a logic low, the second pMOS transistor Mp2 is turned on, and the first node and the second node n1, n2 are connected to each other. That is, voltages of the first node and the second node (n1, n2) become equal to each other, and the first capacitor and the second capacitor (C1, C2) are connected in parallel. The capacitance value charged by the inductor L1 during the third section III is charged by the inductor L1 during the second section II because the first capacitor and the second capacitor C1 and C2 are connected in parallel. Lt; / RTI > capacitance value. That is, the charging rate of the operating voltage Vdd of the third section III may be slower than the charging rate of the operating voltage Vdd of the second section II. However, the voltage regulator 123 according to the present invention can reduce the tracking time by reducing the capacitance value charged by the inductor L1 during the tracking operation (i.e., during the second period II). Thus, a voltage regulator with improved performance is provided.

8 is a flowchart showing the operation of the voltage regulator shown in FIG. Referring to FIGS. 4 and 8, in step S110, the voltage regulator 123 may receive information of the changed target voltage Vtar. For example, the voltage regulator 123 may receive information of the target voltage Vtar changed by the control of the DVFS manager 121 (see FIG. 1).

In step S120, the voltage regulator 123 can determine whether the difference between the operating voltage Vdd and the changed target voltage Vtar is equal to or greater than a predetermined level.

When the difference between the operating voltage Vdd and the changed target voltage Vtar is equal to or greater than the predetermined level, in step S130, the voltage regulator 123 can reduce the internal composite capacitance value. For example, the voltage regulator 123 may transition the control signal CTRL to a logic high. In response to the control signal CTRL, the second pMOS transistor Mp2 may be turned off. Accordingly, the first node n1 and the second node n2 are separated from each other, so that only the first capacitor C1 will be charged by the inductor L1. That is, the capacitance value charged by the inductor Ll will decrease.

In step S140, the voltage regulator 123 may perform a tracking operation. For example, the first pMOS transistor Mp1 will provide the input voltage Vin to the inductor L1 in response to the PWM signal PWM. The first nMOS transistor Mn1 will regenerate the power stored in the inductor L1 in response to the PWM signal PWM to the first capacitor C1. The voltage regulator 123 may repeat the above-described operation to increase or decrease the level of the operating voltage Vdd.

When the difference between the operating voltage Vdd and the changed target voltage Vtar is not equal to or greater than the predetermined level, the voltage regulator 123 performs the operation of step S140. At this time, the voltage regulator 123 will perform the tracking operation without decreasing the value of the internal composite capacitance.

In step S150, the voltage regulator 123 can determine whether the operating voltage Vdd and the changed target voltage Vtar are the same. If the operating voltage Vdd and the changed target voltage Vtar are not equal, the voltage regulator 123 performs the operation of step S120. When the operating voltage Vdd and the changed target voltage Vtar are equal to each other, the voltage regulator 123 ends the operation. Illustratively, the voltage regulator 123 can provide the generated operating voltage Vdd to the core 110 (see FIG. 1). Or the voltage regulator 123 may provide the generated operating voltage Vdd to another external device.

Although the embodiments of the present invention have been described based on pMOS and nMOS transistors, the scope of the present invention is not limited thereto. The pMOS and nMOS transistors may be replaced with nMOS transistors and pMOS transistors, It can be changed to the same power switch element.

According to the embodiment of the present invention described above, the voltage regulator 123 can shorten the tracking time by reducing the internal composite capacitance value during the tracking operation. Thus, a voltage regulator with improved performance is provided.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the claims equivalent to the claims of the present invention as well as the following claims.

100: DVFS system
110: Core
120: DVFS controller
121: DVFS Manager
122: phase locked loop
123: Voltage regulator
Mp1, Mp2: a first pMOS transistor and a second pMOS transistor
Mn1: first nMOS transistor
AMP: Amplifier
n1, n2: the first node and the second node
123a: control circuit

Claims (13)

A power supply for supplying an input voltage in response to the pulse width modulation signal;
An inductor coupled between the power supply and the first node for receiving the input voltage from the power supply;
A first capacitor connected between the first node and a ground terminal, the first capacitor being charged by the inductor;
A switching unit for switching between the first node and the second node in response to a control signal;
An amplifier coupled between the first node and the second node;
A second capacitor connected between the second node and the ground terminal, the second capacitor being charged by the amplifier according to the operation of the switching unit; And
And a control circuit for comparing the target voltage and the voltage of the first node to generate the pulse width modulation signal and the control signal. The method according to claim 1,
Wherein the power supply unit includes a pMOS transistor and an nMOS transistor,
Wherein a source of the pMOS transistor receives the input voltage, a drain of the pMOS transistor is coupled to the inductor, a gate of the pMOS transistor receives the pulse width modulation signal, and a source of the nMOS transistor is connected to the ground terminal Wherein a drain of the nMOS transistor is coupled to the inductor and a gate of the nMOS transistor receives the pulse width modulated signal. The method according to claim 1,
Wherein the control circuit generates the control signal such that the switching unit is turned off when the difference between the voltage of the first node and the voltage level of the target voltage is equal to or greater than a predetermined value. The method of claim 3,
Wherein the switching unit includes a pMOS transistor,
Wherein the control circuit generates the control signal to a logic high such that the pMOS transistor is turned off when the difference between the voltage of the first node and the voltage level of the target voltage is equal to or greater than a predetermined value. The method according to claim 1,
Wherein the amplifier is an operational amplifier, a first input terminal of the amplifier is connected to the first node, and an output terminal and a second input terminal of the amplifier are connected to the second node. 6. The method of claim 5,
Wherein the amplifier detects a difference between the voltage of the first node and the voltage of the second node and controls the voltage of the second node to be equal to the voltage of the first node and the second node based on the sensed voltage difference Voltage regulator to regulate. The method according to claim 1,
Wherein the voltage of the first node is transmitted to an external device when the voltage level of the first node is equal to the level of the target voltage. The method according to claim 1,
And the control circuit generates the control signal so that the switching section is turned on when a difference between the target voltage and the voltage of the first node is equal to or lower than a predetermined level. 9. The method of claim 8,
Wherein when the switching unit is turned on, the first capacitor and the second capacitor are connected in parallel. A method of operating a voltage regulator for converting an input voltage to generate an operating voltage,
Receiving a modified target voltage;
Determining whether a difference between the changed target voltage and the operating voltage is equal to or greater than a predetermined level;
Decreasing an internal composite capacitance value when the difference between the changed target voltage and the operating voltage is equal to or greater than a predetermined level; And
And performing a tracking operation such that the level of the operating voltage is the level of the changed target voltage. 11. The method of claim 10,
The voltage regulator
A first capacitor connected between the first node and the ground terminal;
A second capacitor coupled between the ground node and a second node; And
And a switching unit for switching between the first node and the second node,
And decreasing the internal composite capacitance value when the difference between the changed target voltage and the operating voltage is equal to or greater than a predetermined level,
And turning off the switching unit if the difference between the changed target voltage and the operating voltage is greater than or equal to a predetermined level. 12. The method of claim 11,
The step of performing the tracking operation so that the level of the operating voltage becomes the level of the changed target voltage,
And turning on the switching unit to parallel-connect the first capacitor and the second capacitor when the voltage difference between the operating voltage and the changed target voltage is less than or equal to the predetermined level. A core operating based on operating voltage and operating frequency; And
And a dynamic voltage and frequency scaling controller for setting a target voltage and a target frequency according to an operation state of the core and generating the operation voltage and the operation frequency based on the set target voltage and the set target frequency,
The dynamic voltage and frequency scaling controller
A phase locked loop for generating the operating frequency based on the target frequency; And
And a voltage regulator for generating the operating voltage based on the target voltage,
The voltage regulator
A power supply for supplying an input voltage in response to the pulse width modulation signal;
An inductor coupled between the power supply and the first node for receiving the input voltage from the power supply;
A first capacitor connected between the first node and a ground terminal, the first capacitor being charged by the inductor;
A switching unit for switching between the first node and the second node in response to a control signal;
An amplifier coupled between the first node and the second node;
A second capacitor connected between the second node and the ground terminal, the second capacitor being charged by the amplifier according to the operation of the switching unit; And
And a control circuit for comparing the target voltage and the voltage at the first node to generate the pulse width modulated signal and the control signal.

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