KR101159329B1 - Driving circuit of liquid crystal display and driving method of lcd - Google Patents

Abstract

The present invention discloses a liquid crystal display gate drive circuit and a method of driving the same, which can reduce the output power (number of channels) of a liquid crystal display gate drive IC (Gate Drive Integrated Circuit), thereby reducing manufacturing cost. The disclosed invention includes a liquid crystal display panel in which a plurality of gate lines and data lines are formed; A data driver supplying a data signal to the data line; A gate driver supplying a gate driving signal to the gate line; And a control unit for dividing a gate driving signal generated from the gate driver and supplying the gate driving signal to a gate line of the liquid crystal display panel.

The present invention has the effect of reducing the number of channels of the gate drive, power consumption.

LCD, gate, data, output, reduction, drive

Description

Liquid crystal display driving circuit and driving method {DRIVING CIRCUIT OF LIQUID CRYSTAL DISPLAY AND DRIVING METHOD OF LCD}

1 is a plan view showing a schematic structure of a liquid crystal display device;

2 is a view showing a liquid crystal display gate driving circuit according to the prior art.

3 is a diagram illustrating a liquid crystal display gate driving signal according to the related art.

4 is a view showing a liquid crystal display gate driving circuit according to the present invention.

5 is a diagram illustrating a liquid crystal display gate driving signal according to the present invention;

* Description of the symbols for the main parts of the drawings *

1: liquid crystal display device 2: liquid crystal display panel

4: backlight unit 6: lamp drive unit

8: data driver 10: gate driver

12: timing controller 14: power generation unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display drive circuit and a drive which can reduce manufacturing power while reducing power consumption by reducing an output terminal (number of channels) of a gate drive integrated circuit (Gate Drive Integrated Circuit). It is about a method.

In today's information society, display elements are more important than ever as visual information transfer media. Cathode ray tubes or cathode ray tubes, which are currently mainstream, have problems with weight and volume. Many kinds of flat panel displays have been developed to overcome the limitations of the cathode ray tube.

The flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an electroluminescence (EL). Most of these are commercially available and commercially available.

The liquid crystal display displays an image by controlling an electric field applied to the liquid crystal layer in response to the video signal. The liquid crystal display device is a flat panel display device having advantages of small size, thinness, and low power consumption, and is used as a portable computer such as a notebook PC, an office automation device, an audio / video device, an indoor / outdoor display device, and the like. A liquid crystal display device having such a configuration is rapidly replacing a cathode ray tube (CRT) due to its thinness and low power consumption. In particular, a liquid crystal display panel that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has the advantages of excellent image quality and low power consumption. As a result, it is rapidly developing in size and high resolution.

1 is a plan view showing a schematic structure of a liquid crystal display device.

Referring to FIG. 1, a liquid crystal display device 1 inputs data to a liquid crystal display panel 2 having a data line and a gate line intersected and a TFT formed at an intersection thereof, and data lines of the liquid crystal display panel 2. A data driver 8, a gate driver 10 for inputting gate pulses to gate lines of the liquid crystal display panel 2, and a backlight unit for irradiating light to the liquid crystal display panel 2. 4), a lamp driver 6 for driving the lamp of the backlight unit 4, a data driver 8, the gate driver 10 and the lamp driver 6 of the liquid crystal display panel 2 A timing controller 12 for controlling and a power generation unit 14 for supplying power required for the liquid crystal display panel 2 and the backlight unit 4 are provided.

The thin film transistor TFT formed at the intersection of the data lines and the gate lines of the liquid crystal display panel 2 transmits the data on the data lines to the liquid crystal cell in response to a scanning pulse from the gate driver 6. Will be entered. The timing controller 12 rearranges digital video data input from a digital video card (not shown) for each of red (R), green (G), and blue (B).

The data R, G, and B rearranged by the timing controller 12 are input to the data driver 8. In addition, the timing controller 12 uses a horizontal and vertical synchronizing signal (H, V) and a clock signal (CLK) input to the data control signal (DCS) and the gate control signal (Gate Control Signal). The GCS is generated and supplied to the data driver 8 and the gate driver 10.

The data control signal DCS is input to the data driver 8 including a dot clock Dclk, a source shift clock SSC, a source enable signal SOE, a polarity inversion signal POL, and the like. The gate control signal GCS is input to the gate driver 10 including a gate start pulse GSP, a gate shift clock GSC, a gate output enable GOE, and the like.

After the data driver 8 samples the data according to the data control signal DCS from the timing controller 12, the data driver 8 divides the sampled data into one line for each horizontal period (1H, 2H, ???). Latch and supply the latched data to the data lines. In addition, the digital pixel data R, G, and B from the timing controller 12 are converted into analog pixel signals by using the gamma voltages GMA1 to 6 input from the power generator 14 and supplied to the data lines. do.

The gate driver 10 drives the liquid crystal cell by using a shift register that sequentially generates gate pulses in response to a gate start pulse GSP among the gate control signals GCS from the timing controller 12. And a level shifter for shifting to a voltage level suitable for. The gate driver 10 sequentially supplies a gate high voltage and a low voltage to the gate lines in response to the gate control signal GCS.

The backlight unit 4 includes a lamp (not shown) for irradiating light to the liquid crystal display panel 2 and a lamp inverter for driving the lamp. The lamp receives the driving voltage from the lamp inverter and generates light. The lamp inverter receives the lamp driving voltage Vinv from the power generator 14 and drives the lamp.

The power generator 14 applies the common electrode voltage Vcom to the liquid crystal display panel 2, the gamma voltage GMA1 to 6 to the data driver 8, and the lamp driving voltage Vinv to the lamp inverter. Supply.

2 is a diagram illustrating a liquid crystal display device gate driving circuit according to the prior art, and FIG. 3 is a diagram illustrating a liquid crystal display device gate driving signal according to the prior art.

2 and 3, a gate driver 11 and a data driver 8 are disposed on side surfaces of the liquid crystal display panel 2, and the driving signals output from the gate driver 11 are gated. As a gate output signal, a plurality of gate lines G (n), G (n + 1), G (n + 2), G (n + 3), formed on the liquid crystal display panel 2 It is sequentially applied to G (n + 4), ...) to turn on / off the switching elements.

As shown in FIG. 3, the gate lines G (n), G (n + 1), G (n + 2), G (n + 3), G (n + 4), ...) Accordingly, it can be seen that gate output signals, which are gate driving signals, are sequentially applied. The gate driver 11 sequentially generates gate driving signals according to a gate shift clock signal GSC and a gate start pulse signal GSP.

That is, the gate driver 11 has an output terminal (channel) corresponding to the gate lines formed in the liquid crystal display panel 2, and the output terminals and the gate lines are 1: 1 corresponded to each other and are generated at each output terminal. A drive signal is applied to each gate line.

However, the gate driving circuit having the above structure has a problem in that the production cost of the gate drive IC is high because the output terminals (channels) must be formed in the gate driver 11 as many gate lines as the number of gate lines.

In addition, when the number of output stages of the gate drive IC increases as described above, power consumption increases because the voltage of the gate driving signal is high.

The present invention provides a liquid crystal display device gate drive circuit which can reduce the power consumption and production cost by reducing the output terminal (number of channels) of the gate drive circuit by forming a control unit capable of controlling the drive signal in the liquid crystal display device; The purpose is to provide a driving method.

In order to achieve the above object, the gate driving circuit according to the present invention,

A liquid crystal display panel in which a plurality of gate lines and data lines are formed;

A data driver supplying a data signal to the data line;

A gate driver supplying a gate driving signal to the gate line; And

And a control unit for dividing a gate driving signal generated from the gate driver and supplying the gate driving signal to a gate line of the liquid crystal display panel.

Here, the control unit includes a first switching element disposed for each gate line, a second switching element disposed between the gate lines, a first control signal terminal and a first control element for controlling the first switching element and the second switching element. It is characterized by consisting of two control signal stage.

According to another exemplary embodiment of the present invention, a gate driving method of a liquid crystal display device is provided.

Providing a gate driver generating a gate driving signal;

Sequentially supplying a gate driving signal to the liquid crystal display panel from an output terminal of the gate driver; And

And applying a driving signal output from one output terminal of the gate driver to at least two gate lines disposed in the liquid crystal display panel.

Here, the driving signal is applied to two or more gate lines arranged in the liquid crystal display panel, so that the gate lines are sequentially applied to each line, and the driving signal is outputted from one output terminal of the gate driver. In the step of applying to two or more gate lines arranged in the display panel, it is driven by the first switching element formed on each gate line and the second switching element formed between the gate line.

According to the present invention, by forming a control unit for controlling the driving signal in the liquid crystal display device, the output terminal (number of channels) of the gate driving circuit can be reduced, thereby reducing power consumption and production cost.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a gate driving circuit according to the present invention.

As shown in FIG. 4, a plurality of gate lines and data lines are formed on the liquid crystal display panel 102 to define a unit pixel area, and a thin film transistor as a switching element is formed in the unit pixel area.

A data driver 108 for applying a data signal and a gate driver 111 for applying a gate driving signal are disposed around the outer circumference of the liquid crystal display panel 102.

In addition, a control unit 120 for dividing and supplying the gate driving signal is disposed before the gate driving signal generated from the gate driver 111 is applied to the gate lines of the liquid crystal display panel 102.

The control unit 120 is composed of switching element NMOS transistors and PMOS transistors integrally formed on the liquid crystal display panel 102 to divide the gate driving signal generated from the gate driver 111, and then sequentially gate lines. To apply.

That is, the control unit 120 controls any one output terminal output from the gate driver 111 to apply a driving signal to any two gate lines of the gate lines formed on the liquid crystal display panel 102. N-type transistors (NMOS), which are switching elements, are disposed in all gate lines formed in the liquid crystal display panel 102, and the first gate line, the third gate line, the second gate line, and the fourth gate line of the gate lines; This is realized by arranging P-type transistors (PMOS) which are switching elements in units.

The N-type transistor NMOS and the P-type transistor PMOS are controlled by the first control signal terminal CNT1 and the second control signal terminal CNT2. In the first control signal terminal CNT1, a first inverting unit 130a for inverting a signal and a second inverting unit 130b for inverting a signal are disposed in the second control signal terminal CNT2.

A detailed signal operation will be described with reference to the signal waveform of FIG. 5 as follows.

FIG. 5 is a view illustrating a gate driving signal according to the present invention, in which a gate shift clock (GSC) and a gate start pulse (GSP) signal for generating a gate driving signal in the gate driver 111 are known in the art (see FIG. 2). The gate driving signals (A, B, C, and D shown in FIG. 5) of which the period is doubled are generated at two times longer periods.

As such, any one driving signal output from the gate driver 111 is simultaneously input to any two gate lines G (n) and G (n + 1) of the liquid crystal display panel 102.

In this case, the first control signal terminal CNT1 and the second control signal terminal CNT2 control the switching elements (NMOS and PMOS) disposed in the control unit 120 to control the gate line G (n), The driving signal is sequentially applied to G (n + 1).

That is, the signals A, B, C, and B of FIG. 4 receive signals from two output terminals of the gate driver 111, and drive signals are applied to the A, B, C, and D lines (four gate lines). Is approved. However, when the driving signal is applied, an on / off control signal is applied from the first control signal terminal CNT1 and the second control signal terminal CNT2 so that the gate output signal is sequentially output from the gate output.

In detail, a gate driving signal having a period twice as long as the conventional one is simultaneously applied to the A and B gate lines, but the first gate line G (primarily by the on / off control signal of the first control signal terminal CNT1) is applied. n)) only after the driving signal is applied (the NMOS turn-on state of the first gate line, the NMOS turn-off state of the second gate line), and then the drive signal is applied to the second gate line G (n + 1) (the second gate). NMOS turn-on of line, NMOS turn-off of first gate line.

At this time, the PMOS disposed between the first gate line G (n) and the third gate line G (n + 2) pulls a low voltage up to the first gate line to the first gate line G (n). After the high voltage output (gate output) to low voltage state.

That is, since the high voltage is applied when the NMOS of the first gate line is turned on, the PMOS disposed between the first and third gate lines G (n) and G (n + 2) is the first. 2 When the NMOS is turned off by the control signal terminal CNT2, on the contrary, when the NMOS is turned off, the PMOS is turned on to transfer the low voltage of the third gate line to the first gate line. To be authorized.

In this way, the PMOS is disposed between the gate lines so that the gate driving signal is sequentially applied, and the low voltage is pulled from the lower gate line to maintain the low voltage state.

Therefore, in the present invention, the output terminal (number of channels) output from the gate driver 111 is reduced by half, and the driving signal is displayed by matching two gate lines to one output terminal by the control of the controller 120. Application to the panel 102 was made.

As described in detail above, the present invention forms a control unit capable of controlling a driving signal in the liquid crystal display, thereby reducing the output terminal (number of channels) of the gate driving circuit, thereby reducing power consumption and reducing production costs. It works.

The present invention is not limited to the above-described embodiments, and various changes can be made by those skilled in the art without departing from the gist of the present invention as claimed in the following claims.

Claims (14)

A liquid crystal display panel in which a plurality of gate lines and data lines are formed; A data driver supplying a data signal to the data line; A gate driver supplying a gate driving signal to the gate line; And A control unit for dividing a gate driving signal generated from the gate driver and supplying the gate driving signal to a gate line of the liquid crystal display panel; The control unit, A first switching element arranged for each gate line; And a second switching element disposed between the gate lines. The method of claim 1, The control unit, A first control signal stage for controlling the first switching element; And And a second control signal terminal for controlling the second switching element. The liquid crystal display device gate driving circuit according to claim 1, wherein the first switching element is an NMOS transistor. The liquid crystal display device gate driving circuit according to claim 1, wherein the second switching element is a PMOS transistor. The gate driving circuit of claim 2, wherein the first control signal terminal and the second control signal terminal further include a first inversion unit and a second inversion unit for inverting a signal. The liquid crystal display device gate driving circuit according to claim 1, wherein the number of output terminals of the gate driver is 1/2 of the number of gate lines formed in the liquid crystal display panel. The liquid crystal display device gate driving circuit according to claim 1, wherein any one of output terminals of the gate driver applies a driving signal to two gate lines of the gate lines of the liquid crystal display panel. 2. The gate driving circuit of claim 1, wherein the gate line receives a low voltage from an adjacent gate line by the second switching element to maintain a low state. Providing a gate driver generating a gate driving signal; Sequentially supplying a gate driving signal to a liquid crystal display panel from an output terminal of the gate driver; And And applying a driving signal output from one output terminal of the gate driver to two or more gate lines disposed in the liquid crystal display panel. In the step of applying a drive signal output from one output terminal of the gate driver to two or more gate lines arranged in the liquid crystal display panel, And a second switching element formed between the first switching element formed on each of the gate lines and a second switching element formed between the gate lines. 10. The method of claim 9, wherein the driving signal is applied to two or more gate lines arranged in the liquid crystal display panel so that the gate driving signals are sequentially applied to each line. delete 10. The gate driving method of claim 9, wherein the first switching element is an NMOS transistor. 10. The method of claim 9, wherein the second switching element is a PMOS transistor. 10. The gate driving method of claim 9, wherein the gate line receives a low voltage from an adjacent gate line by the second switching element to maintain a low state.

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