KR102007775B1 - Liquid crystal display device and driving method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display. In particular, the output period of three data voltages input to a distribution unit connected to one output channel of a main driver and connected to three data lines can be set differently. Another object is to provide a liquid crystal display and a driving method thereof. To this end, the liquid crystal display according to the present invention comprises: a panel in which pixels are formed at intersections of gate lines and data lines; Convert image data into data voltages, divide one horizontal period into a plurality of sub-horizontal periods having different periods, and output one data voltage for each of the sub-horizontal periods through one output channel; A main driver for outputting a plurality of selection signals having a pulse width corresponding to each of the two; And a distribution unit for sequentially outputting data voltages input from the one output channel to the sub-horizontal periods according to the selection signals and sequentially outputting them to different data lines formed in the panel.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device comprising a panel made of low temperature polysilicon (LTPS) and a driving method thereof.

Flat panel displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic electroluminescent display (OLED), and more recently, an electrophoretic display ( EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among flat panel display devices, liquid crystal display devices are the most widely used due to the advantages of mass production technology, ease of driving means, and high quality.

1 is a waveform diagram illustrating various waveforms applied to a conventional low temperature polysilicon (LTPS) type liquid crystal display, and FIG. 2 is a holding time and luminance of data voltages applied to a conventional low temperature polysilicon type liquid crystal display. It is a graph showing the relationship between the reduction rate.

The liquid crystal display device includes a panel and a main driver.

The panel is divided into a display area in which an image is output and a non-display area in which an image is not output.

In the liquid crystal display, the main driver supplies a data voltage to each pixel formed in the panel to drive the liquid crystal of each pixel, and the image is represented by a change in the light transmittance of the liquid crystal.

In the panel, a thin film transistor which is a switching element for driving the liquid crystal constituting each pixel is formed. As the thin film transistor, an amorphous thin film transistor using amorphous silicon and a polysilicon thin film transistor using low temperature polysilicon (LTPS) are used.

Since the polysilicon thin film transistor has a higher charge mobility than the amorphous silicon, the polysilicon thin film transistor is suitable for a high resolution display device requiring a fast response speed.

A data distribution unit connected to the main driver is formed in a non-display area of the panel formed of the polysilicon thin film transistor using the low temperature polysilicon (LTPS). The data divider distributes data voltages supplied from the main driver through one connection line to three data lines.

To this end, the data distribution unit includes three switching transistors connected to the connection line and the data line, and the three switching transistors are sequentially turned on by three selection signals to supply data voltages to the corresponding data lines. do.

That is, each of the three switching transistors sequentially supplies R, G, and B data voltages to the data lines when the gate is turned on by the selection signal.

Here, since the pulse widths of the three selection signals are formed to be constant, the on time of the switching transistor is set to one timing. That is, since the pulse widths PSWWA of the three selection signals MUX1, MUX2, and MUX3 are the same in FIG. 1, the ON time of the three switching transistors turned on by each of the three selection signals is one. Is set to timing.

On the other hand, in the liquid crystal display device, in order to prevent the deterioration of the liquid crystal caused by long-term electric field applied to the liquid crystal for a long time, the frame inversion method, the line inversion method, the column inversion method. Various inversion methods such as (Column Inversion) or Dot Inversion methods are applied.

Among these, the column inversion method is a method in which the polarity is changed for each column (vertical line), and in the column inversion method, the polarities of the R, G, and B data are reversed.

In the low-temperature polysilicon type liquid crystal display device configured as described above, since the R, G, and B pixels are formed in each column, the data output to the R, G, and B pixels when the column inversion scheme is applied. The voltage is inverted.

In this case, the holding timing of the green data voltage becomes short due to the polarity inversion of the R, G, and B data voltages.

For example, as shown in FIG. 1, the pulse widths PSWWA of the three selection signals MUX1, MUX2, and MUX3 sequentially output during one horizontal period are the same, and the interval PSWGA between the selection signals is the same. Although the same is true, the holding time GO of the green data voltage outputted to the data line by the second selection signal MUX2 between the first selection signal MUX1 and the third selection signal MUX3 is a red data voltage. Compared with the holding time RO of and the holding time BO of the blue data voltage, it is relatively short.

That is, in the low temperature polysilicon type liquid crystal display device driven by the column inversion method, the polarity of the data voltages output to adjacent red pixels, green pixels, and blue pixels is changing. In this case, the polarities of the red data voltage and the blue data voltage are the same, but the green data voltage has a polarity opposite to that of the red data voltage and the blue data voltage.

Therefore, as shown in FIG. 1, considering the period GR to be changed to ground and the period P required for polarity conversion, during the period in which the data voltage is actually output while the selection signal is turned on, green The period during which the data voltage G is output becomes relatively short. That is, in the case of green between different polarity changes, due to the delay due to rising / falling, the data holding time (Source Holding Time) is shorter than the actual input. Have.

In particular, green has the greatest influence on luminance, as shown in FIG. That is, the amount of luminance decrease when the holding time of the green data voltage decreases is relatively larger than the rate at which the holding time of the red data voltage and the blue data voltage decreases and the luminance decreases.

In other words, as the output holding time of the green data voltage, which has the greatest influence on the luminance, is shortened, the green data voltage is not sufficiently charged in the pixel, and thus, the luminance performance. Is falling compared to red and green.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and is capable of differently setting output periods of three data voltages input to a distribution unit connected to one output channel of a main driver and connected to three data lines. Another object is to provide a liquid crystal display and a driving method thereof.

According to an aspect of the present invention, there is provided a liquid crystal display device including: a panel in which pixels are formed at intersections of gate lines and data lines; Convert image data into data voltages, divide one horizontal period into a plurality of sub-horizontal periods having different periods, and output one data voltage for each of the sub-horizontal periods through one output channel; A main driver for outputting a plurality of selection signals having a pulse width corresponding to each of the two; And a distribution unit for sequentially outputting data voltages input from the one output channel to the sub-horizontal periods according to the selection signals and sequentially outputting them to different data lines formed in the panel.

According to an aspect of the present invention, there is provided a method of driving a liquid crystal display device, which converts image data into data voltages, divides one horizontal period into a plurality of sub horizontal periods having different periods, and outputs one output channel. Outputting one data voltage for each of the sub horizontal periods, and outputting a plurality of selection signals having a pulse width corresponding to each of the sub horizontal periods; And sequentially outputting data voltages input for each sub-horizontal period from the one output channel according to the selection signals to different data lines formed in the panel.

According to the present invention, the charging time of the data voltage can be sufficiently secured in the high resolution panel driven by the column inversion method and the LTPS method. That is, since the charging time of the data voltage can be sufficiently secured, it is possible to secure the holding time margin according to the polarity inversion of the data voltage.

In particular, since the holding time margin of the green data voltage having a polarity opposite to that of the red data voltage and the blue data voltage can be secured, the luminance of white is weaker than that of the conventional liquid crystal display. 4% can be improved.

In other words, the shorter the holding time of the data voltage is, the longer the holding time of the green data voltage, which is the greatest decrease in luminance, may increase the overall brightness of the image, in particular, the brightness of the white Can be.

In detail, the margin of the data driver output is eliminated, the margin of the holding time is set to maximum, and the indirect effects of the present invention are indirectly confirmed. On average, about 4% improvement.

1 is a waveform diagram showing various waveforms applied to a conventional low temperature polysilicon (LTPS) type liquid crystal display device.
2 is a graph showing a relationship between a holding time and luminance reduction rate of data voltages applied to a conventional low temperature polysilicon type liquid crystal display device.
Figure 3 is a schematic diagram of an embodiment of a liquid crystal display according to the present invention.
4 is a configuration diagram of an embodiment of a data driver applied to a liquid crystal display according to the present invention.
5 is an exemplary view showing an internal configuration of a switch applied to a liquid crystal display according to the present invention.
6 is a waveform diagram illustrating various waveforms applied to a liquid crystal display according to the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a schematic diagram of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 4 is a schematic diagram of a data driver applied to a liquid crystal display according to the present invention, and FIG. 6 is an exemplary diagram illustrating an internal configuration of a switch applied to a liquid crystal display according to the present invention, and FIG. 6 is a waveform diagram showing various waveforms applied to the liquid crystal display according to the present invention.

In the liquid crystal display according to the present invention, as illustrated in FIG. 2, a panel 100 and image data in which pixels are formed at each intersection of the gate lines GL1 to GLg and the data lines DL1 to DLd. Converts the data into data voltages, divides one horizontal period 1H into a plurality of sub-horizontal periods having different periods, and outputs one data voltage per sub-horizontal period through one output channel 350. From the main driver 500 and the one output channel 350 for outputting a plurality of selection signals MUX1, MUX2, MUX3 having a pulse width corresponding to each of the subhorizontal periods, for each subhorizontal period. And a distribution unit 600 for sequentially switching the input data voltages according to the selection signals MUX1, MUX2, and MUX3 and sequentially outputting them to different data lines formed in the panel 100. .

First, the panel 100 includes a lower substrate and an upper substrate bonded together with a liquid crystal layer (not shown) therebetween.

A plurality of pixels are formed on the lower substrate by the intersection of d data lines DL1 to DLd and g gate lines GL1 to GLg, and sequentially drive the data lines and the gate lines. The main driver 500 is mounted.

The pixels are formed in the display area 110 of the panel 100, and the main driver 500 is formed in the non-display area 120 of the panel 100.

One pixel is referred to as a red subpixel (hereinafter simply referred to as a 'red pixel'), a green subpixel (hereinafter simply referred to as a 'green pixel') and a blue subpixel (hereinafter simply referred to as a 'blue pixel') ).

Each of the plurality of pixels is formed between one adjacent gate line and a thin film transistor connected to one adjacent data line, a plurality of pixel electrodes (pixel electrodes) and a plurality of pixel electrodes connected to the thin film transistor, It includes a plurality of common electrodes (not shown) receiving a common voltage.

The semiconductor layer of the thin film transistor, which is applied to the liquid crystal display device according to the present invention, is formed of polysilicon having high electron mobility (˜10 cm 2 / Vsec or more) by a low temperature poly-silicon (LTPS) process. do. On the other hand, when the semiconductor layer of the thin film transistor T is primarily formed of amorphous silicon (a-Si), the semiconductor layer of the thin film transistor T is a crystallization process using a secondary laser or heat treatment secondary It can be formed of polysilicon by.

The present invention may be applied to a panel in which the semiconductor layer of the thin film transistor is formed of amorphous silicon, and in particular, may be applied to a panel made of low temperature poly-silicon (LTPS).

The pixel electrode and the common electrode are formed side by side with the liquid crystal layer interposed therebetween, and the liquid crystal is driven according to a difference voltage between the data voltage supplied to the pixel electrode through the thin film transistor and the common voltage supplied to the common electrode. The transmittance is controlled.

The storage capacitor SC is formed in an area where the pixel electrode and the common electrode overlap. The storage capacitor SC maintains the data voltage charged in the liquid crystal LC for a predetermined period.

Next, the main driver 500 receives input image data and timing signals from an external system, rearranges the input image data according to the panel 100, and outputs the input image data, and generates a timing controller for generating various control signals. 400, sequentially outputting a scan signal to the gate line according to a gate control signal generated from the data driver 300 and the timing controller 400 for changing the image data into data voltages. The gate driver 200 may be configured to be included.

As illustrated in FIG. 3, the gate driver 200, the data driver 300, and the timing controller 400 configuring the main driver 500 may be configured as one integrated circuit (IC). However, the gate driver 200 or the timing controller 400 may be configured separately from the main driver 200.

For example, the gate driver 200 may be configured independently of the main driver 500. In this case, the main driver 500 may include one integrated circuit (IC) including the remaining components. Can be. In addition, the gate driver 200 may be composed of devices of a gate in panel (GIP) method formed directly on the panel.

In addition, the timing controller 400 may be connected to the main driver 200 through a flexible substrate FPC in a state in which the timing controller 400 is mounted on a main board not shown.

That is, the main driver 500 may additionally execute the functions of the timing controller 400 and the gate driver 200 based on the function of the data driver 300 outputting a data voltage.

Hereinafter, for convenience of description, the present invention will be described with an example in which the main driver 500 includes all of the data driver 300, the gate driver 200, and the timing controller 400.

First, the gate driver 200 of the main driver 500 sequentially uses a gate control signal transmitted from the timing controller 400 to sequentially gate-on voltage to each of the g gate lines GL1 to GLg. Output a scan signal with

Here, the gate-on voltage refers to a voltage capable of turning on the switching thin film transistors connected to the gate lines. The voltage capable of turning off the switching thin film transistor is called a gate-off signal, and the gate-on signal and the gate-off signal are collectively called a scan signal.

When the thin film transistor is N type, the gate on signal is a high level voltage, and the gate off signal is a low level voltage. When the thin film transistor is a P type, the gate on signal is a low level voltage, and the gate off signal is a high level voltage.

Second, the timing controller 400 of the main driver 500 uses a timing signal input from the external system (not shown) to control the operation timing of the gate driver 200. A data control signal DCS for controlling an operation timing of the GCS and the data driver 300 is generated, and image data RGB to be transmitted to the data driver 300 is generated.

To this end, the timing controller 400 may include a receiver for receiving input image data and timing signals from the external system, a control signal generator 420 for generating various control signals, and the input image data. Rearranging the data, the data aligning unit for outputting the rearranged image data, and an output unit for outputting the control signals and the image data.

That is, the timing controller 400 rearranges the input image data inputted from the external system according to the structure and characteristics of the panel 100 and realigns the rearranged image data with the data driver 300. To send. This function may be executed in the data alignment unit.

The timing controller 400 uses the timing signals transmitted from the external system to control the data control signal DCS for controlling the data driver 300 and the gate control signal for controlling the gate driver 200. Generates a GCS and transmits the control signals to the data driver 300 and the gate driver 200. Such a function may be executed by the control signal generator 420.

The data control signals generated by the control signal generator 420 include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like. .

The gate control signals GCS generated by the control signal generator include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a gate start signal VST, and a gate clock GCLK. Etc. are included.

In particular, the control signal generator 420 generates the polarity control signal POL for two data voltages continuously output from the data driver 300 to have different polarities, thereby generating the data driver 300. To send).

Therefore, when three data voltages are output during one horizontal period in one output channel 350 of the data driver 300, the second data is output second when the first data voltage outputted first has a positive polarity. The second data voltage to be negative has a negative polarity, and the third data voltage to be output third has a positive polarity. That is, the control signal generator 420 generates the polarity control signal POL for changing the polarity of the data voltages according to the column inversion scheme.

In addition, the control signal generator 420 may have a polarity different from the polarity of the two data voltages when there are three data voltages output from one output channel 350 of the data driver 300 for one horizontal period. The data driver generates a source output enable signal SOE such that the second sub-horizontal period for outputting the data voltage is longer than the first sub-horizontal period and the third sub-horizontal period for outputting the two data voltages. Perform the function of transmitting to 300.

That is, since the data driver 300 outputs the data voltage according to the source output enable signal SOE as shown in FIG. 4, the data driver 300 outputs the data voltage in the form as shown in FIG. 6. In order to achieve this, the magnitude of the data voltage output from the data driver 300 must also be varied. Accordingly, the control signal generation unit corresponds to the first sub horizontal period corresponding to the pulse width PSWW1 of the first selection signal MUX1 and the pulse width PSWW2 of the second selection signal MUX2 shown in FIG. 4. A source output enable signal SOE having a second sub horizontal period and a third sub horizontal period corresponding to the pulse width PSWW3 of the third selection signal MUX3 to the data driver 300. send.

Here, each of the first sub horizontal period, the second sub horizontal period, and the third sub horizontal period may be greater than or equal to a period corresponding to a corresponding pulse width.

In detail, as illustrated in FIG. 5, since the output periods of the three data voltages output from the distribution unit 600 to the three data lines are different from each other, the data voltages may be adjusted accordingly. The first sub-horizontal period, the second sub-horizontal period, and the third sub-horizontal period for outputting to (600) must also be different. To this end, the control signal generator 420 has different sub-horizontal periods so that the data driver 300 sequentially outputs different data voltages to the distribution unit 600 for different periods. A source output enable signal SOE is generated and transmitted to the data driver 300.

In addition, as described above, the control signal generator 420 has a first selection signal MUX1 having a pulse width corresponding to the first sub horizontal period and a pulse width corresponding to the second sub horizontal period. And a third selection signal MUX3 having a pulse width corresponding to the second selection signal MUX2 and the third sub horizontal period.

That is, the timing controller 400 generates a source output enable signal SOE having different sub horizontal periods and a polarity control signal POL for changing the polarity of the data voltage and transmits the polarity control signal POL to the data driver 300. The select signals MUX1, MUX2, and MUX3 having pulse widths corresponding to the sub-horizontal periods are generated and transmitted to the distribution unit 600.

Third, the data driver 300 of the main driver 500 converts the digital image data transmitted from the timing controller 400 into a data voltage so that a scan signal is supplied to the gate line (1H). Each horizontal data voltage is supplied to the data lines.

That is, the data driver 300 converts the image data into the data voltage and outputs the data voltage to the data line using gamma voltages supplied from a gamma voltage generator (not shown). To this end, the data driver includes a shift register 310, a latch 320, a digital-to-analog converter (DAC) 330, and an output buffer 340.

The shift register unit 310 generates a sampling signal using data control signals SSC, SSP, etc. received from the timing controller 400.

The latch unit 320 latches the digital image data Data sequentially received from the timing controller 400, and simultaneously outputs the digital image data to the digital analog converter (DAC) 330. .

The digital-to-analog converter 330 simultaneously converts the image data transmitted from the latch unit 320 into a positive or negative data voltage and outputs the data voltage. That is, the digital-to-analog converter 330 converts the image data into positive or negative data voltages (data signals) using the polarity control signal POL transmitted from the timing controller 400. Output to lines

Hereinafter, for convenience of description, the first data voltage to the third data voltage are sequentially output for one horizontal period 1H, and the first data voltage and the third data voltage have a positive polarity. The present invention is described by taking the case where the second data voltage has negative polarity as an example.

Here, the first horizontal period 1H is a period in which the first to third data voltages are output. As shown in FIG. 6, the scan signal GLCL is output to a horizontal line to which the data voltages are output. Is equal to or greater than the pulse width of the high level voltage (gate on voltage).

The output buffer 340 transmits the positive or negative data voltage transmitted from the digital analog converter according to the source output enable signal SOE transmitted from the timing controller. Output to

In this case, the output buffer 340 includes the first data voltage and the second data in the first sub-horizontal period, the second sub-horizontal period and the third sub-horizontal period of the source output enable signal SOE. The data voltage and the third data voltage are sequentially output.

Here, the second sub-horizontal period for outputting the second data voltage having a polarity different from the polarity of the first and third data voltages may include a first sub-horizontal period and a third sub-horizontal period for outputting the first data voltage. The data voltage is formed longer than the third sub-horizon period.

In addition, the output buffer 340 is connected to the distribution unit 600 through one output channel 350. Accordingly, the first to third data voltages are sequentially output to the distribution unit 600 through the output channel 350 during one horizontal period 1H. The first sub-horizontal period corresponds to the third sub-horizontal period.

That is, the data driver 300 sequentially sequentially the first data voltage to the third data voltage during the first server horizontal period to the third sub horizontal period during one horizontal period 1H as shown in FIG. 6. Each of the first sub-horizontal period to the third sub-horizontal period corresponds to a pulse width PSWW1 to PSWW3 of each of the first to third selection signals MUX1 to MUX3.

Finally, the distribution unit 600 includes at least one switch 610 as shown in FIG. 5. The number of the switch 610 constituting the data distribution unit 400 may be variously set according to the size of the liquid crystal display panel 100 and the number of output channels of the data driver 300.

Each of the switchers 610 is connected to three data lines formed in the liquid crystal display panel 100. As shown in FIG. 5, a first data line of the three data lines is connected to a red pixel R, a second data line is connected to a green pixel G, and a third data line. Is connected to the blue pixel (B).

The configuration as described above assumes a case in which one unit pixel forming the panel 100 is composed of red pixels, green pixels, and blue pixels.

As shown in FIG. 5, each of the switchers 610 is connected to one output channel 350 formed in the data driver 300 or the main driver 500.

Each switch 610 is connected to one output channel 350 and a first data line, and is turned on according to a first selection signal MUX1 of the selection signals TR1. And a second switch TR2 connected to the one output channel 350 and a second data line and turned on according to a second selection signal MUX2 among the selection signals and the one output channel 350. And a third switch TR3 connected to a third data line, the third switch TR3 being turned on according to a third selection signal MUX3 among the selection signals, and connected to the green pixel G. Is formed between the first data line connected with the red pixel and the third data line connected with the blue pixel.

Therefore, the first data voltage output through the first switch TR1 is a red data voltage, the second data voltage output through the second switch TR2 is a green data voltage, and the third switch. The third data voltage output through TR3 is a blue data voltage.

Here, the polarity of the first data voltage output to the first data line through the first switch TR1 according to the first selection signal MUX1 and the third according to the third selection signal MUX3. The polarity of the third data voltage output to the third data line through the switch TR3 is output to the second data line through the second switch TR2 according to the second selection signal MUX2. 2 It is formed differently from the polarity of the data voltage.

In addition, as shown in FIG. 6, the pulse width of the second selection signal MUX2 is greater than the pulse width of the first selection signal MUX1 and the pulse width of the third selection signal MUX3. have.

In the following, the liquid crystal display driving method according to the present invention, as described above, is described. In the following description, the content duplicated with the above-described content will be briefly described or omitted.

The liquid crystal display driving method according to the present invention converts image data into data voltages, divides one horizontal period into a plurality of subhorizontal periods having different periods, one for each subhorizontal period through one output channel. Outputting a plurality of selection signals having a pulse width corresponding to each of the sub-horizontal periods, and outputting the data voltages of the sub-horizontal periods from the one output channel 350; Switching according to the selection signals and sequentially outputting different data lines formed on the panel.

First, the timing controller 400 of the main driver 500 generates and transmits the source output enable signal SOE to the data driver 300, and generates the selection signals MUX1 to MUX3. To the distribution unit.

Next, the data driver 300 outputs three data voltages during one horizontal period during the sub horizontal period corresponding to each of the pulse widths of the selection signals using the source output enable signal SOE. In the following, the present invention will be explained as 121 clocks CLK are output during the one horizontal period.

Finally, the distribution unit 600 sequentially outputs the three data voltages to corresponding data lines according to the selection signals.

The first selection signal MUX1 is converted to a high level after the first delay time PSWT corresponding to 10 CLK after the start of one horizontal period, and is output at a first pulse width PSWW1 corresponding to 15 CLK. Accordingly, the first switch TR1 is turned on so that the first data voltage RED is output to the first data line. Therefore, the first data voltage may be charged in the pixel for a time corresponding to about 25 CLK.

The second selection signal MUX2 is output with the second pulse width PSWW2 corresponding to 30CLK after the second delay time PSWG1 corresponding to 10CLK after the output of the first selection signal MUX1. Accordingly, the second switch TR2 is turned on so that the second data voltage RED is output to the second data line. Accordingly, the second data voltage may be charged in the pixel for a time corresponding to about 30 CLK.

The third selection signal MUX3 is output with a third pulse width PSWW3 corresponding to 25 CLK after the third delay time PSWG2 corresponding to 15 CLK after the output of the second selection signal MUX2. Accordingly, the third switch TR3 is turned on so that the third data voltage BLUE is output to the third data line. In FIG. 6, each of SNT1 and SNT2 may include a ground signal and a polarity switching signal.

The present invention as described above, by setting the timing (pulse width) of each of the three selection signals (MUX1 to MUX3) that can switch the three switches to different sizes, the charging time of the green data voltage By increasing the size, the luminance decrease can be minimized.

That is, the present invention outputs between the output periods of the red data voltage and the blue data voltage, and increases the output time of the green data voltage having a polarity different from that of the red data voltage and the blue data voltages, thereby increasing the holding time margin ( By securing the Green Holding Time Margin, it is possible to solve the luminance deterioration problem caused by the lack of the holding time of the green data voltage in the conventional liquid crystal display.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: panel 200: gate driver
300: data driver 400: timing controller
500: main driver 600: distribution

Claims (10)

A panel in which pixels are formed at intersections of the gate lines and the data lines;
Convert image data into data voltages, divide one horizontal period into a plurality of sub-horizontal periods having different periods, and output one data voltage for each of the sub-horizontal periods through one output channel; A main driver for outputting a plurality of selection signals having a pulse width corresponding to each of the two; And
A distribution unit for sequentially outputting data voltages input from the one output channel to the sub-horizontal periods according to the selection signals and sequentially outputting the data voltages to different data lines formed in the panel;
When the data voltages are three, the second sub-horizontal period in which the data voltages having polarities different from the polarities of the two data voltages are output is the first sub-horizontal period and the third sub-horizontal period in which the two data voltages are output. Longer liquid crystal display device. The method of claim 1,
And two data voltages continuously output from the main driver have different polarities. delete The method of claim 1,
The selection signals,
A first selection signal having a pulse width corresponding to the first sub horizontal period;
A second selection signal having a pulse width corresponding to the second sub horizontal period; And
And a third selection signal having a pulse width corresponding to the third sub horizontal period. The method of claim 1,
The distribution unit includes at least one switch,
The switch,
A first switch connected to the one output channel and the first data line and turned on according to a first selection signal of the selection signals;
A second switch connected to the one output channel and the second data line and turned on according to a second selection signal of the selection signals; And
A third switch connected to the one output channel and a third data line and turned on according to a third selection signal among the selection signals,
And the second data line is formed between the first data line and the third data line. The method of claim 5,
A polarity of a first data voltage output through the first switch to the first data line according to the first selection signal, and output to the third data line through the third switch according to the third selection signal The polarity of the third data voltage is different from the polarity of the second data voltage output to the second data line through the second switch according to the second selection signal. The method of claim 5,
And the pulse width of the second selection signal is greater than the pulse width of the first selection signal and the pulse width of the third selection signal. The method of claim 5,
The first data voltage output through the first switch is a red data voltage, the second data voltage output through the second switch is a green data voltage, and the third data voltage output through the third switch is blue. Liquid crystal display device characterized in that the data voltage. Convert image data into data voltages, divide one horizontal period into a plurality of sub-horizontal periods having different periods, and output one data voltage for each of the sub-horizontal periods through one output channel; Outputting a plurality of selection signals having a pulse width corresponding to each of the two; And
Switching the data voltages input at each sub-horizontal period from the one output channel according to the selection signals and sequentially outputting the data voltages to different data lines formed in the panel.
When the data voltages are three, the second sub-horizontal period in which the data voltages having polarities different from the polarities of the two data voltages are output is the first sub-horizontal period and the third sub-horizontal period in which the two data voltages are output. A method of driving a liquid crystal display device, characterized in that it is longer. The method of claim 9,
The pulse width of the second selection signal corresponding to the second sub horizontal period is a pulse width of the first selection signal corresponding to the first sub horizontal period and the pulse of the third selection signal corresponding to the third sub horizontal period. A liquid crystal display device driving method, characterized in that greater than the width.

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