KR101087650B1 - Arrangement structure of light emitting cell for arrays forwardly interconnected - Google Patents

Abstract

PURPOSE: A connection structure of a forward serially connected light emitting cell array is provided to prevent defects in a chip mounting process and simplify a process by structuralizing a P type semiconductor and an N type semiconductor of a light emitting cell with a simple metal thin film. CONSTITUTION: A plurality of light emitting cells(100) is arranged on a substrate with a physically separated structure. A light emitting cell emits light by the PN junction of a P type semiconductor(120) and an N type semiconductor(140). The N type semiconductor is formed on the substrate with a structure with a plurality of electrically isolated islands. A wiring(300) electrically connects the P type semiconductor and the N type semiconductor. The wiring is formed on the substrate with a metal thin film type.

Description

Connection structure of forward-connected light-emitting cell array {ARRANGEMENT STRUCTURE OF LIGHT EMITTING CELL FOR ARRAYS FORWARDLY INTERCONNECTED}

The present invention relates to a connection structure of a light emitting cell array connected in a forward serial connection, and more particularly, a forward serial that can improve reliability by allowing each cell of a light emitting cell array to be driven by direct current or alternating current by a simple metallization process. A connection structure of a connected light emitting cell array is provided.

In general, a light emitting diode (LED) has an N-type semiconductor having electrons as its major carriers and a P-type semiconductor having holes as its main carriers. A photoelectric conversion semiconductor device having a PN junction, which emits light by recombination of electrons and holes diffused into the matching region.

That is, the light emitting diode is a current injection type light emitting device, and when a voltage is applied to both opposite poles in a forward direction, electrons injected from a cathode and holes injected from an anode are generated. Since the devices emit light by recombination with each other by being diffused near the matching layer or the active layer, they are driven with a relatively large forward current of several tens of mA at a low forward voltage of 5 V or less.

Such a light emitting diode is widely used as a light source as well as a display device, and has a shorter power consumption and a longer life than conventional incandescent lamps or fluorescent lamps, thereby replacing the existing lighting to expand its use area for new lighting applications.

Recently, the lighting field requires a high power light emitting diode lamp, and in order to realize a high power lamp, it is possible to increase the matching area of the light emitting diode element, for example, to make a light emitting diode lamp of 20W. There are two ways to do this.

First, there is a method of implementing a large area chip by simply increasing the area of the matching surface of the chip or by connecting several unit chips in parallel. In this case, since the unit LED chip is usually driven at about 4V, a power supply unit having a large current capacity of 5A or more is required to realize a 20W LED lamp. In the case of such a low voltage / high current system, a high voltage in terms of energy efficiency and device size is required. There are disadvantages compared to low current systems. In addition, excessively increasing the cell area in a chip has a disadvantage in that the rated current decreases due to the nonuniformity of the material (property) and the spreading resistance in the electrode.

As another method, a plurality of chips or unit light emitting cells are connected in series to implement a high voltage driving chip array or a light emitting cell array. In this case, when driving at 100V, the operating current is about 200mA to achieve 20W, which is much more advantageous in terms of power supply size and efficiency. Therefore, when making a general lighting system, an array chip is used in which individual LED chips are connected in series to drive at high voltage, or unit light emitting cells are connected in series to enable high voltage driving.

Hereinafter, a connection structure of a conventional light emitting cell array will be described with reference to the accompanying drawings.

1- (a) is a circuit diagram showing a connection structure of a conventional light emitting cell array.

1- (b) is a sectional view showing a connection structure of a conventional light emitting cell array.

1- (c) is a plan view showing a connection structure of a conventional light emitting cell array.

Referring to FIG. 1, a plurality of light emitting cells 10 are disposed on a substrate 1, and a P-electrode 12 and an N-electrode 14 are formed on the light emitting cells 10. The P-electrode 12 and the N-electrode 14 of the adjacent light emitting cells 10 are electrically connected to each other through the air bridge wiring 30 to form a light emitting cell array in which a plurality of light emitting cells 10 are connected in series. The plurality of light emitting cell arrays are connected in anti-parallel to form a circuit. In the two light emitting cell arrays having the above structure, when the external AC power is connected, the two light emitting cell arrays alternately emit light corresponding to the half cycle of the alternating current.

2- (a) is a circuit diagram showing a connection structure of a light emitting cell array as another conventional example.

2- (b) is a plan view showing in plan view a connection structure of a light emitting cell array as another conventional example.

Referring to FIG. 2, light emitting cell arrays including a plurality of light emitting cells 10 are electrically connected to each other through an air bridge wiring 30. Here, six light emitting cell arrays are shown, and the light emitting cell arrays of the first column, the third column, and the fifth column are connected in series to each other to form one first series array, and the second column and the fourth column. And the light emitting cell arrays of the sixth column are connected in series to each other to form another second serial array, and the first and second serial arrays are connected in reverse parallel to each other. In the light emitting cell arrays having the above-described structure, when the external AC power is connected, the light emitting cell arrays of the first, third, and fifth rows emit light for half a period, and the light emitting cell arrays of the second, fourth, and sixth rows emit light for the other half cycle. Done. Thus, under alternating current, the arrays alternately turn on and off each other to emit light.

However, in the conventional forward serially connected light emitting cell array as described above, each light emitting cell 10 should be physically separated from the substrate, and the P-electrode 12 and the N-electrode ( As shown in Fig. 1- (b), the wiring of 14) must be connected by using a metal conductor in an air bridge connection method so that a short circuit does not occur at the edge junction 13 of the PN match, which makes the manufacturing process complicated. And there was a problem that can cause a defect in the mounting process of the chip. That is, in such a case, an air bridge wiring for a bridge-type connection structure is required, and one of the most common failures of the defects of the semiconductor device is a wiring failure.

In addition, the air bridge wiring 30 connecting the P-electrode 12 and the N-electrode 14 of the light emitting cell 10 is easily disconnected due to external pressure since portions other than the contact portion float in the air. There is a problem that may cause a short circuit by deformation by such an external pressure.

In addition, as shown in FIG. 2, when a large number of light emitting cell arrays are connected, the overall size of the light emitting device increases and the number of processes such as connecting the air bridge wiring 30 increases as the light emitting cells 10 are connected to each other. There is a problem that a short circuit may occur in a section in which the array connection wirings 50 connecting the respective light emitting cell arrays cross each other.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a connection structure of a forward serially connected light emitting cell array which can simplify the manufacturing process and prevent defects during chip mounting.

Another object of the present invention is to provide a connection structure of a forward serially connected light emitting cell array which can prevent the wires connecting the electrodes of the light emitting cells from being disconnected and shorted by an external pressure.

It is still another object of the present invention to reduce the number of wiring connection processes when connecting a plurality of light emitting cell arrays, and to prevent the risk of short circuit caused by a cross section between wirings connecting each light emitting cell array. It is to provide a connection structure of the array.

The present invention for achieving the object as described above, in the connection structure of the light emitting cell array in which a plurality of light emitting cells arranged on the substrate is connected in series in the forward direction, one side is bonded to the substrate and the other side is bent to form a space portion A PN-matching light emitting cell consisting of a P-shaped semiconductor having a shape and a N-shaped semiconductor having a straight shape inserted to protrude a predetermined length from the space portion of the P-type semiconductor; And a wire for electrically connecting the P-type semiconductors and the N-type semiconductors of the plurality of light-emitting cells to form a forward serial array.

' 형상으로 이루어지는 것을 특징으로 한다.According to a preferred embodiment, the P-type semiconductor has a side cross section '

'Is formed in a shape.

According to a preferred embodiment, the wiring is characterized in that the portion of the end of the P-type semiconductor and the N-type semiconductor facing each other in adjacent light emitting cells by a predetermined length is matched in the form of a metal thin film on the substrate.

' 형상으로 이루어지는 것을 특징으로 한다.According to a preferred embodiment, the wiring has a side cross section '

'Is formed in a shape.

According to a preferred embodiment, the wiring is formed in a metal thin film form on the substrate by wrapping a portion of the ends of the P-type semiconductor and the N-type semiconductor of the adjacent light emitting cells at a predetermined distance on both sides of the forward serial array It is characterized by matching.

' 형상으로 이루어지는 것을 특징으로 한다.According to a preferred embodiment, the wiring has a side cross section '

'Is formed in a shape.

According to the present invention configured as described above, since the wiring is structured so that the P-type semiconductor and the N-type semiconductor of the light emitting cell can be connected in the form of a simple metal thin film, the process can be simplified and defects can be prevented in the chip mounting process. There is an advantage to prevent the disconnection and short circuit of the wiring by the external pressure.

In addition, the number of wiring connection processes of the light emitting cell arrays arranged in a plurality of rows is reduced, and there is an advantage of preventing a short circuit risk due to a cross section between the wirings connecting the arrays.

In addition, since the edge junction of the N-type semiconductor inserted into the space portion of the P-type semiconductor is protected from the outside in the structure where the light emitting cell is PN matched, deterioration and failure of characteristics due to contamination of the package material during mounting process or use. There is an advantage that can be prevented.

1- (a) is a circuit diagram showing a connection structure of a conventional light emitting cell array.
1- (b) is sectional drawing which shows the connection structure of the conventional light emitting cell array.
1- (c) is a plan view showing a connection structure of a conventional light emitting cell array.
2- (a) is a circuit diagram showing a connection structure of a light emitting cell array in another conventional example.
2- (b) is a plan view showing a connection structure of a light emitting cell array as another conventional example.
3- (a) is a circuit diagram showing a connection structure of a light emitting cell array connected in a forward series according to an embodiment of the present invention.
3- (b) is a cross-sectional view showing a connection structure of a light emitting cell array connected in a forward series according to an embodiment of the present invention.
3- (c) is a plan view showing a connection structure of a forward-connected light-emitting cell array according to an embodiment of the present invention.
Fig. 4- (a) is a circuit diagram showing a connection structure of a forward-sequentially connected light emitting cell array according to another embodiment of the present invention.
4- (b) is a plan view showing a connection structure of a light emitting cell array connected in a forward series according to another embodiment of the present invention.
Fig. 5- (a) is a circuit diagram showing a connection structure of a forward-sequentially connected light emitting cell array according to another embodiment of the present invention.
Fig. 5- (b) is a plan view showing a connection structure of a forward-connected light-emitting cell array according to still another embodiment of the present invention.
6 is a process diagram illustrating a method of manufacturing a light emitting cell array that is connected in series in a forward direction according to an exemplary embodiment of the present invention.

Hereinafter, a preferred embodiment of the present invention will be described in more detail. The features and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiment.

Prior to this, the terms or words used in the present specification and claims are defined in the technical spirit of the present invention on the basis of the principle that the inventor can appropriately define the concept of the term in order to explain his invention in the best way. It must be interpreted to mean meanings and concepts.

In addition, it will be apparent to those skilled in the art that the present invention may be practiced without specific details such as specific components in the following description. Therefore, a detailed description of the general configuration for the governor well known in the art will be omitted.

≪ Embodiment 1 >

3- (a) is a circuit diagram showing a connection structure of a light emitting cell array connected in a forward series according to an embodiment of the present invention.

3- (b) is a cross-sectional view illustrating a connection structure of a light emitting cell array connected in a forward series according to an exemplary embodiment of the present invention.

3- (c) is a plan view illustrating a connection structure of a light emitting cell array connected in a forward series according to an exemplary embodiment of the present invention.

The present invention with reference to FIG. 3 includes a plurality of light emitting cells 100 arranged in a physically separated structure on a substrate 1 and a wiring 300 for electrically connecting the light emitting cells 100. The light emitting cell 100 and the wiring 300 have structural features that are more advanced than those of the related art, and will be described in detail with reference to the accompanying drawings.

First, the light emitting cell 100 will be described.

The light emitting cell 100 emits light by PN matching the P-type semiconductor 120 and the N-type semiconductor 140, in order to explain the structural features of the light emitting cell 100 in more detail FIG. Referring to b) as follows.

' 형상으로 절곡되어 일측은 기판(1)상에 접합되고 타측은 N형 반도체(140) 상에 접합되는 구조를 가진다. 따라서 일자형의 N형 반도체(140)가 P형 반도체(120)의 공간부에 삽입된 것과 같은 구조를 가지는데, N형 반도체(140) 상에 금속전극(미도시)을 형성시키기 위해 상기 N형 반도체(140)의 일부를 P형 반도체(120)의 공간부 밖으로 돌출시키는 것이다.Referring to FIG. 3- (b), when the N-type semiconductor 140 having a plurality of island structures that are electrically separated from each other on the substrate 1 is first formed, the P-type semiconductor 120 has a side to achieve PN matching. Cross section

'Is bent into a shape and one side is bonded to the substrate 1 and the other side has a structure bonded to the N-type semiconductor (140). Therefore, the straight N-type semiconductor 140 has the same structure as that inserted into the space portion of the P-type semiconductor 120, and the N-type to form a metal electrode (not shown) on the N-type semiconductor 140 A portion of the semiconductor 140 protrudes out of the space portion of the P-type semiconductor 120.

Here, the edge junction portion 142 of the N-type semiconductor 140 inserted into the space portion of the P-type semiconductor 120 is surrounded by the space portion of the P-type semiconductor 120 and is not exposed to the outside so that it is completely isolated from the wiring. It becomes a structure. Therefore, in the PN-matched structure, the edge junction portion 142 of the N-type semiconductor 140 is provided so that the structure is not exposed to the outside, so that the wiring structure of the wiring does not need to be bridged as in the prior art, and the process operation is simple and reliable. The wiring structure in the form of a metal thin film can be applied.

According to a preferred embodiment, a transparent electrode such as indium thin oxide (ITO) should be formed on the P-type semiconductor 120, and an ohmic metal should also be formed at the interface between the N-type semiconductor 140 and the wiring 300. Since the above items correspond to the obvious configurations that can be sufficiently omitted in the related art, they will not be described separately in the present invention.

Next, the wiring 300 will be described.

The wiring 300 electrically connects the P-type semiconductor 120 and the N-type semiconductor 140 of the plurality of light emitting cells 100 so that the light emitting cells 100 are formed in a forward serial array. To describe the structural features of the wiring 300 in more detail with reference to FIG. 3- (b) as follows.

' 형상으로 이루어지는 것이 바람직하다.The wiring is preferably matched in the form of a metal thin film on the substrate 1 by wrapping a portion of the ends of the P-type semiconductor 120 and the N-type semiconductor 140 facing each other in the adjacent light emitting cells 100, According to the exemplary embodiment with reference to FIG. 3- (b), the side surface of the wiring 300 is

It is preferable that it is formed in a 'shape.

Here, the metal junction portion of the wiring 300 which surrounds a portion of the end of the N-type semiconductor 140 is not connected to the P-type semiconductor 120 formed on the N-type semiconductor 140 so that the P-type semiconductor 120 Must be formed at regular intervals.

' 형상으로 이루어지는 것이 바람직하다.The wiring 300 surrounds a portion of the ends of the P-type semiconductor 120 and the N-type semiconductor 140 of the adjacent light emitting cells 100 by a predetermined length from the external electrodes formed at predetermined intervals on both sides of the forward serial array. It is preferable to match the shape of the metal thin film on (1). According to the embodiment of FIG. 3- (b), the side surface of the wiring 300 is'

It is preferable that it is formed in a 'shape.

In this case, as described above, a portion of the wiring 300 which surrounds a part of the end of the N-type semiconductor 140 is not in contact with the P-type semiconductor 120 matched to the upper portion of the N-type semiconductor 140. It is formed to surround a portion of the N-type semiconductor 140 at a predetermined interval from the type semiconductor (120).

≪ Embodiment 2 >

4A is a circuit diagram illustrating a connection structure of a light emitting cell array connected in a forward series according to another embodiment of the present invention.

4- (b) is a plan view illustrating a connection structure of a light emitting cell array connected in a forward series according to another exemplary embodiment of the present invention.

Referring to FIG. 4, a plurality of light emitting cells 100 formed on a substrate 1 correspond to a first array a _n connected in series in a forward direction and a light emitting cell 100 of the first array a _n . The second array (b _n ) consisting of a number of inverted parallel to each other has a structure, the adjacent light emitting cells 100 of the first array (a _n ) and the second array (b _n ) have different polarities. connected in series with each other, and the first array (a _n) light emitting cells a _1, a _2, a ₃ and a second array (b _n) light emitting cell b _1, b _2, b ₃ of each other are connected in anti-parallel.

Therefore, the light emitting cells of the first array a _n and the second array b _n connected in anti-parallel in the circuit diagram of FIG. The light is emitted in half cycles. First, during a half cycle in which a positive voltage is applied to the A stage and a negative voltage is applied to the B stage, the first array a _n is forward biased so that the light emitting cells a ₁ and a ₂ , a ₃ , forward current flows to emit light. On the contrary, when (-) voltage is applied to A stage and (+) voltage is applied to B stage, the second array (b _n ) is forward biased to emit light cells b ₁ , Forward current flows to b ₂ and b ₃ to emit light.

Wherein said first array (a _n) of each light emitting cell, a _1, a _2, of a ₃ is preferably a second array respectively connected in anti-parallel with each light emitting cell b _1, b _2, b ₃ of (b _n) However, when one light emitting cell is turned on, a corresponding antiparallel light emitting cell is turned off and becomes a resistor, so that voltage is uniformly distributed in each light emitting cell of the first and second arrays. .

In addition, since the charges charged in the PN matching of the light emitting cells that change from the on state to the off state can be used in the corresponding inverse parallel light emitting cells that change from the off state to the on state, it is advantageous in terms of utilization of reactive power.

When the light emitting cell structure of the present embodiment is used, the metallization process and the anti-parallel light emitting cell wiring process are simultaneously performed to form the interconnection between the light emitting cells of the serial connection array, thereby simplifying the wiring process. There is an effect that the electrodes are formed at the same time.

Third Embodiment

5A is a circuit diagram illustrating a connection structure of a light emitting cell array connected in a forward series according to another embodiment of the present invention.

5- (b) is a plan view illustrating a connection structure of a light emitting cell array connected in a forward series according to another embodiment of the present invention.

Referring to FIG. 5, the first array a _n and the second array b _n connected in series with a plurality of light emitting cells are connected in parallel to form one array G, and the array G is Many are connected in series and are composed of multiple rows.

Arrangement (G) as described above is arranged in a plurality of horizontally side by side as shown, by adjoining each other by extending the wiring 300 in the anti-parallel connection of the first array (a _n ) and the second array (b _n ) The arrangement G may be connected without overlapping the wiring 300.

Through this, the number of wiring connection processes of arrays arranged in a plurality of rows is reduced, and a cross section between wirings connecting each array does not occur, thereby preventing a risk of short circuit.

6 is a process diagram illustrating a method of manufacturing a light emitting cell array connected in series in a forward direction according to an exemplary embodiment of the present invention.

A method of manufacturing a forward-connected light emitting cell array of the present invention with reference to FIG. 6 is as follows.

First, an N-type semiconductor layer (electron injection layer) 140 is formed on the substrate 1, and then an isolated island structure is formed through an etching process, and the N-type semiconductor layer 140 is formed. A P-type semiconductor layer (hole injection layer 120) having opposing polarity is formed thereon.

Here, the order of forming the N-type semiconductor layer 140 and the P-type semiconductor layer 120 may be changed, and nitride (AlN or Si) may be easily grown on the substrate 1 so that the first semiconductor layer (here, the N-type semiconductor layer) is easily grown. _x N _y ) or a buffer layer is formed on the substrate. For example, in the case of GaN LEDs, undoped GaN is formed on the substrate.

Next, a transparent electrode layer 160 having an ohmic match with relatively low contact resistance is formed on the P-type semiconductor, and then the P-type semiconductor layer 120 and the transparent electrode layer 160 are N-type. The etching process is performed such that the light emitting cell is separated from other light emitting cells on the semiconductor layer 140.

In this case, ITO and Ni / Au may be used as the transparent electrode layer 160 and the ohmic junction layer 170 for the P-type GaN semiconductor, respectively.

Next, an ohmic electrode layer 180 is formed on the N-type semiconductor layer 140. As an ohmic matching material for the N-type GaN semiconductor, Ti, Ti / Au, or the like may be used.

Finally, a wiring layer 300 is formed to connect the P-type semiconductor layer 120 of each light emitting cell to the N-type semiconductor layer 140 of the light emitting cell adjacent to each other. It will be prepared. Here, Al, Cu, or the like may be used as a wiring material for transferring current between each light emitting cell.

The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the claims that follow may be better understood. It should be appreciated by those skilled in the art that the above-described concepts and specific embodiments of the present invention can be used immediately as a basis for designing or modifying other shapes for carrying out similar objects to the present invention.

In addition, the above-described embodiment is only one embodiment according to the present invention, and various modifications and changes may be made by those skilled in the art within the scope of the technical idea of the present invention. These various modifications and changes are also within the scope of the technical idea of the present invention, and will be included in the claims of the present invention described below.

1: substrate 10: light emitting cell
12: P-electrode 14: N-electrode
13: PN mating edge junction 30: Airbridge wiring
50: array connection wiring
100: light emitting cell 300: wiring
120: P-type semiconductor 140: N-type semiconductor
142: N-type semiconductor edge junction G: arrangement
160: transparent electrode layer 170: ohmic bonding layer
180: ohmic electrode layer

Claims (6)

In the connection structure of a light emitting cell array in which a plurality of light emitting cells arranged on a substrate is connected in series in the forward direction,
A PN-matching light emitting cell comprising one side bonded to a substrate and the other side consisting of a P-type semiconductor having a shape bent to form a space portion and a N-shaped semiconductor having a straight shape inserted to protrude a predetermined length from the space portion of the P-type semiconductor;
And a wiring for electrically connecting the P-type semiconductors and the N-type semiconductors of the plurality of light-emitting cells to form a forward serial array. The method of claim 1,
The P-type semiconductor has a side cross section '

A connection structure of a forward serially connected light emitting cell array, characterized in that it is formed in a shape. The method of claim 1,
And the wirings are arranged in a metal thin film form on a substrate by wrapping a portion of the ends of the P-type semiconductor and the N-type semiconductor facing each other in adjacent light-emitting cells. The method of claim 3, wherein
The wiring has a side cross section '

A connection structure of a forward serially connected light emitting cell array, characterized in that it is formed in a shape. The method of claim 1,
The wiring may be formed in a metal thin film form on a substrate by wrapping a portion of the ends of the P-type semiconductors and the N-type semiconductors of adjacent light emitting cells at a predetermined distance on both sides of the forward series array. Connection structure of forward serially connected light emitting cell array. The method of claim 5.
The wiring has a side cross section '

A connection structure of a forward serially connected light emitting cell array, characterized in that it is formed in a shape.

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