KR100716645B1 - Light emitting device having vertically stacked light emitting diodes - Google Patents

Abstract

A light emitting device having light emitting diodes stacked vertically is disclosed. The light emitting device includes a lower N-type semiconductor layer located on the substrate. The P-type semiconductor layer is positioned on one region of the lower N-type semiconductor layer, and the upper N-type semiconductor layer is positioned on one region of the P-type semiconductor layer. On the other hand, the lower active layer is interposed between the lower N-type semiconductor layer and the P-type semiconductor layer, and the upper active layer is interposed between the P-type semiconductor layer and the upper N-type semiconductor layer. Accordingly, a light emitting device in which a lower light emitting diode including a lower N-type semiconductor layer, a lower active layer, and a P-type semiconductor layer, and an upper light emitting diode including a P-type semiconductor layer, an upper active layer, and an upper N-type semiconductor layer are vertically stacked. Is provided. Therefore, the light output per unit area is improved as compared with the conventional light emitting device, and the chip area of the light emitting device for obtaining the same light output as the conventional light emitting device can be reduced.

Light emitting devices, light emitting diodes, codoped layers, separating layers, semi-insulating layers.

Description

LIGHT EMITTING DEVICE HAVING VERTICALLY STACKED LIGHT EMITTING DIODES}

1 and 2 are a plan view and a cross-sectional view for explaining a light emitting device according to an embodiment of the present invention.

3 is a partial cross-sectional view for describing a light emitting device having a plurality of light emitting cells according to an embodiment of the present invention.

4 is a circuit diagram illustrating a light emitting device having a plurality of light emitting cells according to an embodiment of the present invention.

5 is a partial cross-sectional view for describing a light emitting device having a plurality of light emitting cells according to another embodiment of the present invention.

6 is a circuit diagram illustrating a light emitting device having a plurality of light emitting cells according to another exemplary embodiment of the present invention, and FIG. 7 is an equivalent circuit diagram of FIG. 6.

8 and 9 are a plan view and a cross-sectional view for describing a light emitting device according to another embodiment of the present invention.

10 is a partial cross-sectional view illustrating a light emitting device having a plurality of light emitting cells according to another embodiment of the present invention.

11 is a circuit diagram illustrating a light emitting device having a plurality of light emitting cells according to another embodiment of the present invention.

The present invention relates to a light emitting device, and more particularly to a light emitting device having light emitting diodes stacked vertically.

Gallium nitride (GaN) series light emitting diodes have been applied and developed for about 10 years. GaN-based LEDs have changed the LED technology considerably and are currently used in a variety of applications, including color LED displays, LED traffic signals and white LEDs.

Recently, high-efficiency white LEDs are expected to replace fluorescent lamps. In particular, the efficiency of white LEDs has reached a level similar to that of conventional fluorescent lamps.

Two major approaches are being attempted to improve LED efficiency. The first is to increase the internal quantum efficiency determined by the crystal quality and epilayer structure, and the second is to increase the light extraction efficiency.

Internal quantum efficiency is currently 70-80%, so there is not much room for improvement, but light extraction efficiency has much room for improvement. Improvement of light extraction efficiency has become a major problem to remove the internal light loss by internal reflection.

The light emitting diode, which prevents internal reflection and improves light extraction efficiency, is called Fuji, etc. under the title of "Increase in the extraction efficiency of GaN-Based ligth emitting diodes via surface roughening". It was disclosed in Applied physics letters, Vol84, N6, p855-857 by Fujii et al.

The light emitting diode is stacked on an sapphire substrate with an N-type semiconductor layer, an active layer and a P-type semiconductor layer, bonding the semiconductor layers on a submount and using laser lift-off (LLO) technology. After separating the semiconductor layers from the substrate, it is formed by roughening the surface of the N-type semiconductor layer. By roughening the surface of the N-type semiconductor layer, it is possible to improve the extraction efficiency of light emitted to the outside through the N-type semiconductor layer.

However, such light extraction efficiency improvement is limited, so that the chip area is increased to obtain the required light output per unit chip. An increase in chip area leads to an increase in manufacturing cost per chip. Therefore, there is a need for a new light emitting diode capable of increasing light output in the same unit chip area.

On the other hand, the light emitting diode is repeatedly turned on and off in accordance with the direction of the current under AC power. Therefore, when the light emitting diode is directly connected to an AC power source, the light emitting diode does not emit light continuously and is easily damaged by reverse current.

In order to solve the problem of the light emitting diode, a light emitting diode that can be directly connected to a high voltage AC power source is disclosed in International Publication No. WO 2004/023568 (Al) "Light-Emitting Device Having Light-Emitting Components". EMITTING ELEMENTS, which was disclosed by SAKAI et. Al.

According to WO 2004/023568 (Al), LEDs (light emitting cells) are two-dimensionally connected in series on an insulating substrate such as a sapphire substrate to form an LED array. These two LED arrays are connected in anti-parallel on the sapphire substrate. As a result, a single chip light emitting device that can be driven by an AC power supply is provided.

In such a light emitting device, since the LED arrays alternately operate under an AC power source, the light output is considerably limited as compared with the case where the light emitting cells operate simultaneously. Therefore, it is further desired to improve the light output per unit area in such a light emitting device.

An object of the present invention is to provide a light emitting device capable of increasing the light output per unit area.

Another object of the present invention is to provide a light emitting device that can be driven under an AC power source, and to provide a light emitting device having improved light output.

In order to achieve the above technical problem, the present invention provides a light emitting device having light emitting diodes stacked vertically. The light emitting device according to an aspect of the present invention includes a lower N-type semiconductor layer positioned on a substrate. A P-type semiconductor layer is positioned on one region of the lower N-type semiconductor layer, and an upper N-type semiconductor layer is positioned on one region of the P-type semiconductor layer. Meanwhile, a lower active layer is interposed between the lower N-type semiconductor layer and the P-type semiconductor layer, and an upper active layer is interposed between the P-type semiconductor layer and the upper N-type semiconductor layer. Accordingly, the lower light emitting diode including the lower N-type semiconductor layer, the lower active layer, and the P-type semiconductor layer, and the upper light emitting diode including the P-type semiconductor layer, the upper active layer, and the upper N-type semiconductor layer are vertical. The laminated light emitting device can be provided. Therefore, the light output per unit area is increased as compared with the conventional light emitting device.

A lower N-type electrode may be formed on another region of the lower N-type semiconductor layer, and a P-type electrode may be formed on another region of the P-type semiconductor layer. In addition, an upper N-type electrode may be formed on the upper N-type semiconductor layer. Accordingly, the light emitting device may be driven by connecting the P-type electrode to one terminal of an external power source and connecting the lower and upper N-type electrodes to another terminal.

Meanwhile, a codoped layer may be interposed between the P-type semiconductor layer and the upper active layer. The co-doped layer is a semiconductor layer doped with N-type and P-type ions, for example, may be gallium nitride doped with Mg and Si, or Mg and In. The dope layer improves the crystal quality of the upper active layer.

The light emitting device according to the embodiment of the present invention includes a plurality of light emitting cells positioned on the substrate. Each of the light emitting cells includes a lower N-type semiconductor layer on the substrate. A P-type semiconductor layer is positioned on one region of the lower N-type semiconductor layer, and an upper N-type semiconductor layer is positioned on one region of the P-type semiconductor layer. Meanwhile, a lower active layer is interposed between the lower N-type semiconductor layer and the P-type semiconductor layer, and an upper active layer is interposed between the P-type semiconductor layer and the upper N-type semiconductor layer. Accordingly, the lower light emitting diode including the lower N-type semiconductor layer, the lower active layer, and the P-type semiconductor layer, and the upper light emitting diode including the P-type semiconductor layer, the upper active layer, and the upper N-type semiconductor layer are vertical. It is possible to provide a plurality of stacked light emitting cells. Accordingly, a light emitting device capable of electrically connecting the light emitting cells to be driven under an AC power source and providing a light emitting device having an increased light output per unit area compared to a conventional light emitting device may be provided.

In some embodiments of the present invention, each of the light emitting cells may further include a lower N-type electrode formed on another region of the lower N-type semiconductor layer. In addition, a P-type electrode may be formed on another region of the P-type semiconductor layer, and an upper N-type electrode may be formed on the upper N-type semiconductor layer. The lower N-type electrode and the upper N-type electrode of each light emitting cell may be electrically connected to the P-type electrode of a neighboring light emitting cell. Therefore, the P-type electrode of each light emitting cell is electrically connected to the lower N-type electrode and the upper N-type electrode of the neighboring other light emitting cells. Accordingly, an array in which the light emitting cells are connected in series may be provided.

In another embodiment of the present invention, in addition to the lower N-type electrode, the P-type electrode, and the upper N-type electrode, another P-type electrode may be formed on another region of the P-type semiconductor layer. The lower N-type electrode of each light emitting cell is connected to the P-type electrode of the neighboring light emitting cell, and the other P-type electrode of each light emitting cell is connected to the upper N-type electrode of the neighboring light emitting cell. In addition, the P-type electrode of each light emitting cell is connected to the lower N-type electrode of the neighboring other light emitting cells, and the upper N-type electrode of each light emitting cell is connected to the other P-type electrode of the other neighboring light emitting cells. According to the present exemplary embodiment, an array in which upper LEDs of the light emitting cells are connected in series and an array in which lower LEDs of the light emitting cells are connected in series may be provided, and the two arrays may be connected in parallel to each other. In addition, the nodes between the light emitting diodes in the one array are connected to the nodes between the light emitting diodes in the other array to enable electrically stable operation.

The light emitting device according to another aspect of the present invention includes a lower N-type semiconductor layer located on the substrate. A lower P-type semiconductor layer is positioned on one region of the lower N-type semiconductor layer, and an upper P-type semiconductor layer is positioned on one region of the lower P-type semiconductor layer. In addition, an upper N-type semiconductor layer is positioned on one region of the upper P-type semiconductor layer. Meanwhile, a lower active layer is interposed between the lower N-type semiconductor layer and the lower P-type semiconductor layer, and an upper active layer is interposed between the upper P-type semiconductor layer and the upper N-type semiconductor layer. In addition, a spacing layer is interposed between the lower P-type semiconductor layer and the upper P-type semiconductor layer. Accordingly, a lower light emitting diode including the lower N-type semiconductor layer, the lower active layer, and the lower P-type semiconductor layer, and an upper light emission including the upper P-type semiconductor layer, the upper active layer, and the upper N-type semiconductor layer. A light emitting device in which a diode is separated by a separation layer is provided.

Here, the isolation layer is a layer for electrically separating the lower light emitting diode and the upper light emitting diode, and may be, for example, an insulating layer or a semi-insulating layer having a high resistance.

The lower N-type electrode may be formed on another region of the lower N-type semiconductor layer, and the lower P-type electrode may be formed on another region of the lower P-type semiconductor layer. In addition, an upper P-type electrode may be formed on another region of the upper P-type semiconductor layer, and an upper N-type electrode may be formed on the upper N-type semiconductor layer. The lower and upper P-type electrodes may be connected to one terminal of an external power source, and the lower and upper N-type electrodes may be connected to another terminal of the external power source to drive the light emitting device. In addition, the upper and lower light emitting diodes may be respectively driven by connecting two external power sources to the lower N-type electrode and the lower P-type electrode, and the upper P-type electrode and the upper N-type electrode, respectively.

A light emitting device according to another embodiment of the present invention includes a plurality of light emitting cells located on a substrate. Each of the light emitting cells includes a lower N-type semiconductor layer on the substrate. A lower P-type semiconductor layer is positioned on one region of the lower N-type semiconductor layer, and an upper P-type semiconductor layer is positioned on one region of the lower P-type semiconductor layer. In addition, an upper N-type semiconductor layer is positioned on one region of the upper P-type semiconductor layer. A lower active layer is interposed between the lower N-type semiconductor layer and the lower P-type semiconductor layer, and an upper active layer is interposed between the upper P-type semiconductor layer and the upper N-type semiconductor layer. In addition, a separation layer is interposed between the lower P-type semiconductor layer and the upper P-type semiconductor layer. Accordingly, a lower light emitting diode including the lower N-type semiconductor layer, the lower active layer, and the lower P-type semiconductor layer, and an upper light emitting diode including the upper P-type semiconductor layer, the upper active layer, and the upper N-type semiconductor layer. May provide a plurality of light emitting cells stacked vertically.

Each of the light emitting cells may further include a lower N-type electrode formed on another region of the lower N-type semiconductor layer. Further, a lower P-type electrode is formed on another region of the lower P-type semiconductor layer, an upper P-type electrode is formed on another region of the upper P-type semiconductor layer, and an upper N on the upper N-type semiconductor layer. Type electrodes can be formed. The lower N-type electrode and the upper N-type electrode of each light emitting cell may be electrically connected to the lower P-type electrode and the upper P-type electrode of neighboring light emitting cells, respectively, to provide a light emitting cell array connected in series. According to the present embodiment, an upper series connection array in which the upper light emitting diodes are connected in series and a lower series connection array in which the lower light emitting diodes are connected in series may be provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 and 2 are a plan view and a cross-sectional view for explaining a light emitting device according to an embodiment of the present invention, respectively.

1 and 2, the lower N-type semiconductor layer 25 is positioned on the substrate 21. The substrate 21 may be, for example, a sapphire substrate or a silicon carbide (SiC) substrate. A buffer layer 23 may be interposed between the substrate 21 and the lower N-type semiconductor layer 25.

The P-type semiconductor layer 29 is positioned on one region of the lower N-type semiconductor layer 25, and the lower active layer 27 is interposed between the lower N-type semiconductor layer 25 and the P-type semiconductor layer 29. do. In addition, an upper N-type semiconductor layer 35 is positioned on one region of the P-type semiconductor layer 29, and an upper active layer between the P-type semiconductor layer 29 and the upper N-type semiconductor layer 35. 33). As a result, a lower light emitting diode including the lower N-type semiconductor layer 25, the lower active layer 27, and the P-type semiconductor layer 29, the P-type semiconductor layer 29, and the upper active layer 33. And an upper light emitting diode including the upper N-type semiconductor layer 35 is provided.

The lower active layer 27 and the upper active layer 33 may each be a single quantum well or multiple quantum wells. The lower N-type semiconductor layer 25 and the P-type semiconductor layer 29 have a wider band gap than the lower active layer 27, and the P-type semiconductor layer 29 and the upper N-type semiconductor layer 35 ) Has a wider bandgap than the upper active layer 33.

The lower and upper N-type semiconductor layers 25 and 35, the lower and upper active layers 27 and 33, and the P-type semiconductor layers may be GaN-based semiconductor layers formed of (B, Al, Ga, In) N, respectively. . The N-type semiconductor layers 25 and 35 may be formed by doping Si, and the P-type semiconductor layer 29 may be formed by doping Mg.

Meanwhile, when the P-type semiconductor layer 29 is a GaN-based semiconductor layer doped with Mg, Mg may deteriorate crystallinity of the upper active layer 33. In order to prevent the influence of Mg, a codoped layer 31 may be interposed between the P-type semiconductor layer 29 and the upper active layer 33. The co-dope layer may be, for example, a gallium nitride-based semiconductor layer doped with Mg and Si or Mg and In. The improvement of the crystal quality of the upper active layer 33 using the dope layer 31 is described by Su, et al. (InGaN / GaN light emitting diode having a "p-down structure"). (InGaN / GaN Light Emitting Diodes With a p-Down Structure) has been disclosed in IEEE TRANSACTIONS ON ELECTRON DEVICES (VOL.49, NO.8, pp1361-1366, AUGUST 2002). According to the number, the dope layer 31 may be inserted between the P-type semiconductor layer 29 and the upper active layer 33 to improve the crystallinity of the upper active layer 33.

Meanwhile, the lower N-type electrode 37a is formed on another region of the lower N-type semiconductor layer 25, and the upper N-type electrode 37b is formed on the upper N-type semiconductor layer 35. In addition, a P-type electrode 39 is formed on another region of the P-type semiconductor layer 29. The lower N-type electrode 37a and the P-type electrode 39 may be located at both sides of the upper N-type semiconductor layer 35, respectively, as shown in FIG. 1, but are not limited thereto. Can be arranged. In addition, the upper N-type electrode 37b may be formed over a large area on the N-type semiconductor layer 35 to reduce contact resistance with the N-type semiconductor layer 35. The upper N-type electrode 37b may be formed of a transparent electrode through which light emitted from the lower and upper active layers 27 and 33 may pass. For example, the upper N-type electrode 37b may be formed of indium tin oxide (ITO). Can be formed. The lower N-type electrode 37a may also be formed of ITO. ITO is in ohmic contact with the N-type semiconductor layer to lower the contact resistance. On the other hand, the P-type electrode 39 may be formed of Ni / Au, for example. These electrodes 37a, 37b, 39 may be formed using a lift-off process.

The P-type electrode 39 is connected to one terminal of an external power source (not shown), and the lower and upper N-type electrodes 37a and 37b are connected to the other terminal of the external power source to drive the light emitting device. You can. At this time, the P-type electrode 39 is connected to the positive terminal of the external power source, and the N-type electrodes 37a and 37b are connected to the negative terminal of the external power source. The electrodes may be electrically connected to an external power source through bonding wires (not shown). Accordingly, current flows from the P-type electrode 39 to the lower N-type electrode 37a and the upper N-type electrode 37b. That is, a forward current flows through the lower light emitting diodes and the upper light emitting diodes so that the lower and upper light emitting diodes are driven.

According to the present embodiment, since the lower and upper light emitting diodes are provided in a vertically stacked structure, the light output per unit area of the substrate can be increased as compared with the light emitting device having the conventional single light emitting diode structure.

In the present exemplary embodiment, the n-type electrodes 37a and 37b are connected to the negative terminals of the same external power source. However, in order to adjust the bias voltages of the upper and lower light emitting diodes differently, the N-type electrodes The resistors 37a and 37b and the negative terminals of the external power supply may be interposed with each other, or the N-type electrodes 37a and 37b may be connected to different external power sources.

3 and 4 are partial cross-sectional views and circuit diagrams for describing a light emitting device having a plurality of light emitting cells according to an embodiment of the present invention.

Referring to FIG. 3, a plurality of light emitting cells are positioned on a single substrate. Each of the light emitting cells has a structure of vertically stacked light emitting diodes as described with reference to FIGS. 1 and 2. Each of the light emitting cells has a lower N-type electrode 37a, an upper N-type electrode 37b, and a P-type electrode 39 as described with reference to FIGS. 1 and 2. Here, since the structure of the light emitting cells is the same as the light emitting device described with reference to FIGS. 1 and 2, a detailed description thereof is omitted, and electrical connection of the light emitting cells will be described.

The lower N-type electrode 37a and the upper N-type electrode 37b of each of the light emitting cells are electrically connected to the P-type electrode 39 of the neighboring light emitting cells. The electrodes are connected via the metal wire 41. The metal wire 41 may be formed using an air-bridge process or a step-cover process.

At this time, the metal wiring 41 connecting the lower N-type electrode 37a and the P-type electrode 39 and the metal wiring 41 connecting the upper N-type electrode 37b and the P-type electrode 39 are provided. May be connected to each other, as shown, but is not limited thereto, and may be separated from each other.

Referring to FIG. 4, an array in which light emitting cells 43 each having a lower light emitting diode 45a and an upper light emitting diode 45b are connected in series by connecting the metal wiring 41 as described with reference to FIG. 3. Fields 47a and 47b are provided. The series arrays 47a and 47b are connected in anti-parallel and connected to the AC power source 49. Accordingly, a light emitting device driven under an AC power source is provided.

According to the present embodiment, by adopting light emitting cells having vertically stacked light emitting diodes 45a and 45b, the light output per single chip area of a light emitting device driven under an AC power source can be increased.

The number and arrangement of electrodes formed on the lower and upper N-type semiconductor layers 25 and 35 and the P-type semiconductor layer 29, and a connection structure of the electrodes may be variously selected. 5 to 7 are views for explaining an embodiment in which the number of electrodes and the connection structure of the electrodes are different. 5 and 6 are partial cross-sectional and circuit diagrams for describing the light emitting device according to the embodiment, respectively, and FIG. 7 is an equivalent circuit diagram of FIG. 6.

Referring to FIG. 5, a plurality of light emitting cells are positioned on a single substrate. Each of the light emitting cells has a structure of vertically stacked light emitting diodes as described with reference to FIGS. 1 and 2. Each of the light emitting cells has a lower N-type electrode 37a, an upper N-type electrode 37b, and a P-type electrode 39 as described with reference to FIGS. 1 and 2. Here, the structure of the light emitting cells is substantially the same as the light emitting device described with reference to FIGS. 1 and 2, but another P-type electrode 40 is further formed on another region of the P-type semiconductor layer 29. . The another region may be selected to face the other region with the active layer 33 therebetween, but is not limited thereto.

Meanwhile, the lower N-type electrode 37a of each light emitting cell is electrically connected to the P-type electrode 29 of the neighboring light emitting cell, and the other P-type electrode 40 of each light emitting cell is the neighboring light emission. Is electrically connected to the upper N-type electrode 37b of the cell, and the P-type electrode 29 of each light emitting cell is electrically connected to the lower N-type electrode 37a of another neighboring light emitting cell. The upper N-type electrode 37b of is electrically connected to the other P-type electrode 40 of another neighboring light emitting cell. The lower N-type electrode 37a and the P-type electrode 39 of the adjacent light emitting cell are connected through a metal wire 42a, and the upper N-type electrode 37b and the other P-type electrode 40 are made of metal. It is connected via the wiring 42b. The metal wires 42a and 42b may be formed using an air-bridge process or a step-cover process.

Referring to FIG. 6, by connecting the metal wires 42a and 42b as described with reference to FIG. 5, the light emitting cells 44 each having the lower light emitting diode 46a and the upper light emitting diode 46b are formed. A connected array 48 is provided. In this case, the lower light emitting diodes 46a are connected to each other in series, and the upper light emitting diodes 46b are also connected to each other in series. The array in which the lower light emitting diodes 46a are connected in series and the array in which the upper light emitting diodes 46b are connected in series are arranged in parallel with each other.

Meanwhile, as shown in FIG. 7, additional diodes are connected to both sides of the array 48 of the light emitting cells 44 to form an equivalent circuit as shown in FIG. 7.

Referring to FIG. 7, lower light emitting diodes 46a and an additional light emitting diode are connected in series to form one series array, and upper light emitting diodes 46b and another additional light emitting diode are connected in series to form another series array. To form. The arrays of lower and upper light emitting diodes 46a and 46b are connected in anti-parallel to each other. Accordingly, the light emitting cells may be driven by connecting an AC power source 49 to both ends of the arrays. As the AC power supply 49 changes phase, the array of the upper light emitting diodes 46b and the array of the lower light emitting diodes 46a alternately operate.

Meanwhile, as shown in FIG. 7, nodes between the lower light emitting diodes 46a are electrically connected to nodes between the upper light emitting diodes 46b, respectively. By the connection between the nodes, the light emitting cells 46a and 46b can be driven stably under an AC power source, and as a result, the reliability of the light emitting device is improved.

In the present embodiment, a circuit in which additional light emitting diodes are connected to the array 48 of light emitting cells 44 is illustrated, but this is for convenience of description and the additional light emitting diodes may be omitted.

8 and 9 are a plan view and a cross-sectional view for describing a light emitting device according to another embodiment of the present invention, respectively.

8 and 9, as described with reference to FIGS. 1 and 2, the lower N-type semiconductor layer 55 is positioned on the substrate 51, and the substrate 51 and the lower N-type semiconductor are also located. A buffer layer 53 may be interposed between the layers 55.

The lower P-type semiconductor layer 59 is positioned on one region of the lower N-type semiconductor layer 55, and the lower active layer 57 is disposed between the lower N-type semiconductor layer 55 and the lower P-type semiconductor layer 59. This intervenes. In addition, an upper P-type semiconductor layer 63 is positioned on one region of the lower P-type semiconductor layer 59, and a separation layer between the lower P-type semiconductor layer 59 and the upper P-type semiconductor layer 63. (separating layer 61) is interposed. In addition, an upper N-type semiconductor layer 69 is positioned on one region of the upper P-type semiconductor layer 63, and an upper portion is formed between the upper P-type semiconductor layer 63 and the upper N-type semiconductor layer 69. The active layer 67 is interposed. As a result, a lower light emitting diode including the lower N-type semiconductor layer 55, the lower active layer 57, and the lower P-type semiconductor layer 59, the upper P-type semiconductor layer 63, and the upper active layer A light emitting device having a structure in which an upper light emitting diode including a 67 and the upper N-type semiconductor layer 69 is stacked is provided.

The lower active layer 57 and the upper active layer 67 may each be a single quantum well or multiple quantum wells. The lower N-type semiconductor layer 55 and the lower P-type semiconductor layer 59 have a wider bandgap than the lower active layer 57, and the upper P-type semiconductor layer 63 and the upper N-type semiconductor layer. 69 has a wider bandgap than the upper active layer 67.

The lower and upper N-type semiconductor layers 55 and 69, the lower and upper active layers 57 and 67, and the lower and upper P-type semiconductor layers are GaN-based semiconductor layers formed of (B, Al, Ga, In) N, respectively. Can be entered. The N-type semiconductor layers 55 and 69 may be formed by doping Si, and the P-type semiconductor layers 59 and 63 may be formed by doping Mg.

Meanwhile, the separation layer 61 is adopted to electrically separate the lower light emitting diode and the upper light emitting diode, and may be an insulating layer or a semi-insulating layer having a high resistance. The separation layer 61 is preferably formed of a material having the same or similar crystal structure as the lower and upper P-type semiconductor layers 59 and 63, and may be formed of, for example, semi-insulating gallium nitride.

In addition, as described with reference to FIG. 2, a co-dope layer 65 may be interposed between the upper P-type semiconductor layer 63 and the upper active layer 67. The co-doped layer 65 is adopted to improve the crystallinity of the upper active layer 67 when the P-type semiconductor layer 63 is formed of Mg-doped gallium nitride.

The lower N-type electrode 71a is formed on another region of the lower N-type semiconductor layer 55, and the upper N-type electrode 71b is formed on the upper N-type semiconductor layer 69. In addition, a lower P-type electrode 73a is formed on another region of the lower P-type semiconductor layer 59, and an upper P-type electrode 73b is formed on another region of the upper P-type semiconductor layer 63. do. The lower N-type electrode 71a and the upper N-type electrode 71b may be formed of, for example, ITO, and the lower P-type electrode 73a and the upper P-type electrode 73b may be formed of, for example, Ni / Au. Can be. These electrodes 71a, 71b, 73a, 73b may be formed using a lift-off process.

The P-type electrodes 73a and 73b are connected to one terminal of an external power source (not shown), and the N-type electrodes 71a and 71b are connected to the other terminal of the external power source to drive the light emitting device. You can. The electrodes may be electrically connected to an external power source through bonding wires (not shown). Accordingly, a current flows from the lower P-type electrode 73a to the lower N-type electrode 71a, and a current flows from the upper P-type electrode 73b to the upper N-type electrode 71b, so that the lower light emitting diode and the upper light emission. The diode is driven. In addition, the lower P-type electrode 73a and the lower N-type electrode 71a, and the upper P-type electrode 73b and the upper N-type electrode 71b are connected to different external power sources, respectively, so that the lower light emitting diode and The top light emitting diodes can be driven individually.

According to the present embodiment, since the lower and upper light emitting diodes are provided in a vertically stacked structure, the light output per unit area of the substrate can be increased as compared with the light emitting device having the conventional single light emitting diode structure. Further, by adopting the separation layer 61 to electrically separate the upper light emitting diodes and the lower light emitting diodes, it is easy to drive these light emitting diodes individually.

10 and 11 are partial cross-sectional views and circuit diagrams for describing a light emitting device having a plurality of light emitting cells according to another embodiment of the present invention, respectively.

Referring to FIG. 10, a plurality of light emitting cells are positioned on a single substrate. Here, each of the light emitting cells has a structure of light emitting diodes stacked vertically as described with reference to FIGS. 8 and 9. In addition, each of the light emitting cells has a lower N-type electrode 71a, an upper N-type electrode 71b, a lower P-type electrode 73a, and an upper P-type electrode 73b as described with reference to FIGS. 8 and 9. Has Here, since the structure of the light emitting cells is the same as the light emitting device described with reference to FIGS. 8 and 9, a detailed description thereof is omitted, and electrical connection of the light emitting cells will be described.

The lower N-type electrode 71a and the upper N-type electrode 71b of each of the light emitting cells are electrically connected to the lower P-type electrode 73a and the upper P-type electrode 73b of neighboring light emitting cells, respectively. The lower N-type electrode 71a and the lower P-type electrode 73a are connected through the metal wiring 75a, and the upper N-type electrode 71b and the upper P-type electrode 73b connect the metal wiring 75b. Can be connected. The metal wires 75a and 75b may be formed together using an air-bridge process or a step-cover process.

The metal wires 75a and 75b may be formed separately from each other, as illustrated, but are not limited thereto and may be connected to each other.

Referring to FIG. 11, by connecting the metal wires 75a and 75b as described with reference to FIG. 10, the light emitting cells 83 having the lower light emitting diode 85a and the upper light emitting diode 85b are respectively formed. Arrays 87a and 87b connected in series are provided. The series arrays 87a and 87b are connected in reverse parallel to an AC power source 89. Accordingly, a light emitting device driven under an AC power source is provided.

Meanwhile, when the metal lines 75a and 75b are separated from each other, the lower light emitting diodes 85a are also connected in series to form an array, and the upper light emitting diodes 85b also form a series array. Accordingly, by connecting the serial array of the upper light emitting diodes and the serial array of the lower light emitting diodes in parallel and in parallel, it is possible to provide a light emitting device in which the lower light emitting diode and the upper light emitting diode of each light emitting cell are alternately driven under AC power. As a result, a light emitting device that emits light over the entire area of the chip under an AC power supply can be provided.

The light emitting device according to the embodiments of the present invention may be mounted in the LED package in various forms. For example, the substrate 21 of the light emitting device may be mounted as a mounting surface. Alternatively, the light emitting device may be mounted by flip bonding to the submount substrate. When the light emitting device is mounted by flip bonding to the submount substrate, the upper N-type semiconductor layer (s) 35 or 69 of the light emitting device are bonded to the submount substrate through the metal bumper (s). By flip-bonding the light emitting device to a submount substrate having excellent heat dissipation characteristics, heat emitted from the light emitting device can be easily discharged, thereby further improving luminous efficiency.

According to embodiments of the present invention, it is possible to provide a light emitting device capable of increasing light output per unit area by adopting light emitting diodes stacked vertically. In addition, a plurality of light emitting cells having vertically stacked light emitting diodes may be electrically connected to each other to provide a light emitting device capable of being driven under an AC power source and having improved light output. On the other hand, according to the embodiments of the present invention, since the upper N-type semiconductor layer is located above, it is easy to adopt the ITO electrode as a transparent electrode, and also to form a rough surface easily to facilitate the light extraction efficiency It can be improved.

Claims (14)

A lower N-type semiconductor layer on the substrate; A P-type semiconductor layer located on one region of the lower N-type semiconductor layer; An upper N-type semiconductor layer on one region of the P-type semiconductor layer; A lower active layer interposed between the lower N-type semiconductor layer and the P-type semiconductor layer; An upper active layer interposed between the P-type semiconductor layer and the upper N-type semiconductor layer; And A light emitting device having vertically stacked light emitting diodes including a codoped layer interposed between the P-type semiconductor layer and the upper active layer. The method according to claim 1, A lower N-type electrode formed on another region of the lower N-type semiconductor layer; A P-type electrode formed on another region of the P-type semiconductor layer; And The light emitting device having vertically stacked light emitting diodes further comprising an upper N type electrode formed on the upper N type semiconductor layer. delete In the light emitting device having a plurality of light emitting cells on the substrate, Each of the light emitting cells A lower N-type semiconductor layer on the substrate; A P-type semiconductor layer located on one region of the lower N-type semiconductor layer; An upper N-type semiconductor layer on one region of the P-type semiconductor layer; A lower active layer interposed between the lower N-type semiconductor layer and the P-type semiconductor layer; An upper active layer interposed between the P-type semiconductor layer and the upper N-type semiconductor layer; And And a codoped layer interposed between the P-type semiconductor layer and the upper active layer. The method according to claim 4, Each of the light emitting cells may include a lower N-type electrode formed on another region of the lower N-type semiconductor layer; A P-type electrode formed on another region of the P-type semiconductor layer; And Further comprising an upper N-type electrode formed on the upper N-type semiconductor layer, The lower N-type electrode and the upper N-type electrode of each light emitting cell is electrically connected to the P-type electrode of the neighboring light emitting cell. In the light emitting device having a plurality of light emitting cells on the substrate, Each of the light emitting cells A lower N-type semiconductor layer on the substrate; A P-type semiconductor layer located on one region of the lower N-type semiconductor layer; An upper N-type semiconductor layer on one region of the P-type semiconductor layer; A lower active layer interposed between the lower N-type semiconductor layer and the P-type semiconductor layer; An upper active layer interposed between the P-type semiconductor layer and the upper N-type semiconductor layer; A lower N-type electrode formed on another region of the lower N-type semiconductor layer; A P-type electrode formed on another region of the P-type semiconductor layer; Another P-type electrode formed on another region of the P-type semiconductor layer; And An upper N-type electrode formed on the upper N-type semiconductor layer, The lower N-type electrode of each light emitting cell is electrically connected to the P-type electrode of a neighboring light emitting cell, the other P-type electrode of each light emitting cell is electrically connected to the upper N-type electrode of the neighboring light emitting cell, The P-type electrode of each light emitting cell is electrically connected to the lower N-type electrode of another neighboring light emitting cell, and the upper N-type electrode of each light emitting cell is electrically connected to another P-type electrode of the other neighboring light emitting cell. Light emitting device. The method according to claim 6, Each of the light emitting cells further includes a codoped layer interposed between the P-type semiconductor layer and the upper active layer. A lower N-type semiconductor layer on the substrate; A lower P-type semiconductor layer on one region of the lower N-type semiconductor layer; An upper P-type semiconductor layer on one region of the lower P-type semiconductor layer; An upper N-type semiconductor layer positioned on one region of the upper P-type semiconductor layer; A lower active layer interposed between the lower N-type semiconductor layer and the lower P-type semiconductor layer; An upper active layer interposed between the upper P-type semiconductor layer and the upper N-type semiconductor layer; And The light emitting device having vertically stacked light emitting diodes including a separation layer interposed between the lower P-type semiconductor layer and the upper P-type semiconductor layer. The method according to claim 8, A lower N-type electrode formed on another region of the lower N-type semiconductor layer; A lower P-type electrode formed on another region of the lower P-type semiconductor layer; An upper P-type electrode formed on another region of the upper P-type semiconductor layer; The light emitting device having vertically stacked light emitting diodes further comprising an upper N type electrode formed on the upper N type semiconductor layer. The method according to claim 8, A light emitting device having vertically stacked light emitting diodes further comprising a co-dope layer interposed between the upper P-type semiconductor layer and the upper active layer. The method according to claim 8, The light emitting device having vertically stacked light emitting diodes, wherein the separation layer is a semi-insulating layer. In the light emitting device having a plurality of light emitting cells on the substrate, Each of the light emitting cells A lower N-type semiconductor layer on the substrate; A lower P-type semiconductor layer on one region of the lower N-type semiconductor layer; An upper P-type semiconductor layer on one region of the lower P-type semiconductor layer; An upper N-type semiconductor layer positioned on one region of the upper P-type semiconductor layer; A lower active layer interposed between the lower N-type semiconductor layer and the lower P-type semiconductor layer; An upper active layer interposed between the upper P-type semiconductor layer and the upper N-type semiconductor layer; And And a separation layer interposed between the lower P-type semiconductor layer and the upper P-type semiconductor layer. The method according to claim 12, Each of the light emitting cells A lower N-type electrode formed on another region of the lower N-type semiconductor layer; A lower P-type electrode formed on another region of the lower P-type semiconductor layer; An upper P-type electrode formed on another region of the upper P-type semiconductor layer; Further comprising an upper N-type electrode formed on the upper N-type semiconductor layer, The lower N type electrode and the upper N type electrode of each light emitting cell are electrically connected to the lower P type electrode and the upper P type electrode of a neighboring light emitting cell, respectively. The method according to claim 12, Each of the light emitting cells further includes a co-dope layer interposed between the upper P-type semiconductor layer and the upper active layer.

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