KR101060118B1 - Chip stacked semiconductor package and chip stacking method thereof - Google Patents

Abstract

The present invention relates to a chip stacked semiconductor package and a chip stacking method thereof, and more particularly, to plate a conductive layer for electrical connection at the wafer level in advance, thereby facilitating stacking of chips and attaining a large heat dissipation effect. The present invention relates to a chip stacked semiconductor package and a chip stacking method thereof.

To this end, the present invention is a substrate; A plurality of chips fabricated in an inclined structure on all sides and electrically stacked on the substrate by an electrical connection layer; The vertical layer plated with conductive material on the inclined four sides of each chip and the horizontal layer plated with the conductive material on the upper or lower edge of each chip are integrally connected and form a predetermined interval along the circumferential direction of the chip. A plurality of electrical connection layers formed; It provides a chip stacked semiconductor package and a chip stacking method thereof comprising a.

Semiconductor Chip, Lamination, Package, Electrical Connection Layer, Wafer, Reflow, Solder

Description

Chip stacked semiconductor package and chip stacking method thereof {Stack chip package and chip stacking method}

The present invention relates to a chip stacked semiconductor package and a chip stacking method thereof, and more particularly, to plate a conductive layer for electrical connection at the wafer level in advance, thereby facilitating stacking of chips and attaining a large heat dissipation effect. The present invention relates to a chip stacked semiconductor package and a chip stacking method thereof.

Three-dimensional lamination technology among packaging technologies of semiconductor integrated circuits has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance, and the three-dimensional lamination package has a plurality of chips having the same storage capacity. This is a stacked package, which is commonly referred to as a stacked chip package.

The technology of the multilayer chip package can reduce the manufacturing cost of the package by a simplified process, and also has the advantage of mass production, etc., but lacks the wiring space for the electrical connection inside the package according to the increase in the number and size of the stacked chips. The disadvantage is that.

That is, the conventional laminated chip package is manufactured in a structure in which a plurality of chips are stacked and attached to the chip attachment region of the substrate, so that the bonding pads of the chips and the conductive circuit patterns of the substrate are electrically connected to each other by wires. A space for bonding is required, and a circuit pattern area of a substrate to which wires are connected is required, resulting in an increase in the size of a semiconductor package.

In view of these shortcomings, a structure using through silicon vias has been proposed as an example of a stack package, which uses laser drilling to process a plurality of vertical holes in a chip and embeds conductive materials in the vertical holes. A method of electrically stacking chips by connecting through silicon vias with conductive bumps has been proposed.

The method of stacking chips using the through silicon vias can reduce the size of the semiconductor package by eliminating the need for wire bonding. However, the process of forming the through silicon vias and electrically connecting the chips is complicated. There is a need for a new method of chip stacking.

The present invention has been made in view of the above, the chip is formed on both sides of the chip inclined at the wafer level, and the electrical connection layer formed by plating a conductive material over the top and inclined sides of the chip, the electrical connection of the chip Laminating and contacting layers, or reflowing solder balls attached to the uppermost chip to flow down the side of each chip to interconnect the interconnect layers of each chip, using wire bonding and through silicon vias It is an object of the present invention to provide a chip stacked semiconductor package and a chip stacking method thereof in which chips can be stacked in a simpler process and a heat dissipation effect can be obtained compared to a chip stacking method.

One embodiment of the present invention for achieving the above object is a substrate; A plurality of chips fabricated in an inclined structure on all sides and electrically stacked on the substrate by an electrical connection layer; The vertical layer plated with conductive material on the inclined four sides of each chip and the horizontal layer plated with the conductive material on the upper or lower edge of each chip are integrally connected and form a predetermined interval along the circumferential direction of the chip. A plurality of electrical connection layers formed; It provides a chip stacked semiconductor package, characterized in that configured to include.

The plurality of chips are stacked in a vertical direction or stacked in a staircase, and the electrical connection layers of each chip are electrically connected by solder flow lines due to reflow of solder balls.

The plurality of chips may be stacked in a step shape while being eccentric in one direction, and a vertical layer of an electrical connection layer formed on one side of the upper chip and a horizontal connection of the electrical connection layer formed on one side of the lower chip. The layers are in contact with each other and electrically connected to each other, and the electrical connection layers formed on the other side of the upper chip and the lower chip are spaced apart from each other to be heat dissipation means.

A horizontal extension layer extending outward is integrally formed at a lower end of the vertical layer of the electrical connection layer formed on each side of each chip, and an insulating material is coated on the surfaces of the vertical layer and the horizontal extension layer.

Another embodiment of the present invention for achieving the above object comprises the steps of: forming a vertical groove inclined inner wall surface around each chip in the wafer state; Forming an electrical connection layer by plating a conductive material on the bottom and inner wall of each vertical groove and the outer peripheral surface of the inlet of the vertical groove; Performing backgrinding on the bottom surface of the wafer until the bottom surface of each vertical groove penetrates, separating the chips into individual chips; Stacking each chip with the electrical connection layers electrically connected thereon to mount the separated chips on the substrate; A chip stacking method of a chip stack type semiconductor package is provided.

The conductive material plated on the outer periphery of the inlet of the vertical groove is formed on the upper or lower edge of each chip to form a horizontal layer of the electrical connection layer, and the conductive material plated on the inner wall of the vertical groove is on the inclined side of each chip. While being formed is characterized in that the vertical layer of the electrical connection layer.

In another embodiment of the present invention, after stacking the chips in a vertical direction, or stacked to form a stairway to one side eccentrically, fusing a solder ball on the horizontal layer of the top chip; Reflowing the solder balls so that a liquid solder is applied along the electrical connection layers of the respective chips stacked below and applied to the conductive patterns on the substrate to be electrically connected to each other; It characterized in that it further comprises.

When the chips are stacked in a stepped manner while being eccentric in one direction, a vertical layer of an electrical connection layer formed on one side of the upper chip and a horizontal layer of an electrical connection layer formed on one side of the lower chip among the chips stacked in a step form. Are in contact with each other and electrically connected.

Another embodiment of the present invention for achieving the above object comprises the steps of: forming a vertical groove inclined inner wall surface around each chip in the wafer state; Forming an electrical connection layer by plating a conductive material on the bottom and inner wall of each vertical groove and the outer peripheral surface of the inlet of the vertical groove; Filling an insulating material into the vertical groove in which the electrical connection layer is formed; Performing backgrinding on the bottom of the wafer until the plated electrical connection layer is exposed on the bottom surface of each vertical groove; Performing sawing in the vertical direction along the center of the vertical groove and the insulating material to separate the individual chips; Stacking each chip with the electrical connection layers electrically connected thereon to mount the separated chips on the substrate; A chip stacking method of a chip stack type semiconductor package is provided.

The conductive material plated on the outer periphery of the inlet of the vertical groove is formed on the upper or lower edge of each chip to form a horizontal layer of the electrical connection layer, and the conductive material plated on the inner wall of the vertical groove is on the inclined side of each chip. While being formed as a vertical layer of the electrical connection layer, the conductive material plated on the bottom surface of the vertical groove is characterized in that the horizontal extension layer extending outward from the horizontal layer.

Each chip is laminated in the vertical direction or each chip is laminated stepwise while the horizontal extension layers of the chips are in electrical contact with each other.

Another embodiment of the present invention for achieving the above object is: after forming the first vertical groove inclined inner wall surface in a portion of the upper peripheral portion of each chip in the wafer state, the bottom and the inside of the first vertical groove Forming an electrical connection layer by plating a conductive material on a wall surface and an outer circumferential surface of the inlet of the first vertical groove; After forming the second vertical groove in which the inner wall surface is inclined over the section which does not coincide with the first vertical groove among the bottom circumference of each chip in the wafer state, the bottom and the inner wall surface of the second vertical groove and the inlet of the second vertical groove Plating an outer circumferential surface to form an electrical connection layer; Performing a sawing along the inner wall surface of the first vertical groove and the inner wall surface of the second vertical groove forming the same diagonal line, and separating the chips into parallelograms; Stacking each chip with the electrical connection layers electrically connected thereon to mount the separated chips on the substrate; A chip stacking method of a chip stack type semiconductor package is provided.

The conductive material plated on the outer circumferential surface of the inlet of the first vertical groove is formed on the upper edge of each chip, and becomes the upper horizontal layer of the electrical connection layer, and the conductive material plated on the inner wall surface of the first vertical groove is the diameter of each chip. It is formed on the side of the photo and becomes a vertical layer of the electrical connection layer, the conductive material plated on the outer peripheral surface of the inlet of the second vertical groove is formed on the bottom edge of each chip and becomes the lower horizontal layer of the electrical connection layer, the second vertical The conductive material plated on the inner wall surface of the groove is formed on the inclined side of each chip, characterized in that it becomes a vertical layer of the electrical connection layer.

Among the stacked chips, a vertical layer and a lower horizontal layer of the chip stacked on the upper side are electrically connected to the upper horizontal layer and the vertical layer of the chip stacked below, respectively.

Through the above problem solving means, the present invention provides the following effects.

According to the present invention, by stacking the chip on the substrate, by plating the respective chip in the wafer state to form an electrical contact layer in advance, and then to stack the chip, the conventional electrical laminated connection method through the through-silicon via and Compared to the electrical laminated connection method through wire bonding, the electrical connection between chips can be easily achieved while having a simple structure.

In addition, the electrical connection between the chips can be easily made by the electrical connection layer by plating without a separate electrical intermediary means such as conductive bumps.

In addition, the stacked chips are arranged in a stepwise manner, so that the electrical connection layers arranged on one side are energized and the electrical connection layers arranged on the other side do not come into contact with each other. By performing the release function, a large heat release effect can be obtained.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 1 and FIG. 2 to which the first embodiment of the chip stacked package according to the present invention is attached as follows.

The chip stacked package according to the first embodiment of the present invention is a package in which a plurality of chips 20a to 20n are stacked on a substrate 10, as shown in the cross-sectional views of FIGS. 1 and 2. When viewed from the side is inclined to form a trapezoidal shape when viewed from the side, each chip (20a ~ 20n) is formed by plating an electrically conductive material 30 for the electrical connection between the chips.

The electrical connection layer 30 is formed to form a predetermined interval along the circumferential direction of each chip (20a ~ 20n), the vertical layer 32 is plated with a conductive material on the inclined four sides of each chip (20a ~ 20n) ) And a horizontal layer 34 plated with a conductive material on the upper or lower edge of each chip 20a to 20n are integrally connected.

Among the chips 20a to 20n stacked on the substrate 10, the bottommost chip 20a is laminated on the substrate 10 using adhesive means, and then a plurality of chips on the bottom chip 20a are stacked. 20b to 20n) are laminated in order by using an adhesive means.

As such, as illustrated in FIG. 1, chips 20a to 20n having the same size are stacked vertically on the substrate 10 or the largest size chips are stacked at the bottom and the smallest size at the top. By stacking the chips of each chip 20a ~ 20n are stacked in a step on the substrate (10).

According to the first embodiment of the present invention, the electrical connection between the substrate 10 and the chip 20a, and the electrical connection between the chips (20a ~ 20n) is made through the reflow of the solder ball 40 have.

That is, after stacking the chips 20 in the vertical direction as described above or to form a staircase, and then fusion bonding the solder ball 40 on the horizontal layer 34 of the top chip (20n), the solder ball 40 Reflow).

Therefore, the liquid solder is applied along each of the electrical connection layers 30 of the chips 20a to 20b stacked below the upper chip 20n, and at the same time, to the conductive pattern 12 on the substrate 10. Electrically connected.

More specifically, the liquid solder is applied along the horizontal layer 34 and the vertical layer 32 of each electrical connection layer 30 of the stacked chips 20a to 20b and at the same time the bottom of the chip 20b. Flow is applied to the conductive pattern 12 on the substrate 10 to be electrically connected to the vertical layer 32 of the electrical connection layer 30.

After the reflow of the solder ball 40, the curing process, the solder by the reflow of the solder ball 40 over the conductive pattern 12 of the substrate 10 and the electrical connection layer 30 of the chip 20 The flow line 42 is formed, and the solder flow line 42 makes electrical connection between the substrate 10 and the chip 20a and electrical connection between the chips 20a to 20n easy.

As described above, according to the package according to the first exemplary embodiment, the stacking and the electrical connection between the chips can be easily performed in a simple structure without the need for forming a separate through silicon via (TSV), thereby reducing the number of processes and reducing the cost. Can be.

Here, a description will be given with reference to FIGS. 3A and 3D to which a second embodiment of a chip stacked package according to the present invention is attached.

3A to 3D are cross-sectional views illustrating a chip stacked semiconductor package and a chip stacking method according to a second embodiment of the present invention.

As shown in FIG. 3A, in order to form an electrical connection layer 30 that becomes an electrical connection means when stacking chips, a trench having an inner wall surface inclined around each chip 20 in a wafer 50 state. To form a vertical groove (52).

Subsequently, the electrical connection layer 30 is formed by plating a conductive material on the bottom and inner wall surfaces of the vertical grooves 52 and the outer peripheral surface of the inlet of the vertical grooves 52.

Next, backgrinding is performed on the bottom surface of the wafer 50 until the bottom surface of the vertical groove 52 is penetrated.

When backgrinding is performed on the wafer as described above, the bottom surface of the trench-shaped vertical grooves 52 is penetrated, so that the chips in the wafer state are separated into individual chips 20.

Thus, in order to mount each chip 20a-20n separated by each unit on the board | substrate 10, it is laminated | stacked, electrically connecting the electrical connection layer 30 of each chip 20a-20n.

At this time, the conductive material plated on the outer peripheral surface of the inlet of the vertical groove 52 is formed on the upper or lower edge of each chip 20 to become a horizontal layer 34 of the electrical connection layer 30, the vertical groove 52 The conductive material plated on the inner wall surface of the c) is formed on the inclined side surfaces of the respective chips 20a to 20n to become the vertical layer 32 of the electrical connection layer 30.

The chips 20a to 20n provided as described above are stacked in a vertical direction or stacked to form a stairway by being eccentric to one side, and as shown in FIG. 3D, the uppermost chip 20n is the same as that of the first embodiment. By melting the solder balls 40 on the horizontal layer 34 of the, and then reflowing the solder balls 40, a liquid solder is applied along each electrical connection layer 30 of the chips 20a stacked below. At the same time, the conductive pattern 12 on the substrate 10 is also applied, so that the substrate 10, the bottom chip 20a, and each chip 20a to 20n may be electrically connected to each other.

According to the second embodiment of the present invention, the electrical connection method in chip stacking may be electrically connected by directly contacting the electrical connection layers 30 with electricity without using a reflow method of solder balls.

In more detail, when the chips 20a to 20n are stacked in one direction while being eccentric in one direction, an electrical connection is formed on one side of the chip stacked on the upper side of the chips 20a to 20n stacked in a step. The vertical layer 32 of the layer 30 and the horizontal layer 34 of the electrical connection layer 30 formed on one side of the chip stacked on the lower side are in contact with each other and electrically connected.

In this case, when the chips 20a to 20n are stacked in one direction while being eccentrically stacked, the electrical connection layers 30 formed on the other side of each of the chips 20a to 20n are separated from each other without being contacted with each other. It is in a state of being in an intact state, and serves as a kind of heat dissipation means for dissipating heat generated from the chip to the outside.

On the other hand, as shown in Figure 3c attached to the chip (20a ~ 20n) in one direction eccentrically stacked stepped, the chip is turned upside down to the electrical connection layer 30 formed on one side of the chip stacked on the upper side Of course, it is possible to electrically connect the horizontal layer 32 of) and the vertical layer 34 of the electrical connection layer 30 formed on one side of the chip stacked on the lower side.

As described above, according to the second exemplary embodiment of the present invention, the electrical connection between the chips is made through the electrical connection layer, which is a plating layer, thereby forming and stacking through silicon vias on the chip and connecting the chips with wires. Compared to the above, the stacking of the chips and the electrical connection between the chips have a simple structure, which can reduce the number of processes and reduce the cost, and can also greatly obtain the effect of dissipating heat generated from the chips.

Here, a description will be given with reference to FIGS. 4A and 4D attached to a third embodiment of a chip stacked package according to the present invention.

4A to 4D are cross-sectional views illustrating a chip stacked semiconductor package and a chip stacking method according to a third embodiment of the present invention.

As shown in FIGS. 4A and 4B, in order to form an electrical connection layer 30 that is an electrical connection means when stacking chips, vertical grooves 52 having an inner wall surface inclined around each chip in the state of the wafer 50. The electrical connection layer 30 is formed by plating a conductive material on the bottom and inner wall surfaces of the vertical grooves 52 and the outer peripheral surface of the inlet of the vertical grooves 52.

At this time, the conductive material plated on the outer peripheral surface of the inlet of the vertical groove 52 is formed on the upper or lower edge of each chip (20a ~ 20n) when separated into individual chips, the horizontal layer of the electrical connection layer 30 ( 34, and the conductive material plated on the inner wall surface of the vertical groove 52 is formed on the inclined side of each chip (20a ~ 20n) when separated into individual chips, the electrical connection layer (30) The conductive material plated on the bottom surface of the vertical groove 52 is formed as a vertical layer 32 of the horizontal extension layer extending outward from the horizontal layer 34 when separated into individual chips ( 36).

Subsequently, according to the third embodiment, the insulating material 38 is filled to surround the electrical connection layer 30 in the vertical groove 52 in which the electrical connection layer 30 is formed. Is in a state of being applied to the surface of the vertical layer 32 and the horizontal extension layer 36 when separated into individual chips, the electrical connection layer 30 including the vertical layer 32 and the horizontal extension layer 36 It prevents moisture from penetrating the water and prevents oxidation.

Next, as shown in FIG. 4A, backgrinding is performed on the bottom surface of the wafer 50 until the plated electrical connection layer 30 is exposed on the bottom surface of the vertical groove 52. The sawing is performed vertically along the center of the vertical groove 52 and the insulating material 38 to be separated into individual chips.

Alternatively, as shown in FIG. 4B, after sawing in a vertical direction along the centers of the vertical grooves 52 and the insulating material 38, an electrical connection layer plated on the bottom surface of the vertical grooves 52 ( Until 30) is exposed, backgrinding of the bottom surface of the wafer 50 is performed to separate the chips into individual chips.

Accordingly, in order to mount the separated chips 20 on the substrate 10, the chips 20 are stacked while the electrical connection layers 30 of the chips 20 are electrically connected to each other.

According to the second embodiment of the present invention, as shown in FIGS. 4C and 4D, each chip 20a to 20n is placed in a vertical direction while the horizontal extension layers 36 of the chips 20a to 20n are electrically contacted with each other. The chips 20a to 20n are stacked in a stepwise manner.

Similarly, according to the third embodiment of the present invention, the electrical connection between the chips is made through the electrical connection layer, which is a plating layer, compared to the method of forming and stacking through-via vias on the chip and connecting the chips by wire. In addition, the stacking between the chips and the electrical connection between the chips can be made simple to reduce the number of processes and reduce the cost, and to prevent the short circuit and the oxidation between the electrical connection layers by filling the insulating material.

Here, a description will be given with reference to FIGS. 5A and 5C to which the fourth embodiment of the chip stacked package according to the present invention is attached.

5A to 5C are cross-sectional views illustrating a chip stacked semiconductor package and a chip stacking method according to a fourth embodiment of the present invention.

According to the fourth embodiment of the present invention, the electrical connection layers 30a and 30b, which serve as electrical connection means when the chips are stacked, are formed in a multilayer structure on both sides of the chip.

To this end, after forming the first vertical groove 52a in which the inner wall surface is inclined in a portion of the upper peripheral portion of each chip in the wafer 50 state, the bottom and the inner wall surface of the first vertical groove 52a, first A conductive material is plated on the outer circumferential surface of the inlet of the vertical groove 52a to form the electrical connection layer 30a.

Further, after the wafer is inverted, a second vertical groove 52b having an inclined inner wall surface is formed over a section which does not coincide with the first vertical groove 52a among the bottom circumferences of the respective chips 20 in the wafer 50 state. The conductive material is plated on the bottom and inner wall surfaces of the second vertical grooves 52b and the outer peripheral surface of the inlet of the second vertical grooves 52b to form the electrical connection layer 30a.

Subsequently, as a chip separating step, sawing is performed along the inner wall surface of the first vertical groove 52a and the inner wall surface of the second vertical groove 52b forming the same diagonal lines, thereby forming a chip having a parallelogram cross-sectional shape. Are separated.

At this time, when separated into individual chips, the conductive material plated on the outer peripheral surface of the inlet of the first vertical groove (52a) is formed on the upper edge of each chip 20, the upper horizontal layer (34a) of the electrical connection layer (30a) And a conductive material plated on the inner wall surface of the first vertical groove 52a is formed on the inclined side surface of each chip 20 and is formed as the vertical layer 32a of the electrical connection layer 30a. In addition, the conductive material plated on the outer circumferential surface of the inlet of the second vertical groove 52b is formed on the bottom edge of each chip 20, and is formed as the lower horizontal layer 34b of the electrical connection layer 30b. The conductive material plated on the inner wall surface of the groove 52b is formed on the inclined side surface of each chip 20 and is formed as the vertical layer 32b of the electrical connection layer 30b.

In order to mount the individual chips 20a to 20n thus separated on the substrate 10, the chips 20a to 20n are laminated while the electrical connection layers 30a and 30b are electrically contacted with each other.

According to the fourth embodiment of the present invention, as shown in FIG. 5C, the solder ball 40 is fused to the horizontal layer 34 of the uppermost chip 20 n as in the first embodiment, and then the solder ball is By reflowing the 40, the substrate 10, the lowest chip 20a, and each chip 20a to 20n may be electrically connected to each other.

In addition, the electrical connection layers 30 may be electrically connected to each other so as to be in electrical contact with each other. For example, the vertical layer 32a of the chip 20n stacked on the top of the stacked chips 20 may be electrically connected. ) And the lower horizontal layer 34b may be electrically connected to the upper horizontal layer 34a and the vertical layer 32b of the chip 20a stacked below and stacked in contact with each other.

As described above, the fourth embodiment of the present invention also enables the electrical connection between the chips to be made through the electrical connection layer, which is a plating layer, as compared with the conventional method of forming and stacking through-silicon vias on the chip and connecting the chips with wires. The stacking of each chip and the electrical connection between chips can be made simple to reduce the number of processes and reduce the cost.

1 and 2 are cross-sectional views showing a first embodiment of a chip stacked semiconductor package according to the present invention;

3A to 3D are cross-sectional views illustrating a chip stacking method in accordance with a second embodiment of a chip stacked semiconductor package according to the present invention;

4A to 4D are cross-sectional views illustrating a chip stacking method according to a third embodiment of a chip stacked semiconductor package according to the present invention;

5A to 5C are cross-sectional views illustrating a chip stacking method in accordance with a fourth embodiment of a chip stacked semiconductor package according to the present invention;

<Explanation of symbols for the main parts of the drawings>

10: substrate 12; Conductive Pattern

20a ~ 20n: chip 30: electrical connection layer

30a, 30b: electrical connection layer 32: vertical layer

32a, 32b: vertical layer 34: horizontal layer

34a: upper horizontal layer 34b: lower horizontal layer

36: horizontally extending layer 38: insulating material

40: solder ball 42: solder flow line

50: wafer 52: vertical groove

52a: first vertical groove 52b: second vertical groove

Claims (14)

A substrate 10; A plurality of chips 20a to 20n which are fabricated in an inclined side surface and electrically connected and stacked by the electrical connection layer 30 on the substrate 10; The vertical layer 32 plated with the conductive material on the inclined four sides of each chip 20a to 20n and the horizontal layer 34 plated with the conductive material on the upper or lower edge of each chip 20 are integrally formed. As a connected configuration, a plurality of electrical connection layer 30 formed at regular intervals along the circumferential direction of the chip (20a ~ 20n); When the plurality of chips 20a to 20n are stacked in a step, a solder flow line due to reflow of the solder ball 40 for electrically connecting the electrical connection layer 30 of each chip 20a to 20n ( 42); In the chip laminated semiconductor package comprising: The plurality of chips 20a to 20n may be stacked in a step shape while being eccentric in one direction, and the electrical connection layer 30 formed on one side of the chip stacked on the upper side of the chips 20a to 20n stacked in a step. The vertical layer 32 of the and the horizontal layer 34 of the electrical connection layer 30 formed on one side of the chip stacked on the lower side is in contact with each other and electrically connected, the other side of the upper chip and the lower chip The formed electrical connection layer 30 is a chip laminated semiconductor package, characterized in that spaced apart and electrically separated to be a heat dissipation means. delete delete The method according to claim 1, At the lower end of the vertical layer 32 of the electrical connection layer 30 formed on the side of each chip 20a to 20n, a horizontal extension layer 36 extending outward is integrally formed, and the vertical layer 32 And a surface of the horizontal extension layer 36, an insulating material 38 is coated. Forming vertical grooves 52 in which an inner wall surface is inclined around each chip 20a to 20n in the wafer 50 state; Electrical connection consisting of a vertical layer 33 formed by plating a conductive material on the bottom and the inner wall surface of the vertical groove 52 and a horizontal layer 34 formed by plating a conductive material on the outer peripheral surface of the inlet of the vertical groove 52. Forming a layer 30; Backgrinding the bottom surface of the wafer (50) until the bottom surface of the vertical groove (52) is penetrated, separating the individual chips into individual chips; Stacking the electrically connected layers 30 of the respective chips 20a to 20n while electrically connecting the separated chips on the substrate; In the chip stacking method of the chip stacked semiconductor package comprising: When the chips 20a to 20n are stacked in an eccentric direction in one direction, a step of the electrical connection layer 30 formed on one side of the chip stacked on the upper side of the chips 20a to 20n stacked in a step form The vertical layer 32 and the horizontal layer 34 of the electrical connection layer 30 formed on one side of the chip stacked on the lower side are in contact with each other and electrically connected to each other, and are formed on the other side of the upper chip and the lower chip. The chip stacking method of the chip laminated semiconductor package, characterized in that the electrical connection layers 30 are spaced apart and electrically separated to be heat dissipation means. delete delete delete delete delete delete After forming the first vertical groove 52a in which the inner wall surface is inclined in a part of the upper peripheral portion of each chip in the wafer 50 state, the bottom and the inner wall surface of the first vertical groove 52a, the first vertical groove ( Plating the conductive material on the outer circumferential surface of the inlet 52a to form an electrical connection layer 30a; After forming the second vertical groove 52b in which the inner wall is inclined over a section which does not coincide with the first vertical groove 52a among the bottom circumferences of the respective chips in the wafer 50 state, the second vertical groove 52b is formed. Forming an electrical connection layer (30b) by plating a conductive material on the bottom and inner wall surfaces of the inner surface of the second vertical groove (52b); Performing sawing along the inner wall surface of the first vertical groove (52a) and the inner wall surface of the second vertical groove (52b) forming the same oblique line, and separating the chip into a chip having a parallelogram cross-sectional shape; Stacking the chips 20a to 20n with the electrical connection layers 30a and 30b electrically connected to each other to mount the separated chips 20a to 20n on the substrate 10; A chip stacking method of a chip stack type semiconductor package, characterized in that consisting of. The method according to claim 12, The conductive material plated on the outer peripheral surface of the inlet of the first vertical groove (52a) is formed on the upper edge of each chip (20a ~ 20n) and becomes the upper horizontal layer (34a) of the electrical connection layer (30a), The conductive material plated on the inner wall surface of the first vertical groove 52a is formed on the inclined side surface of each chip 20a to 20n to become the vertical layer 32a of the electrical connection layer 30a. The conductive material plated on the outer peripheral surface of the inlet of the second vertical groove (52b) is formed on the bottom edge of each chip (20a ~ 20n) and becomes the lower horizontal layer (34b) of the electrical connection layer (30b), The conductive material plated on the inner wall surface of the second vertical groove (52b) is formed on the inclined side of each chip (20a ~ 20n) chip stack type, characterized in that the vertical layer (32b) of the electrical connection layer (30b) Chip stacking method of semiconductor package. The method according to claim 12, The vertical layer 32a and the lower horizontal layer 34b of the chip stacked above the stacked chips 20a to 20n are respectively disposed on the upper horizontal layer 34a and the vertical layer 32b of the chip stacked below. A chip stacking method for a chip stacked semiconductor package, characterized in that the corresponding contact is electrically connected.

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