KR101001490B1 - Liquid Crystal Display - Google Patents

Abstract

According to an exemplary embodiment of the present invention, a liquid crystal display includes: a plurality of gate lines and data lines formed to cross each other on a lower substrate; A plurality of pixel electrodes formed on a region where the gate line and the data line cross each other; In a liquid crystal display device comprising a plurality of thin film transistors formed at the intersection of the gate line and the data line,

The predetermined portion of the gate line used as the first electrode of the storage capacitor and the pixel electrode portion adjacent to the gate line are formed to be inclined in the same direction as the rubbing direction of the alignment layer.

According to the present invention, the light leakage phenomenon can be minimized without increasing the mask, increasing the process, or changing the process. As a result, the contrast ratio can be secured while maintaining the same aperture ratio by minimizing the light leakage phenomenon.

Description

Liquid Crystal Display

1 is an exploded perspective view showing a part of a general liquid crystal display device.

2 is an enlarged plan view schematically showing some pixels of a conventional array substrate for a liquid crystal display device;

3 is a cross-sectional view of a specific part I-I of FIG. 2;

4 is an enlarged plan view schematically showing some pixels of an array substrate for a liquid crystal display according to the present invention;

FIG. 5 is a sectional view of a specific part II-II of FIG. 4; FIG.

<Explanation of symbols for the main parts of the drawings>

43: gate line 45: data line

47: front pixel electrode 49: rear pixel electrode

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device having a pixel structure that overcomes light leakage caused by poor rubbing.

In general, the driving principle of the liquid crystal display device uses the optical anisotropy and polarization of the liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light polarized by optical anisotropy may be arbitrarily modulated to express image information.

The liquid crystal may be classified into a positive liquid crystal having a positive dielectric anisotropy and a negative liquid crystal having a negative dielectric anisotropy according to an electrical property classification. The long axes are arranged in parallel, and the liquid crystal molecules having negative dielectric anisotropy are arranged in the direction in which the electric field is applied and the long axes of the liquid crystal molecules are perpendicular to each other.

Nowadays, thin film transistors and active matrix LCDs in which pixel electrodes connected to the thin film transistors are arranged in a matrix manner have been commonly used because of their excellent resolution and video performance.

The structure of the liquid crystal panel, which is a basic component of the liquid crystal display, is as follows.

1 is an exploded perspective view showing a part of a general liquid crystal display device.

Referring to FIG. 1, a general liquid crystal display device 11 includes a color filter 7 including a black matrix 6 and a sub-color filter (red, green, blue) 8, and a common electrode transparent on the color filter. An upper substrate 5 having an 18 formed thereon, and a lower substrate 22 having an array wiring including a pixel region P, a pixel electrode 17 formed on the pixel region, and a switching element T. The liquid crystal 14 described above is filled between the upper substrate 5 and the lower substrate 22.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is disposed in a matrix form, and a gate line 13 and a data line 15 passing through the plurality of thin film transistors are formed.

In addition, the pixel area P is a region where the gate line 13 and the data line 15 cross each other. The pixel electrode 17 formed on the pixel region P uses a transparent conductive metal having a relatively high transmittance of light, such as indium tin oxide (ITO).

In the liquid crystal display device 11 configured as described above, the liquid crystal layer 14 positioned on the pixel electrode 17 is oriented by a signal applied from the thin film transistor, and the liquid crystal layer depends on the degree of alignment of the liquid crystal layer. The image can be expressed by controlling the amount of light passing through the image.

2 is an enlarged plan view schematically illustrating some pixels of a conventional array substrate for a liquid crystal display device.

Referring to FIG. 2, the gate line 13 and the data line 15 cross each other to define the pixel region P. The gate electrode 13 is formed at the intersection of the gate line 13 and the data line 15. A thin film transistor T composed of 31, a source electrode 33 and a drain electrode 35 is formed.

The source electrode 33 and the drain electrode 35 are configured to be spaced apart from each other on the gate electrode 31 by a predetermined interval, and an active channel (not shown) is exposed between the source electrodes 33 and the drain electrode 35.                         

When a predetermined scanning pulse is applied to the gate electrode 31 of the thin film transistor, the voltage of the gate electrode 31 is increased accordingly, and the thin film transistor is turned on. At this time, the liquid crystal driving voltage is applied to the liquid crystal from the data line 15 via the drain and the source of the thin film transistor T, and the pixel capacitance in which the liquid crystal capacitance and the storage capacitance are combined is charged.

The storage capacitor may include an on-gate including a part of the gate line 13 and a part of the rear pixel electrode 19 overlapping the gate line 13, and a part of the gate line 13 and the auxiliary electrode 18 overlapping the gate line 13. It is formed by an on-gate accumulation capacitor.

3 is a cross sectional view of a specific portion I-I of FIG. 2, which is a cross sectional view of the accumulation capacitor region;

Referring to FIG. 3, a gate line 13 used as a first electrode of an accumulation capacitor is formed on a substrate 100, and a gate insulating layer 12 is formed on an exposed surface of the substrate including the gate line 13. ) Is formed.

An auxiliary electrode 18 used as the second electrode of the capacitor formed of the metal layer for forming the source / drain electrodes is formed on the gate insulating layer 12.

In addition, the passivation layer 14 covers the auxiliary electrode 18, and a contact hole for exposing a part of the auxiliary electrode 18 is formed in the passivation layer 14, and the pixel electrode 19 is formed through the contact hole. It is formed on the passivation layer 14 while being connected to the auxiliary electrode 18.

As described above, when an array substrate including a gate line, a data line, and a pixel is formed, that is, a lower substrate, it is bonded to an upper substrate, and a liquid crystal layer is formed therebetween, wherein the back light is disposed below the lower substrate. area on the upper substrate (not shown) overlapping with the gate line 13, the data line 15, the thin film transistor T, and the like to prevent the light emitted through the back light from leaking in the region other than the pixel. Black matrix BM is formed on the substrate. The portion 20 in which the black matrix BM is formed is shown in FIG. 2.

In addition, upper and lower alignment layers (not shown) are formed on the upper and lower substrates to facilitate the alignment of the liquid crystal when voltage is applied to the contact surface with the liquid crystal layer, respectively.

In general, the alignment layer is subjected to a rubbing treatment in order to make the alignment of the liquid crystal constant and to give a pretilt angle for easily inducing the alignment of the liquid crystal. The rubbing treatment is to form a certain groove in the alignment layer by applying a pressure to the rotating roller wrapped with a rubbing cloth while maintaining a constant angle with the substrate, in the case of a substrate having a stepped portion, rubbing failure may occur with respect to the stepped portion.

In this case, since the lower substrate is manufactured by repeating a plurality of processes, that is, deposition, photolithography, and the like, many times, compared to the upper substrate, a plurality of array elements form a step, and a step frequency is higher than that of the upper substrate. Becomes high.

Accordingly, when rubbing the lower substrate at an angle of 45 ° from top to bottom as shown in FIG. 2 to secure the main viewing angle of the alignment layer, rubbing is likely to occur unevenly due to the step of the array elements, and the non-uniformity Light leakage may occur due to rubbing.

In particular, as shown in FIG. 3, the storage capacitor region has a gate line, an auxiliary electrode, and a pixel electrode stacked thereon to form a large step, thereby rubbing the lower substrate at an angle of 45 ° from the top to the bottom as described above. As a result, rubbing defects are generated by the stepped portion of the accumulation capacitor region, causing light leakage in the region.

At this time, the rubbing direction cannot be changed to match the main viewing angle, and the aperture ratio of the liquid crystal display device when the BM is formed in the region of the upper substrate corresponding to the region to overcome the light leakage caused by the rubbing failure. There is a problem of this deterioration.

According to an embodiment of the present invention, a predetermined portion of a gate line used as a first electrode of an accumulation capacitor and a pixel electrode portion adjacent to the gate line are formed to be inclined in the same direction as the rubbing direction of the alignment layer, thereby preventing light leakage. It is an object of the present invention to provide a liquid crystal display device that minimizes the amount.

In order to achieve the above object, a liquid crystal display device includes: a plurality of gate lines and data lines formed to cross each other on a lower substrate; A plurality of pixel electrodes formed on a region where the gate line and the data line cross each other; In a liquid crystal display device comprising a plurality of thin film transistors formed at the intersection of the gate line and the data line,

The predetermined portion of the gate line used as the first electrode of the storage capacitor and the pixel electrode portion adjacent to the gate line are formed to be inclined in the same direction as the rubbing direction of the alignment layer.

Here, the pixel electrode portion is formed at the front end of the gate line, and the lower region of the front pixel electrode electrically connected to the thin film transistor and the upper portion of the rear pixel electrode overlapping the gate line with a predetermined region to form an accumulation capacitor. It is characterized by an area.

In addition, an auxiliary electrode used as a second electrode of the storage capacitor is interposed between the gate line and a rear pixel electrode overlapping the gate line with a predetermined region.

In addition, the rubbing direction of the alignment layer is 45 degrees from the top to the bottom, and the thin film transistor includes a gate electrode, a source electrode, and a drain electrode, and the drain electrode of the thin film transistor is electrically connected to the front end pixel electrode. It features.

According to the present invention, the light leakage phenomenon can be minimized without increasing the mask, increasing the process, or changing the process. As a result, the contrast ratio can be secured while maintaining the same aperture ratio by minimizing the light leakage phenomenon.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is an enlarged plan view schematically illustrating some pixels of an array substrate for a liquid crystal display according to the present invention.

Referring to FIG. 4, a gate line 43 and a data line 45 cross each other to define a pixel region P on an array substrate for a liquid crystal display device, that is, a lower substrate according to the present invention. The thin film transistor T composed of the gate electrode 51, the source electrode 53, and the drain electrode 55 is formed at the intersection of the 43 and the data line 45.

In addition, a first pixel electrode 47 and a second pixel electrode 49 are formed in an area where the gate line 43 and the data line 45 intersect, that is, the pixel area P. FIG. The first pixel electrode 47 is a pixel electrode formed in the front pixel area based on the gate line 43, and the second pixel electrode 49 is a pixel electrode formed in the rear pixel area based on the gate line 43. .

In an exemplary embodiment of the present invention, the gate line 43 crosses the front pixel area and the rear pixel area of the pixel area P with a predetermined slope, and the first pixel electrode 47 and the first pixel electrode adjacent to the gate line 43 are formed. The two pixel electrodes 49 are also formed at predetermined inclination in parallel with the gate line 43. The gate line 43 is formed to have a predetermined angle in the same direction as the rubbing direction of the alignment layer. In addition, the data line 45 crossing the gate line 43 is formed in a straight line direction perpendicular to the lower substrate as in the prior art.

Here, the portion of the pixel electrode which is formed to have a slope corresponding to the gate line 43 is formed at the front end of the gate line 43 of the first pixel electrode 47 electrically connected to the thin film transistor. The upper region of the second pixel electrode 49 overlapping the lower region and the gate line 43 with a predetermined region to form a storage capacitor. Accordingly, the gate line 43 is the rear pixel in the lower region of the front pixel region at a predetermined angle with respect to the data line 45 in the pixel region P (to have the same 45 ° angle as the rubbing direction in the drawing). It is formed in the direction of the upper region of the region. That is, the gate line 43 is formed in the form of cutting in the diagonal direction with respect to the center portion of the pixel region P. FIG. Correspondingly, the side surface of the lower region of the first pixel electrode 47 and the side surface of the upper region of the second pixel electrode 49 have the same angle as that of the gate line 43. As shown in FIG. 4, the side surfaces of the first pixel electrode 47 and the second pixel electrode 49 which are not adjacent to the gate line 43 but adjacent to the data line 45 are formed in a vertical direction. It is formed in parallel with the data line 45, respectively. That is, the first pixel electrode 47 and the second pixel electrode 49 have a vertical surface on the left and right sides adjacent to the data line 45 and are formed to cross the pixel region P to have the predetermined slope. Upper and lower surfaces of the first pixel electrode 47 and the second pixel electrode adjacent to the gate line 43 are formed to have the same inclination angle as the rubbing direction.

The source electrode 53 and the drain electrode 55 of the thin film transistor are configured to be spaced apart from each other by a predetermined interval on the gate electrode 51, and an active channel (not shown) is exposed between the drain electrode 55 and the drain electrode 55. The first pixel electrode 47 is electrically connected to the first pixel electrode 47 to transmit a signal applied from the data line 45.

That is, when a predetermined scanning pulse is applied to the gate electrode 51 of the thin film transistor, the voltage of the gate electrode 51 is increased accordingly, and the thin film transistor is turned on. At this time, a liquid crystal driving voltage is applied to the liquid crystal from the data line 45 through the first pixel electrode 47 via the source and drain electrodes 53 and 55 of the thin film transistor T and consequently the liquid crystal capacitance. The pixel capacity combined with the storage capacity is charged.

The storage capacitor may include an on-gate including a portion of the gate line 43 and a portion of the second pixel electrode 49 overlapping the gate line 43, and a portion of the gate line 43 and the auxiliary electrode 48 overlapping the gate line 43. It is formed by an on-gate accumulation capacitor.

FIG. 5 is a sectional view of a specific portion II-II of FIG. 4, which is a sectional view of the accumulation capacitor region. FIG.

Referring to FIG. 5, a gate line 43 used as a first electrode of an accumulation capacitor is formed on a substrate 500, and a gate insulating layer 42 is formed on an exposed surface of the substrate including the gate line 43. ) Is formed.

An auxiliary electrode 48 used as the second electrode of the capacitor formed of the metal layer for source / drain electrode formation is formed on the gate insulating layer 42.

In addition, the passivation layer 44 covers the auxiliary electrode 48, and a contact hole exposing a part of the auxiliary electrode 48 is formed in the passivation layer 44, and the pixel electrode 49 is formed through the contact hole. It is formed on the passivation layer 44 while being connected to the auxiliary electrode 48.

As described above, when the array substrate provided with the gate line 43, the data line 45, and the pixel, that is, the lower substrate, is formed, it is bonded to the upper substrate (not shown), and the liquid crystal layer (not shown) therebetween. At this time, the gate line 43, the data line 45, the thin film in order to prevent the light emitted through the back light to the lower portion of the lower substrate to prevent leakage in areas other than the pixel The black matrix BM is formed in a region on the upper substrate (not shown) overlapping the transistor T or the like.

The portion 40 in which the black matrix BM is formed is shown in FIG. 4.

In addition, upper and lower alignment layers (not shown) are formed on the upper and lower substrates to facilitate the alignment of the liquid crystal when voltage is applied to the contact surface with the liquid crystal layer, respectively.

In general, the alignment layer is subjected to a rubbing treatment in order to make the alignment of the liquid crystal constant and to give a pretilt angle for easily inducing the alignment of the liquid crystal. The rubbing treatment is to form a certain groove in the alignment layer by applying a pressure to the rotating roller wrapped with a rubbing cloth while maintaining a constant angle with the substrate, in the case of a substrate having a stepped portion, rubbing failure may occur with respect to the stepped portion.

In this case, since the lower substrate is manufactured by repeating a plurality of processes, that is, deposition, photolithography, and the like, many times, compared to the upper substrate, a plurality of array elements form a step, and a step frequency is higher than that of the upper substrate. Becomes high.

In the conventional case, since the gate capacitor, the auxiliary electrode, and the pixel electrode are stacked in the accumulation capacitor region, the stepped portion is formed to be large. Thus, when the lower substrate is rubbed at an angle of 45 ° from the top to the bottom, There was a problem in that rubbing is caused by the stepped portion, causing light leakage in the area.

In order to overcome the above-described problems, the present invention provides a method for overcoming the gate line in the region crossing the pixel region P, that is, the gate line used as the first electrode of the storage capacitor and adjacent to the gate line on the region. The pixel electrode portion is formed to be inclined in the same direction as the rubbing direction of the alignment layer.

At this time, since the rubbing direction of the alignment layer is 45 degrees from the top to the bottom, the gate line in the region and the pixel electrode portion adjacent to the gate line are formed in such a manner as to be inclined from the top to the bottom by 45 degrees.

Here, the pixel electrode portion is formed at the front end of the gate line 43 as shown in FIG. 4, and the lower region and the gate line of the first pixel electrode 47 electrically connected to the thin film transistor. The upper region of the second pixel electrode 49 overlapping with the predetermined region 43 to form the storage capacitor.

By forming the accumulation capacitor region in which the large stepped portion is formed so as to coincide with the rubbing direction, it is possible to overcome the light leakage phenomenon due to rubbing failure in the region.

As a result, when the structure of the present invention is taken, light leakage can be minimized while maintaining the same aperture ratio, thereby improving the image quality of the liquid crystal display.

According to the liquid crystal display according to the present invention, the light leakage phenomenon can be minimized without increasing the mask, increasing the process, or changing the process. As a result, the contrast ratio can be secured while maintaining the same aperture ratio by minimizing the light leakage phenomenon. There is an advantage.

Claims (6)

A plurality of gate lines and data lines formed to cross each other on the lower substrate; A plurality of pixel electrodes formed on a region where the gate line and the data line cross each other; In a liquid crystal display device comprising a plurality of thin film transistors formed at the intersection of the gate line and the data line, A front pixel region and a rear pixel region are defined as pixel regions based on a gate line intersecting the data line, and pixel electrodes formed in the front pixel region and the rear pixel region are referred to as a first pixel electrode and a second pixel electrode, respectively. when doing, The data line is formed in a straight line perpendicular to the lower substrate, the gate line intersecting the data line is formed across the pixel area in the same direction as the rubbing direction of the alignment layer, The side of the first pixel electrode formed in the front pixel region adjacent to the gate line and the side of the second pixel electrode formed in the rear pixel region are inclined at the same slope to be parallel to the gate line and adjacent to the vertical data line. And side surfaces of the first pixel electrode and the second pixel electrode are parallel to the data line, respectively. The method of claim 1, The storage capacitor of the rear pixel region includes the gate line as the first electrode of the storage capacitor, and an auxiliary electrode electrically connected to the second pixel electrode of the rear pixel region as the second electrode of the storage capacitor. Display. 3. The method of claim 2, And the auxiliary electrode is disposed to overlap the gate line. The method of claim 1, And a rubbing direction of the alignment layer is 45 degrees from top to bottom. 3. The method of claim 2, The thin film transistor includes a gate electrode, a source electrode, and a drain electrode, and the drain electrode of the thin film transistor is electrically connected to the first pixel electrode. The liquid crystal display of claim 1, wherein the first pixel electrode is spaced apart from the gate line, and the second pixel electrode partially overlaps the gate line.

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