KR100945995B1 - Method for forming metal wires in a semiconductor device - Google Patents

Abstract

The present invention relates to a method for forming a metal wiring of a semiconductor device, the method comprising the steps of forming a first insulating film, an etch stop layer and a second insulating film on a semiconductor substrate subjected to a predetermined process, and the predetermined portion of the semiconductor substrate is exposed Patterning a second insulating film, an etch stop layer, and a first insulating film to form a contact hole, forming a first metal layer on the second insulating film so that the contact hole is filled, and forming a first hole on the second insulating film Forming a trench by patterning the second insulating layer and the etch stop layer by an etching process using the first metal layer pattern as a mask after patterning the metal layer, and forming a second metal layer on the entire upper surface of the trench to fill the trench And removing the second metal layer and the remaining first metal layer pattern on the second insulating layer so that metal wiring is formed in the trench. It includes.

Metal wiring, damascene, trench, hard mask, contact resistance

Description

Method for forming metal wires in a semiconductor device             

1A and 1B are cross-sectional views for explaining a metal wiring formation method of a conventional semiconductor device.

FIG. 2 is a TEM photograph of portion “A” of FIG. 1A. FIG.

3A and 3B are enlarged cross-sectional views of portion “B” of FIG. 1A.

4 is a TEM photograph for explaining a metallization method of a conventional semiconductor device.

5A to 5H are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

FIG. 6 is a TEM photograph of portion “C” of FIG. 5G

<Description of the symbols for the main parts of the drawings>

1, 51: semiconductor substrate 2, 52: memory cell

3, 4, 53, 54: transistor 5, 55: first insulating film

6, 56: second insulating film 7, 57: etch stop layer

8, 58: third insulating film 9, 63: trench

10, 60: junction 11, 59: contact hole                 

12, 64a: metal wiring 61, 64: metal layer

61a: metal pattern 62: photosensitive film

65: interlayer insulating film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices capable of maintaining the width of the metal wirings as desired while ensuring sufficient spacing between the metal wirings.

As the degree of integration of the semiconductor memory device increases, the size of the pattern and the spacing between the patterns are slightly reduced. Therefore, the conventional technique of patterning the metal layer to form the metal wiring and then embedding the oxide film to form the insulating film is difficult to apply any more. Therefore, in recent years, metal wirings are formed using a damascene process, and a method of forming metal wirings of a conventional semiconductor device using the damascene process will be described with reference to FIGS. 1A and 1B.

Referring to FIG. 1A, a plurality of memory cells 2 and select transistors 3 are formed on a semiconductor substrate 1 in a memory cell array region through a predetermined process, and a plurality of semiconductor substrates 1 are formed on a semiconductor substrate 1 in a peripheral circuit region. The high voltage and low voltage transistors 4 are formed.

After the first and second insulating films 5 and 6 are sequentially formed on the entire upper surface, an etch stop layer 7 and a third insulating film 8 for forming trenches are formed on the second insulating film 6. . In this case, the etch stop layer 7 is formed of a nitride film, and the third insulating film 8 is formed of an oxide film.

The third insulating film 8 and the etch stop layer 7 are sequentially patterned to form a trench 9 in which metal wiring is to be formed, and then the second insulating film 6 and the first insulating film 5 in the exposed portions. The contact hole 11 is formed to pattern the semiconductor substrate 1 to expose the junction 10 of the semiconductor substrate 1.

As described above, when the contact hole 11 is formed, a natural oxide film is grown on the surface of the semiconductor substrate 1 exposed through the contact hole 11, and organic impurities generated during the etching process are formed in the contact hole 11. impurity, polymer or particle. Since these impurities increase the contact resistance with the metal wiring, the contact holes 11 are formed and then a cleaning process is performed to remove them.

Referring to FIG. 1B, a metal such as tungsten (W) is deposited on the entire upper surface of the contact hole 11 and the trench 9 to be buried, followed by a chemical mechanical polishing (CMP) process or an etchback process. When the metal is polished and planarized, metal wiring 12 is formed in the trench 9 and the contact hole 11.

In the damascene process as described above, the trench 9 is formed to a size of 100 nm or less. Therefore, it is important to secure the distance between the metal wires 12 during the photolithography process for forming the trench 9 to prevent cross talk caused by the interference between the metal wires. However, when the distance between the metal wires 12 is secured, since the size of the trench 9 is relatively reduced, it is difficult to determine the photoresist that serves as an etch stop layer. That is, in order to form the fine trench 9 having a large step, a photoresist having a step ratio of 3: 1 to 5: 1 should be used. In this case, the photoresist may collapse due to the large step and the focus margin may be increased. There are problems such as difficult to secure.

In addition, in the dual damascene process as described above, the trench 9 and the contact hole 11 are formed and then cleaned to secure contact resistance with the semiconductor substrate 1. Due to the difference in the etch selectivity between the etch stop layer 7 and the insulating films 6 and 8 formed of the oxide film, as shown in FIG. 2, the insulating film 8 collapses or the gap between the trenches 9 becomes narrow, which makes it difficult to embed the metal. Electrical shorts and crosstalk with metal wires are caused. 3A and 3B partially illustrate a cross section of the trench 9 and the contact hole 11 formed and subjected to a cleaning process.

In the case of using a single damascene process or an etch back process, since the contact area of the metal becomes narrow in the upper portion of the fine contact hole as shown in FIG. 4, an electric resistance increases.

Accordingly, an object of the present invention is to provide a method for forming a metal wiring in a semiconductor device which can solve the above-mentioned disadvantages by forming a hard mask for trench formation by forming a metal layer for filling contact holes and then patterning the metal layer. have.

The present invention for achieving the above object is a step of forming a first insulating film, an etch stop layer and a second insulating film on a semiconductor substrate subjected to a predetermined process, the second insulating film, to expose a predetermined portion of the semiconductor substrate, Patterning an etch stop layer and a first insulating layer to form a contact hole, forming a first metal layer on the exposed semiconductor substrate and the second insulating layer to fill the inside of the contact hole, and forming the contact hole; Forming a trench by patterning the second insulating layer and the etch stop layer by an etching process using the first metal layer pattern as a mask after patterning the first metal layer on the first metal layer pattern; Forming a second metal layer on the upper surface, removing the second metal layer and the remaining first metal layer pattern on the second insulating layer; Characterized in that it comprises the step of: so that the metal wiring formed in the wrench.

The method may further include performing a cleaning process after removing the contact hole to remove organic impurities, polymers, or particles generated during the etching process.

The second metal layer and the remaining first metal layer pattern may be removed by a chemical mechanical polishing process or an etch back process.

As semiconductor devices are increasingly integrated and finely patterned, problems caused by crosstalk between metal wirings are critical to device defects in NAND flash memory devices. Crosstalk is a phenomenon in which a malfunction occurs due to the shaking of the voltage when the adjacent metal wiring is reversed by the capacitance between the metal wirings when a signal (voltage) is applied to the desired metal wiring when the spacing between the metal wirings is minute. As a result, the operation speed of the device may be reduced or a malfunction may be caused.

To prevent cross talk, the capacitance between metal wirings should be reduced. To do this, first, increase the width of the insulating film between the metal wirings, second, reduce the height of the metal wirings, third, use a low dielectric film, or fourth. However, the thickness of the nitride film used as the etch stop layer should not be reduced or used.

Accordingly, the present invention provides a method for forming metal wirings in a semiconductor device capable of maintaining the width of the metal wirings as desired while ensuring sufficient width of the insulating film between the metal wirings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5A to 5H are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

Referring to FIG. 5A, a plurality of memory cells 52 and select transistors 53 are formed on a semiconductor substrate 51 in a memory cell array region through a predetermined process, and a plurality of semiconductor substrates 51 are formed on a semiconductor substrate 51 in a peripheral circuit region. The high voltage and low voltage transistors 54 are formed.                     

After the first and second insulating films 55 and 56 are sequentially formed on the entire upper surface, an etch stop layer 57 and a third insulating film 58 for forming trenches are formed on the second insulating film 56. . In this case, the etch stop layer 57 may be formed by using a nitride oxide-based silicon oxide film or a silicon nitride film (SiN, SiON, etc.) having an etching selectivity with respect to a general interlayer insulating film in a low temperature reactor or by plasma chemical vapor deposition (CVD). The third insulating film 58 is formed by depositing a thickness of 300 to 1000 GPa, and the third insulating film 58 is formed of an oxide film such as BPSG, PSG, FSG, PE-TEOS, PE-SiH ₄ , HDP, USG, HDP, PSG, APL, etc. It is formed by depositing at a thickness of.

The third insulating layer 58, the etch stop layer 57, the second insulating layer 56, and the first insulating layer 55 are sequentially etched so that the junction portion 60 of the semiconductor substrate 51 is exposed to the contact hole 59. ).

Referring to FIG. 5B, a cleaning process is performed to remove a natural oxide film grown on the surface of the semiconductor substrate 51 exposed through the contact hole 59 and organic impurities, polymers or particles generated during the etching process. . After the diffusion barrier (not shown) is formed on the entire upper surface including the contact hole 59, a metal layer 61 is deposited by depositing tungsten (W) or the like on the diffusion barrier so that the contact hole 59 is buried. ). The diffusion barrier is formed by depositing Ti / TiN or WN by physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the metal layer 61 is formed by W, TiSix, TiN, by chemical vapor deposition (CVD). It is formed by depositing Cu, Al and the like. The cleaning process and the diffusion barrier and the metal layer forming process are performed continuously so that no time delay occurs.

Referring to FIG. 5C, after forming an anti-reflection film (not shown) and a photoresist layer 62 on the metal layer 61, the photoresist layer 62 is patterned by using a trench forming mask for forming metal wiring.

Referring to FIG. 5D, the metal layer 61 and the diffusion barrier layer formed on the third insulating layer 58 are sequentially patterned by an etching process using the patterned photoresist layer 62 as a mask to form a hard mask. After the metal pattern 61a to be used is formed, the photosensitive film 62 is removed.

Referring to FIG. 5E, in the etching process using the metal pattern 61a as a hard mask, the trench 63 may be etched by etching the exposed third insulating layer 58 until the etch stop layer 57 is exposed. Form. Thereafter, the etch stop layer 57 of the exposed portion is etched. At this time, the lower second insulating layer 56 may be partially etched. Since the metal pattern 61a used as the hard mask is reduced in thickness by etching, the overall step is reduced, and the metal layer 61 embedded in the contact hole 59 is exposed in a cylindrical shape in the trench 63. do.

The process of FIGS. 5D and 5E may be performed in-situ in one chamber or continuously in a single apparatus having several chambers.

Referring to FIG. 5F, after forming a diffusion barrier (not shown) on the entire upper surface including the trench 63, a metal layer is deposited by depositing tungsten (W) or the like on the diffusion barrier to fill the trench 63. Form 64.

The diffusion barrier layer is formed by depositing Ti, TiN, WN, etc. by chemical vapor deposition (CVD), and the metal layer 64 is formed by depositing W, Cu, Al, etc. by chemical vapor deposition (CVD).

Referring to FIG. 5G, when the metal layer 64 and the remaining metal pattern 61a are planarized by a chemical mechanical polishing (CMP) process or an etch back process until the third insulating layer 58 is exposed, the trench 63 ), Metal wiring 64a is formed. In this case, as shown in FIG. 6, the metal wire 64a is connected to the metal layer 61 protruding in the form of a cylinder in the trench 63, and the contact resistance is reduced due to the shape of the water column having a large contact area. In the chemical mechanical polishing (CMP) process, the metal layer 64 is polished using SiO ₂ or spherical Al ₂ O ₃ having a pH of 2-8 and a particle size of 50 to 150 nm. .

Referring to FIG. 5H, an interlayer insulating film 65 is formed on the entire upper surface of the metal wiring 64a to electrically insulate the upper conductive layer.

As described above, the present invention uses the photoresist as a mask to form a contact hole, and then proceeds with a cleaning process and embeds metal into the contact hole. The metal layer for filling the contact holes is patterned to form a hard mask for trench formation. Therefore, the loss of the insulating film during the cleaning process does not affect the size of the trench. Accordingly, the width of the metal wiring can be maintained as desired while sufficiently securing the gap between the metal wirings, thereby preventing crosstalk and improving device reliability. And yield can be increased. In addition, since the cylindrical metal layer protrudes in the process of forming the trench, the contact resistance with the metal wiring is reduced by increasing the surface area, thereby improving the operation speed of the device.

Claims (10)

(a) forming a first insulating film, an etch stop layer and a second insulating film on a semiconductor substrate which have been subjected to a predetermined process; (b) forming a contact hole by patterning the second insulating film, the etch stop layer and the first insulating film so that a predetermined portion of the semiconductor substrate is exposed; (c) forming a first metal layer on the exposed semiconductor substrate and the second insulating layer to fill the inside of the contact hole; (d) patterning the first metal layer on the second insulating layer to form a first metal layer pattern, and then forming the trench by patterning the second insulating layer and the etch stop layer by an etching process using the first metal layer pattern as a mask Wow, (e) forming a second metal layer over the entire upper surface such that the trench is buried; (f) removing the second metal layer and the remaining first metal layer pattern on the second insulating layer to form metal wiring in the trench. The method of claim 1, wherein the etch stop layer is formed of an oxide film or a silicon nitride film of a nitride film type, and is formed to a thickness of 300 to 1000 Å. The method of claim 1, wherein the third insulating layer is formed of BPSG, PSG, FSG, PE-TEOS, PE-SiH ₄ , HDP, USG, HDP, PSG, or APL, and has a thickness of 2000 to 4000 μs. A metal wiring formation method of a semiconductor device. The method of claim 1, further comprising performing a cleaning process to remove organic impurities, polymers, or particles generated after the step (b). The method of claim 1, further comprising: forming a first diffusion barrier along the entire upper surface including the contact hole before forming the first metal layer; And forming a second diffusion barrier along the entire upper surface including the trench before forming the second metal layer. The method of claim 1, wherein the first metal layer is formed of W, TiSix, TiN, Cu, or Al. The semiconductor according to claim 1, wherein the steps (c) and (d) proceed in-situ in one chamber or continuously in a single device having several chambers. Metal wiring formation method of a device. The method of claim 1, wherein the second metal layer is formed of W, Cu, or Al. The method of claim 1, wherein the second metal layer and the remaining first metal layer pattern are removed by a chemical mechanical polishing process or an etch back process. The method of claim 9, wherein the chemical mechanical polishing process is performed using SiO ₂ or spherical Al ₂ O ₃ in a gaseous state having a pH of 2-8 and a particle size of 50 to 150 nm. Metal wiring formation method.

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