KR100848108B1 - liquid crystal display, thin film transistor array plate and method for fabricating the plate - Google Patents

Abstract

A gate wiring including a gate line, first and second gate electrodes is formed on an insulating substrate, and a gate insulating film, first and second semiconductor layers, and an ohmic contact layer are sequentially formed thereon. A data line including first and second data lines, a data line connection part, first and second source electrodes, and first and second drain electrodes is formed on the ohmic contact layer. A thick passivation layer is formed on the data line, and a contact hole for electrically connecting the first and second drain electrodes and the pixel electrode is formed in the passivation layer. A pixel electrode is formed on the passivation film, and the pixel electrode overlaps the upper portion of the data line. In this way, by forming one data line on each side of the pixel region, the variation in pixel voltage due to parasitic capacitance is equalized between divided regions having different degrees of misalignment. The parasitic capacitances of the gate electrode and the drain electrode are the same between the two generated regions to equalize the fluctuations in the pixel voltage to prevent uneven brightness, and the aperture ratio is increased by superimposing the pixel electrodes on two data lines. You can.

Pixel voltage, parasitic capacitance, misalignment, brightness unevenness

Description

Liquid crystal display device, thin film transistor substrate and manufacturing method thereof {liquid crystal display, thin film transistor array plate and method for fabricating the plate}

1 is a layout view illustrating a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1;

3A illustrates a case in which the data line is formed to the left side with respect to the pixel electrode due to misalignment of the mask.

3B shows a case in which the data line is biased to the right with respect to the pixel electrode,

FIG. 3C illustrates a change in pixel voltage of FIGS. 3A and 3B.

4A illustrates a case where the first data line is biased to the pixel electrode.

4B illustrates a case where the second data line is biased to the pixel electrode.

5 is a layout view illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

6 is a cross-sectional view taken along the line VI-VI 'in FIG. 5,

FIG. 7 is a layout view illustrating a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along line VII-VII 'in FIG. 7,

9 is a schematic cross-sectional view of a liquid crystal display device according to the prior art,                 

10 is a schematic cross-sectional view of a liquid crystal display according to a third exemplary embodiment of the present invention.

11A is a layout view showing a thin film transistor substrate in a first step of manufacturing according to an embodiment of the present invention;

FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ in FIG. 11A.

12A is a layout view at the next step of FIG. 11A;

FIG. 12B is a cross-sectional view taken along the line XIIb-XIIb 'in FIG. 12A;

FIG. 13A is a layout view in the next step of FIG. 12A;

FIG. 13B is a cross-sectional view taken along line XIIIb-XIIIb 'in FIG. 13A;

FIG. 14a is a layout view in the next step of FIG. 13a;

FIG. 14B is a cross sectional view taken along line XIVb-XIVb ′ in FIG. 14A;

15 to 18 are cross-sectional views sequentially showing a sequence of processes in a subsequent step of FIG. 11B according to another embodiment of the present invention.

19A is a layout view at the next stage of FIG. 18,

19B is a cross sectional view taken along a line XIX-XIX ′ in FIG. 19A;

20A is a layout view at the next stage of FIG. 19A,

20B is a cross-sectional view taken along line XXb-XXb 'in FIG. 20A.

FIG. 21A is a layout view of the next step of FIG. 20A;

FIG. 21B is a cross-sectional view taken along line XXIb-XXIb ′ in FIG. 21A.

The present invention relates to a liquid crystal display device, a thin film transistor substrate thereof and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two glass substrates on which electrodes are formed and a liquid crystal layer interposed therebetween. A display device for controlling the amount of light transmitted by rearranging them.

One substrate of such a liquid crystal display generally has a thin film transistor for switching a voltage applied to an electrode, and a wiring including a gate line and a data line is formed on the thin film transistor substrate in addition to the thin film transistor. A pixel electrode electrically connected to the thin film transistor is formed in the pixel region defined by the intersection of the gate line and the data line.

In such a liquid crystal display device, a storage capacitor should be formed to improve the charge storage capability of the pixel. A method of forming such a storage capacitor includes a front gate method and an independent wiring method.

In the front gate method, a storage capacitor is formed by overlapping a gate line and a pixel electrode of neighboring pixels with an insulating film interposed therebetween. In the independent wiring method, a separate storage electrode wiring and a pixel electrode separated from the gate line are overlapped with an insulating film interposed therebetween. Thereby forming a holding capacity. In the case of forming the storage capacitor by the independent wiring method, there is an advantage in that the signal delay can be reduced in the large screen liquid crystal display of 30 inches to 40 inches.

On the other hand, a large number of photolithography processes are used to manufacture a large-screen liquid crystal display device. In this case, the divisional exposure method of dividing into two or more areas and exposing several times without exposing at one time is used. different. As a result, brightness unevenness occurs in each divided region, and two reasons can be cited. First, there is a difference in distance between the data line and the pixel electrode between the divided regions due to misalignment. In the case of the divided region in which the pixel electrode is formed close to the right data line and the divided region in which the pixel electrode is formed close to the left data line, Each pixel voltage is different. Next, the parasitic capacitance value generated between the gate electrode and the drain electrode is different between the divided regions due to misalignment. In the case of the divided region where the gate electrode and the drain electrode are formed far from the divided region, the parasitic capacitance is formed. This causes different kickback voltages and thus different pixel voltages.

In addition, in order to minimize signal interference between the pixel electrode and the data line, the pixel electrode is not overlapped on the upper portion of the data line, and a black matrix is generally formed around the line. However, the black matrix has a problem of lowering the aperture ratio. .

An object of the present invention is to prevent uneven brightness between divided regions and to increase aperture ratio in a liquid crystal display device.

In order to achieve this problem, the present invention forms two data lines to which the same signal is applied to the pixel area, and the pixel electrodes are overlapped on the two data lines.

The liquid crystal display according to the present invention includes a first insulating substrate, a gate line formed on the first insulating substrate, and a gate including first and second gate electrodes connected to the gate line and positioned at a predetermined distance from each other. First and second data lines positioned at a predetermined distance and defining a pixel area intersecting the wiring and the gate line, and first and second source electrodes that are part of each of the first and second data lines, and the first and second sources. First and second drain electrodes facing the source electrodes, respectively, and are formed for each of the data lines insulated from and intersecting with the gate lines, the pixel regions of the matrix form defined by the gate lines and the data lines crossing each other, A pixel former formed with a passivation layer having at least one contact hole for electrically connecting the data line. A thin film transistor connected to the pole, the gate wiring, the data wiring, and the pixel electrode, a first domain dividing means formed on the first insulating substrate, a second insulating substrate facing the first insulating substrate, and the second insulating substrate facing the first insulating substrate. 2, a color filter formed on the insulating substrate, a common electrode formed on the color filter, and second domain dividing means formed on the second insulating substrate.                     

The pixel electrode may be formed to overlap at least a portion of the data line including the first and second data lines. In this case, the thickness of the protective film formed between the data line and the pixel electrode is preferably 3 μm or more.

Further, the first and second domain dividing means may be a projection pattern or an opening pattern, wherein one of the first and second domain dividing means is a projection pattern, and the other domain dividing means is an opening. It may be a pattern.

On the other hand, the thin film transistor substrate according to the present invention, the gate line formed on the insulating substrate and the gate wiring including the first and second gate electrodes which are positioned at a predetermined distance connected to the gate line, covering the gate wiring A gate insulating layer, first and second semiconductor layers formed on the first and second gate electrodes, respectively, first and second data lines positioned at a predetermined distance to define a pixel area crossing the gate line, and the second and second data lines First and second source electrodes that are part of each of the first and second data lines, a data line including first and second drain electrodes facing the first and second source electrodes, respectively, and the first and second drain electrodes A protective film having at least one first contact hole for electrically connecting the pixel electrode to the pixel electrode, wherein the passivation layer is electrically connected to the first and second drain electrodes. A pixel electrode is included, and the same signal is applied to the first and second data lines.

The data line may be formed on the upper and lower portions of the pixel area, and further include a data line connection part connecting the first and second data lines.                     

It is also preferable to further include a storage capacitor line which is formed in the same layer as the gate line in parallel. Further, it is preferable to further include a storage capacitor conductor pattern formed to overlap the storage capacitor line. In this case, the semiconductor device may further include a conductor pattern connection unit connecting the drain electrode of the data line and the conductive capacitor pattern.

The first contact hole formed in the passivation layer may be formed on the conductive pattern conductor for the storage capacitance.

In addition, the first and second semiconductor layers and the data line except for the space between the first source electrode and the first drain electrode and between the second source electrode and the second drain electrode may have the same planar shape. In this case, it is preferable to further include an ohmic contact layer formed between the first and second semiconductor layers and the data line. The ohmic contact layer and the data line may have the same planar shape.

The gate line further includes a gate pad for applying a signal to the gate line, the data line further includes a data pad for applying a signal to the data line, and the protective layer includes the gate pad and the data pad. Second and third contact holes respectively exposing the second and third contact holes, the auxiliary gate pads being formed in the same layer as the pixel electrode and connected to the gate pad and the data pad through the second and third contact holes, respectively; It may further include an auxiliary data pad.

The pixel electrode may overlap the upper portion of the data line including the first and second data lines. In this case, the thickness of the protective film formed between the data line and the pixel electrode is preferably 3 μm or more.

According to an aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate, the method including: forming a gate line including a gate line and first and second gate electrodes positioned at a predetermined distance from the gate line on an insulating substrate, and the gate Forming an insulating film, forming a first and a second semiconductor layer, first and second data lines and a first and second data lines positioned at a predetermined distance to define a pixel area crossing the gate line. Forming a data line including first and second source electrodes that are part of the first and second source electrodes respectively facing the first and second source electrodes, and forming the first and second drain electrodes as pixel electrodes Forming a protective film having at least one first contact hole for electrically connecting with the first electrode; the pixel connected with the first and second drain electrodes It comprises the step of forming a pole.

In this case, it is preferable to form a data line connection part connecting the first and second data lines in the step of forming the data line.

In the forming of the gate wiring, it is preferable to form a storage capacitor line in parallel with the gate line, and in the forming of the data wiring, a conductive capacitance conductor pattern overlapping the storage capacitor line may be formed. In the forming of the data line, a conductor pattern connection part connecting the drain electrode and the storage capacitor conductor pattern may be formed.

Further, the first contact hole of the protective film is preferably formed on the conductive pattern conductor for the storage capacitance.

The semiconductor layer and the data line may be formed together by a photolithography process using a photoresist pattern having a different thickness depending on a location.

Further, in the gate wiring forming step, a gate pad for applying a signal to the gate line is further formed, and in the data wiring forming step, a data pad for applying a signal to the data line is further formed. And forming second and third contact holes respectively exposing the gate pad and the data pad, respectively, connected to the gate pad and the data pad through the second and third contact holes, respectively, and assisting with the same layer as the pixel electrode. The method may further include forming a gate pad and an auxiliary data pad.

In the protective film forming step, the first contact holes may be formed in the first and second drain electrodes, respectively, to have two first contact holes.

In the pixel electrode forming step, the pixel electrode may be formed to overlap the upper portion of the data line including the first and second data lines.

In the present invention, the data lines are formed on each side of the pixel area one by one to make the fluctuations in pixel voltage due to parasitic capacitance between divided areas having different degrees of misalignment, and two thin film transistors formed on each pixel area to the left and right. The parasitic capacitance by the gate electrode and the drain electrode is the same between the two divided regions where misalignment occurs, so that variations in the pixel voltage are made equal to prevent brightness unevenness. In addition, the aperture ratio can be increased by superimposing the pixel electrodes on the data lines formed one on each side of the pixel region.

Then, the liquid crystal display according to the exemplary embodiment of the present invention, the thin film transistor substrate thereof, and the manufacturing method thereof will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. Explain.

First, the structure of the liquid crystal display according to the first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a layout view illustrating a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II 'of FIG. 1.

First, the structure of the "lower board | substrate" of a liquid crystal display device is demonstrated.

As shown in FIGS. 1 and 2, the thin film transistor substrate, which is a “bottom substrate”, includes aluminum (Al) or aluminum alloy, molybdenum (Mo), or molybdenum-tungsten alloy (MoW alloy) on the insulating substrate 10. Gate wirings 21, 221, and 222 made of metal or a conductor such as chromium (Cr) and tantalum (Ta) and the storage capacitor line 25 are formed. The gate line includes a gate line 21 extending in the horizontal direction and first and second gate electrodes 221 and 222 which are formed at a predetermined distance while being part of the gate line 21. The storage capacitor line 25 is formed in parallel with the gate line 21 between the gate lines 21, and overlaps the pixel electrode 80 to be described later to maintain the storage capacitance between the insulating films 30 and 70. Form.

The gate wirings 21, 221, 222 and the storage capacitor line 25 may be formed in a single layer, but may be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is made of a material having a low resistance and the other layer is made of a material having good contact properties with other materials, for example, a double layer of Cr / Al (or Al alloy) or Al (Or Al alloy) / Mo double layer is mentioned.

The gate wirings 21, 221, and 222 and the storage capacitor line 25 are covered with the gate insulating film 30 made of silicon nitride (SiN _X ).

A first semiconductor layer 411 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30 on the first gate electrode 221, and an n type like phosphorous (P) is formed on the first semiconductor layer 411. Resistive contact layers 521 and 531 made of a semiconductor such as amorphous silicon doped with impurities are formed on both sides of the first gate electrode 221. The second semiconductor layer 412 is formed on the gate insulating layer 30 on the second gate electrode 222, and the ohmic contacts 522 and 532 are formed on the second semiconductor layer 412. It is formed separately from both sides about 222.

On the ohmic contacts 521, 531, 522, and 532 and the gate insulating layer 30, data wires 611, 612, 613, which are made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium, tantalum, or the like. 614, 621, 631, 622, and 632 are formed. The data line extends in the vertical direction at a predetermined distance, and intersects the gate line 21 to define the pixel area, and the first and second data lines 611 and 612 and the first and second data lines 611 and 612. ), And the data line connecting portions 613 and 614 formed adjacent to the gate line 21, the first source electrode 621 and the first gate electrode 221 which are part of the first data line 611. The first drain electrode 631 facing the first source electrode 621, the second source electrode centering on the second source electrode 622 and the second gate electrode 222 that are part of the second data line 612. And a second drain electrode 632 facing 622.

The data lines 611, 612, 613, 614, 621, 631, 622, and 632 may be formed in a single layer like the gate lines 21, 221, and 222, but may be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials.

Here, the first gate electrode 221, the first semiconductor layer 411, the first source electrode 621, and the first drain electrode 631 form the first thin film transistor, and the second gate electrode 222, the first The second semiconductor layer 412, the second source electrode 622, and the second drain electrode 632 form a second thin film transistor.

A protective film 70 made of silicon nitride is formed on the data wires 611, 612, 613, 614, 621, 631, 622, 632 and the gate insulating film 30. The passivation layer 70 has contact holes 721 and 722 exposing the first and second drain electrodes 631 and 632, respectively.

The pixel electrode 80 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the passivation layer 70.

The pixel electrode 80 is connected to the first and second drain electrodes 631 and 631 through the contact holes 721 and 722 to receive an image signal.

Next, the structure of the "upper substrate" facing the "lower substrate" of the liquid crystal display device according to the first embodiment of the present invention having such a structure will be described.

As shown in FIG. 2, the color filter substrate, which is an “top substrate,” has a black matrix 200 formed under a transparent insulating substrate 100 such as glass, and a color filter 300 formed under the black matrix 200. It is. An overcoat layer 600 is formed under the color filter 300, and a common electrode 400 made of a transparent conductive material such as ITO or IZO is formed under the overcoat layer 600.

Meanwhile, when the "lower substrate" of the liquid crystal display according to the exemplary embodiment of the present invention is manufactured by using the divided exposure method, brightness unevenness between the divided regions caused by the difference in distance between the pixel electrode and the data line between the divided regions can be prevented. have. This will be described in detail with reference to FIGS. 3A to 4B. 3A to 4B show only components necessary for convenience of description.

First, referring to FIGS. 3A to 3C, brightness unevenness occurring between divided regions in a thin film transistor substrate according to the related art will be described.

3A illustrates a case in which the data line is formed to be shifted to the left with respect to the pixel electrode due to misalignment of the mask, FIG. 3B illustrates a case in which the data line is to the right to the pixel electrode, and FIG. 3C is a pixel of FIGS. 3A and 3B. The change in voltage is shown.

As shown in FIGS. 3A and 3B, the pixel region is defined by the intersection of the gate line 21 and the data line 61, and the pixel electrode 80 is formed in each pixel region. The line 61 and the pixel electrode 80 are connected to the thin film transistor TFT. In such a structure, a gate signal and a data signal are applied from the gate line 21 and the data line 61, respectively, and a pixel voltage is applied to the pixel electrode 80 by the operation of the thin film transistor.

As shown in Figure 3a, the pixel electrode 80 in this case, the partition is formed closer to the right of the data line 61, the distance between the pixel electrode 80 and the D _j of the data line 61, D _{j- The} parasitic capacitance is greater in C _R1 than C _L1 because it is closer than the distance to the data line 61 of one. Here, after the pixel voltage of the pixel area A is positively charged with respect to the common voltage which is the reference voltage, the data line 61 of D _j is changed from positive to negative to charge the next row, and the pixel voltage of the pixel area C is After being negatively charged with respect to the common voltage as the reference voltage, the data line 61 of D _j-1 is varied from negative to positive to charge the next row. This causes the pixel voltage of the pixel area A is variable as long as the sum of the voltage V _L1 by the voltage V _R1 and the parasitic capacitance C _L1 due to the parasitic capacitance C _R1. Where V _R1 is negative and V _L1 is positive and | V _R1 | > V _L1 |, so V _R1 + V _L1 is negative.

Meanwhile, as shown in FIG. 3B, in the case of the divided region in which the pixel electrode 80 is formed closer to the left data line 61, the distance between the pixel electrode 80 and the data line 61 of D _j is D. _The parasitic capacitance is greater in C _L2 than in C _R2 because it is larger than the distance from the data line 61 of _j-1 . Here, as shown in FIG. 3A, after the pixel voltage of the A pixel region is positively charged with respect to the common voltage which is the reference voltage, the data line 61 of D _j is changed from positive to negative to charge the next row. After the pixel voltage of the C pixel region is negatively charged with respect to the common voltage which is the reference voltage, the data line 61 of D _j-1 is changed from negative to positive to charge the next row. This causes the pixel voltage of the pixel area A is variable as long as the sum of the voltage V _L2 by the voltage V _R2 and the parasitic capacitance C _L2 due to the parasitic capacitance C _R2. Where V _R2 is negative and V _L2 is positive and | V _R2 | V | _R2 + V _L2 is positive because <| V _L2 |

As described above, the pixel voltages V _p and V _{p ′} in the holding time fluctuate high or low with respect to the charging voltage depending on whether the data line is biased to the left or to the right with respect to the pixel electrode. That is, as shown in FIG. 3C, the variation amount and direction of the pixel voltages V _p and V _{p ′} vary depending on the mask misalignment state.

Accordingly, when a difference in the degree of misalignment between the pixel electrode 80 and the data line 61 occurs between the divided regions, the variation of the pixel voltage applied between the divided regions is changed, resulting in uneven brightness between the divided regions.

Meanwhile, a case of the thin film transistor substrate for a liquid crystal display according to the exemplary embodiment of the present invention will be described with reference to FIGS. 4A and 4B.

4A illustrates a case where the first data line is biased to the pixel electrode, and FIG. 4B illustrates a case where the second data line is biased to the pixel electrode.

As shown in FIGS. 4A and 4B, the pixel area is defined by the intersection of the gate line 21 and the first and second data lines 611 and 612, and the pixel electrode 80 is formed in each pixel area. The first data line 611 is positioned to the left of the pixel electrode 80, and the second data line 612 is positioned to the right of the pixel electrode 80. The first and second data lines 611 and 612 are connected by data line connectors 613 and 614 formed at upper and lower portions of the pixel area, respectively. The gate line 21, the first and second data lines 611 and 612, and the pixel electrode 80 are connected to the first and second thin film transistors TFT1 and TFT2. In such a structure, a gate signal is applied from the gate line 21, a data signal is applied from the first and second data lines 611 and 612, and a pixel voltage is applied to the pixel electrode 80 by the operation of the thin film transistor. In this case, the first and second data lines 611 and 612 are connected to one data pad to receive the same data signal.

Therefore, when the pixel electrode 80 is formed close to the second data line 612 as shown in FIG. 4A, or when the pixel electrode 80 is formed close to the first data line 611 as shown in FIG. 4B. The change in pixel voltage is the same since it varies with the same polarity with respect to. This will be described in more detail.

First, in the divided region in which the pixel electrode 80 is formed closer to the second data line 611, as shown in FIG. 4A, the distance between the pixel electrode 80 and the second data line 612 is first. because closer than the distance between the data line 611, parasitic capacitance C is larger than _R3 C _L3. Here, after the pixel voltage of the A pixel region is positively charged with respect to the common voltage which is the reference voltage, the first and second data lines 611 and 612 are changed from positive to negative to charge the next row. the pixel voltage is the sum of the voltage variation as V _L3 of the voltage V _R3 and the parasitic capacitance C _L3 by the parasitic capacitance C _R3. At this time, since voltages of the same polarity are applied to the first and second data lines 611 and 612, V _R3 and V _L3 are negative and | V _R3 | > | V _L3 | and V _R3 + V _L3 are negative.

Meanwhile, as shown in FIG. 4B, in the case of the divided region in which the pixel electrode 80 is formed closer to the first data line 611, the distance between the pixel electrode 80 and the first data line 611 is zero. The parasitic capacitance is greater in C _L4 than in C _R4 because it is closer than the distance to the two data lines 612. Here, as shown in FIG. 4A, after the pixel voltage of the A pixel region is positively charged with respect to the common voltage which is the reference voltage, the first and second data lines 611 and 612 are positively charged to charge the next row. since variation in the voltage of the negative pixel a is the pixel area is varied as the sum of the voltage V _L4 by the voltage V _R4 and parasitic capacitance C _L4 due to the parasitic capacitance C _R4. At this time, since voltages of the same polarity are applied to the first and second data lines 611 and 612, V _R4 and V _L4 are negative and | V _R4 | <| V _L4 | and V _R2 + V _L2 are negative.

That is, regardless of whether the data line is biased to the left or to the right with respect to the pixel electrode, the voltage fluctuations of the pixel electrode at the time when the charging time passes from the holding time to the holding time all occur in the same negative direction. This is because the effects of the two data lines are compensated for each other by being divided into both sides of the pixel electrode.

In addition, the data line connectors 613 and 614 may also be used in the case where the pixel electrode 80 is formed to be close to the data line connector 613 in the upper portion of the pixel region or close to the data line connector 614 in the lower pixel region. It is connected to the first and second data lines 611 and 612 and fluctuates in the same polarity so that the change in pixel voltage is the same.

On the other hand, the parasitic capacitance caused by the gate electrode and the drain electrode is different between the two divided regions in the divided region in which the misalignment occurs to the left and the divided region in the right, so that the kickback voltage is changed and thus the pixel voltage is changed. In the present invention, there is no such problem. That is, the parasitic capacitance C _P1 and the second gate electrode 222 formed by the first gate electrode 221 and the first drain electrode 631 are divided into the divided region in which the misalignment occurs to the left and the divided region generated to the right. The sum of the parasitic capacitance C _P2 by the second drain electrode 632 (C _P1 + C _P2 ) is determined because C _P1 and C _P2 are compensated for each other. That is, when C is increased _P1 C _P2 is decreased, when the other hand is reduced C _P1 C _P2 does not largely change because the increase in C + C _{P1 P2.}

Next, the structure of the liquid crystal display according to the second embodiment of the present invention will be described in detail.

5 is a layout view illustrating a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view taken along the line VI-VI 'in FIG. 5.

First, the structure of the "lower substrate" of the liquid crystal display device according to the second embodiment of the present invention will be described.

As shown in FIGS. 5 and 6, the thin film transistor substrate, which is a “bottom substrate”, includes aluminum (Al) or aluminum alloy, molybdenum (Mo), or molybdenum-tungsten alloy (MoW alloy) on the insulating substrate 10. Gate wirings 21, 221, and 222 made of metal or a conductor such as chromium (Cr) and tantalum (Ta) and the storage capacitor line 25 are formed. The gate line includes a gate line 21 extending in the horizontal direction and first and second gate electrodes 221 and 222 which are formed at a predetermined distance while being part of the gate line 21. The storage capacitor line 25 is formed in parallel with the gate line 21 between the gate lines 21, and receives a voltage such as a common electrode voltage input to the common electrode of the upper panel from the outside to be described later. Or overlapping with the conductor pattern 633 for the storage capacitor to form a storage capacitor that improves the charge storage capability of the pixel.

The gate wirings 21, 221, 222 and the storage capacitor line 25 may be formed in a single layer, but may be formed in a double layer or a triple layer. In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance, and the other layer is formed of a material having good contact properties with other materials. For example, a double layer of Cr / Al (or an Al alloy) or Al ( Or a bilayer of Al alloy) / Mo.

The gate wirings 21, 221, and 222 and the storage capacitor line 25 are covered with the gate insulating film 30 made of silicon nitride (SiN _X ).

A first semiconductor layer 411 made of a semiconductor such as amorphous silicon is formed on the gate insulating layer 30 on the first gate electrode 221, and an n type like phosphorous (P) is formed on the first semiconductor layer 411. Resistive contact layers 521 and 531 made of a semiconductor such as amorphous silicon doped with impurities are formed on both sides of the first gate electrode 221. The second semiconductor layer 412 is also formed on the gate insulating layer 30 on the second gate electrode 222, and the ohmic contacts 522 and 532 are formed on the second semiconductor layer 412. It is formed separately from both sides about 222.

On the ohmic contacts 521, 531, 522, and 532 and the gate insulating layer 30, data wires 611, 612, 613, which are made of a metal or a conductor such as aluminum or an aluminum alloy, molybdenum or molybdenum-tungsten alloy, chromium, tantalum, or the like. 621, 622, 631, 632, 633, and 634 are formed. The data line extends in the vertical direction at a predetermined distance, and intersects the gate line 21 to define the pixel area, and the first and second data lines 611 and 612 and the first and second data lines 611 and 612. ) Is connected to the data line connector 613 formed adjacent to the gate line 21, the first source electrode 621, which is part of the first data line 611, and the first gate electrode 221. The second source electrode 622 centering around the first drain electrode 631 facing the first source electrode 621, the second source electrode 622 that is part of the second data line 612, and the second gate electrode 222. ) And a second drain electrode 632 facing each other, a conductor pattern 633 for a storage capacitor, and a conductor pattern connection part 634. Here, the first drain electrode 631 and the second drain electrode 632 are connected in one pattern, and the conductor pattern 633 for the storage capacitor is connected to the drain electrodes 631 and 632 through the conductor pattern connection part 634. ) And overlaps with the storage capacitor wiring 25.

The data wirings 611, 612, 613, 621, 622, 631, 632, 633, and 634 may be formed in a single layer like the gate wirings 21, 221, and 222, but may be formed in a double layer or a triple layer. . In the case of forming more than two layers, it is preferable that one layer is formed of a material having a low resistance and the other layer is formed of a material having good contact properties with other materials.

Here, the first gate electrode 221, the first semiconductor layer 411, the first source electrode 621, and the first drain electrode 631 form the first thin film transistor, and the second gate electrode 222, the first The second semiconductor layer 412, the second source electrode 622, and the second drain electrode 632 form a second thin film transistor.

A protective film 70 made of silicon nitride is formed on the data wires 611, 612, 613, 621, 622, 631, 632, 633, 634, and the gate insulating film 30. The protective film 70 has a contact hole 720 exposing the conductor pattern 633 for the storage capacitor.

The pixel electrode 80 made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is formed on the passivation layer 70.

The pixel electrode 80 is connected to the conductive capacitor pattern 633 through the contact hole 720 to receive an image signal from the first and second drain electrodes 631 and 631.

In addition, the pixel electrode 80, together with the opening patterns 411, 412, 413, and 414 formed in the common electrode 400 of the “upper substrate” described later, controls the inclination of the liquid crystal to form a plurality of domains. An opening pattern including the fourth to fourth openings 811, 812, 813, and 814 is formed.

The first opening 811 is formed in the upper half of the pixel electrode 80 formed in a rectangular shape and is formed in an oblique direction from the right side to the left side, and the second opening 812 is centered on the central portion of the pixel electrode 80. The first opening 811 is formed to be symmetrical with each other. The third opening 813 is formed in a shape in which the left end of the upper half of the pixel electrode 80 is cut in an oblique direction, and the fourth opening 814 is the second opening around the center of the pixel electrode 80. It is formed so as to be symmetrical with 812.

The opening patterns 811, 812, 813, and 814 formed on the pixel electrode 80 may also be formed as protrusion patterns.

Next, the structure of the "upper substrate" facing the "lower substrate" of the liquid crystal display device according to the second embodiment of the present invention having such a structure will be described.

As shown in FIGS. 5 and 6, the color filter substrate, which is an “top substrate,” has a black matrix 200 formed under a transparent insulating substrate 100 such as glass, and the color filter 300 under the black matrix 200. ) Is formed. An overcoat layer 600 is formed under the color filter 300, and a common electrode 400 made of a transparent conductive material such as ITO or IZO is formed under the overcoat layer 600.

The common electrode 400, together with the above-described opening patterns 811, 812, 813, and 814 of the pixel electrode 80, controls the inclination of the liquid crystal to form a plurality of domains so as to form a plurality of domains. Opening patterns including 412, 413, and 414 are formed.

The first opening portion 411 is formed in the upper half of the common electrode 400 and is formed in an oblique direction from the right side to the left side, and the second opening portion 412 is formed at the center of the common electrode 400. It is connected to the 411 and is formed to have a vertical symmetry with the first opening 411. The third opening 413 is formed in the upper half of the common electrode 400 above the first opening 411 and is formed in an oblique direction from the right side to the left side, and the fourth opening 414 is formed of the common electrode 400. It is formed to be symmetrical with the second opening portion 412 about the center portion.

The opening patterns 411, 412, 413, and 414 formed in the diagonal direction on the common electrode 400 and the opening patterns 811, 812, 813, and 814 formed in the diagonal direction in the pixel electrode 80 are alternately disposed. .

The opening patterns 411, 412, 413, and 414 formed on the common electrode 400 may also be formed as protrusion patterns.

Next, the structure of the liquid crystal display according to the third embodiment of the present invention will be described in detail.

FIG. 7 is a layout view illustrating a liquid crystal display according to a third exemplary embodiment of the present invention.

FIG. 8 is a cross-sectional view taken along line VII-VII ′ in FIG. 7.

As shown in Figs. 7 and 8, the structures of the "lower substrate" and "upper substrate" of the present invention include the conductor pattern 633 for the storage capacitor and the first and second drain electrodes 631, which are formed on the "lower substrate". The shape of the conductor pattern connecting portion 634 connecting the 632 and all structures except for the passivation layer 70 and the pixel electrode 80 formed on the data line are the same as in the second embodiment of the present invention.                     

The conductive pattern connecting portion 634 of the “lower substrate” of the liquid crystal display according to the third exemplary embodiment of the present invention may have a storage capacitor line (across the center at a point where the first and second drain electrodes 631 and 632 are connected). It is connected to the conductor pattern 633 for the storage capacitor formed overlapping with (25).

The passivation layer 70 is formed to be much thicker than the passivation layer 70 of the second embodiment, and the first and second data lines 611 and 612 to which the pixel electrode 80 receives the same data signal. The data wirings 611, 612, 613, 621, 622, 631, 632, 633, and 634 are completely overlapped with each other.

Here, the protective film 70 is preferably formed to a thickness of 3 μm or more.

In addition, the pixel electrodes 80, together with the opening patterns 411, 412, 413, and 414 of the common electrode 400, control the inclination of the liquid crystal to form a plurality of domains, thereby forming first to fourth protrusions 811 and 812. , 813, 814 are formed.

The first protrusion 811 is formed at an upper half of the pixel electrode 80 and is formed in an oblique direction from the right side to the left side, and the second protrusion 812 is formed at the central portion of the pixel electrode 80. It is connected to the and is formed to have a vertical symmetry with the first projection (811). The third protrusion 813 is formed on the upper half of the pixel electrode 80 in an oblique direction from the upper portion of the first protrusion 811, and the fourth protrusion 814 is formed around the center of the pixel electrode 80. It is formed so as to be symmetrical with the projection 812.

 The projection patterns 811, 812, 813, and 814 formed in the diagonal direction on the pixel electrode 80 are alternately disposed alternately with the opening patterns 411, 412, 413, and 414 formed in the diagonal direction in the common electrode 400. It is.

The protrusion patterns 811, 812, 813, and 814 formed on the pixel electrode 80 may also be formed in an opening pattern.

Although not shown in the first to third embodiments of the present invention, a gate pad connected to the gate line 21 and receiving a gate signal from the outside, and formed on the gate pad and having the same conductivity as the pixel electrode 80 may be used. It may further include an auxiliary gate pad made of a material.

In addition, a data pad formed outside the display area where the first and second data lines 611 and 612 are joined to apply the same signal to the first and second data lines 611 and 612. It may further include an auxiliary data pad formed on the upper portion and made of a conductive material such as the pixel electrode 80.

In addition, the protective layer 70 further includes respective contact holes that expose the gate pad and the data pad, respectively, so that the gate pad and the data pad are electrically connected to the auxiliary gate pad and the auxiliary data pad.

As described above, the aperture ratio can be increased by completely overlapping the pixel electrodes on the double data lines 611 and 612, which will be described in detail with reference to FIGS. 9 to 10. 9 to 10 show only components necessary for convenience of description.

First, with reference to FIG. 9, a structure that causes a decrease in aperture ratio in the liquid crystal display according to the related art will be described.                     

9 is a schematic cross-sectional view of a liquid crystal display according to the related art.

As shown in FIG. 9, the liquid crystal display according to the related art has a structure in which one data line passes between pixels, and a pixel electrode is not overlapped on the data line to prevent signal interference between the pixel electrode and the data line. . In order to block uncontrolled light in the vicinity of the data line, a black matrix is formed on the “upper substrate”, and the black matrix is formed on the upper part of the pixel electrode in consideration of the viewing angle. Therefore, the opening ratio decreases with the increase of the black matrix.

In addition, malfunction of the liquid crystal may occur at the edge of the pixel electrode due to the electric field generated by the data line.

10 is a schematic cross-sectional view of a liquid crystal display according to a third exemplary embodiment of the present invention.

As shown in FIG. 10, the pixel electrode is completely overlapped on the double data line, and a thick protective film is formed between the data line and the pixel electrode to prevent signal interference that may occur due to the overlap of the pixel electrode on the data line. It is.

In this way, since the data line is completely superimposed on the pixel electrode, the parasitic capacitance difference described above does not occur between the data line and the pixel electrode even when misalignment occurs during the photolithography process using the divided exposure method. In addition, since the data lines divided on both sides serve to block light leakage generated by signal interference between neighboring pixel electrodes, the black matrix of the upper substrate can be narrowly formed.

Next, a method of manufacturing the "lower substrate" of the liquid crystal display according to the third exemplary embodiment of the present invention will be described with reference to FIGS. 11A to 14B and FIGS. 7 and 8.

First, as shown in FIGS. 11A and 11B, a gate wiring conductor or a metal is deposited on the insulating substrate 10 to a thickness of 1,000 Å to 3,000 으로 by sputtering, and patterned by a photolithography process using a mask. Thus, the gate line 21 and the gate line including the first and second gate electrodes 221 and 222 and the storage capacitor line 25 are formed.

Next, as shown in FIGS. 12A and 12B, the gate insulating layer 30, the amorphous silicon layer, and the amorphous silicon layer doped with the n-type impurity are respectively 1,500 kPa to 5,000 using chemical vapor deposition (CVD). 증착, 500 Å to 1,500 Å and 300 Å to 600 Å in order to be deposited, and the upper two layers are patterned by a photolithography process using a mask to form semiconductor layers 41 and 42 and resistive contact layers 51 and 52. .

Next, as shown in FIGS. 13A and 13B, the data wiring conductor or the metal is deposited to a thickness of 1,500 kV to 3,000 kV by a method such as sputtering, and patterned by a photolithography process using a mask to form the first and second data lines. 611, 612, data line connecting portion 613, first and second source electrodes 621, 622, first and second drain electrodes 631, 632, conductive pattern 633 for a storage capacitor, and conduction A data line including the sieve pattern connecting portion 634 is formed. Next, the ohmic contact layer 51 not covered by the first source electrode 621 and the first drain electrode 631 is removed to be separated into two parts 521 and 531, and the second source electrode 622 and the second source electrode 622 are removed. The ohmic contact layer 52 not covered by the drain electrode 632 is removed and separated into two parts 522 and 532.

Next, as shown in FIGS. 14A and 14B, silicon nitride is deposited using a chemical vapor deposition method, or spin coating an organic insulating material to form a protective film 70 having a thickness of 30,000 GPa or more and patterned by a photolithography process using a mask. To form a contact hole 720.

Next, as shown in FIGS. 7 and 8, a transparent conductive material such as ITO or IZO is deposited on the passivation layer 70 to a thickness of 400 μs to 500 μs by a sputtering method, and patterned by a photolithography process using a mask. The pixel electrode 80 is formed.

In this case, the projection patterns 811, 812, 813, and 814 are simultaneously formed using a mask having a partially different transmittance in a photolithography process for forming the pixel electrode 80. The principle is as follows.

In order to control the light transmission, a slit or lattice pattern or a mask with a translucent film is used. In this case, the line width of the pattern located between the slits or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure, and in the case of using a translucent film, the transmittance is different in order to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

In the thin film transistor substrate of the liquid crystal display according to the third exemplary embodiment of the present invention, although the protrusion pattern is formed on the pixel electrode 80, the protrusion pattern may also be formed as an aperture pattern. In this case, the pattern is formed by a photolithography process using a mask.

Meanwhile, in the exemplary embodiments of the present invention, the thin film transistor substrate is manufactured using five photolithography etching processes, but may be manufactured using four photolithography etching processes, which are described with reference to FIGS. 15 to 21b. It demonstrates by an Example.

First, as shown in FIGS. 11A and 11B, a gate wiring conductor or a metal is deposited on the insulating substrate 10, and patterned by a first photolithography process in the same manner as in the previous embodiment to form the gate line 21 and the first. And a gate wiring including the second gate electrodes 221 and 222 and the storage capacitor line 25.

Next, as shown in FIG. 15, the gate insulating layer 30, the amorphous silicon layer 40, the doped amorphous silicon layer 50, and the data wiring conductor layer 60 are sequentially deposited.

Next, after the photoresist film 110 is applied to a thickness of 1 μm to 2 μm, light is irradiated to the photoresist film through a mask 100 having a different transmittance depending on the position, and then developed by a second photographic process to form the photoresist patterns 112 and 114. To form. In this case, among the photoresist patterns 112 and 114, the channel portions C of the first and second thin film transistors, that is, between the first source electrode 621 and the first drain electrode 631 and the second source electrode 622 The first portion 114 positioned between the second drain electrodes 632 may be a data wiring portion A, that is, a portion where the data wirings 611, 612, 613, 621, 622, 631, 632, 633, and 634 are formed. The thickness is thinner than the second part 112 positioned at, and the photosensitive film of the other part B is removed.                     

As such, there may be various methods of varying the thickness of the photoresist layer according to the position. In order to control the light transmittance in the C region, a slit or lattice-shaped pattern is mainly formed or a semi-transmissive layer is used.

In this case, the line width of the pattern located between the slits, or the interval between the patterns, that is, the width of the slits, is preferably smaller than the resolution of the exposure machine used for exposure. In the case of using a semi-transmissive film, other transmittances are used to control the transmittance when fabricating a mask. A thin film having a thickness or a thin film may be used.

Here, the first portion 114 of the photoresist layer is exposed to light using a photoresist layer made of a reflowable material, and is exposed using a conventional mask that is divided into a portion that can completely transmit light and a portion that can not completely transmit light. And a portion of the photoresist film flows down to a portion where the photoresist film does not remain.

Next, etching is performed on the photoresist pattern 114 and the underlying layers, that is, the conductor layer 60, the doped amorphous silicon layer 50, and the amorphous silicon layer 40. At this time, the data line and the lower layer of the data line remain in the data wiring portion A, only the amorphous silicon layer should remain in the channel portion C, and the three layers 60, 50, 40 in the remaining portion B. All of these should be removed to expose the gate insulating film 30.

First, as shown in FIG. 16, the exposed conductor layer 60 of the other portion B is removed to expose the underlying doped amorphous silicon layer 50. In this process, the photoresist patterns 112 and 114 are preferably performed under conditions that are hardly etched.                     

Next, as shown in FIG. 17, the doped amorphous silicon layer 50 of the other portion B and the amorphous silicon layer 40 thereunder are simultaneously removed by the dry etching method together with the first portion 114 of the photosensitive film. . The etching may be performed under the condition that the photoresist patterns 112 and 114, the doped amorphous silicon layer 50, and the amorphous silicon layer 40 are simultaneously etched and the gate insulating layer 30 is not etched.

This removes the first portion 114 of the channel portion C to reveal the conductor layer 60, and removes the doped amorphous silicon layer 50 and the amorphous silicon layer 40 of the other portion B. The lower gate insulating film 30 is exposed. On the other hand, since the second portion 112 of the data wiring portion A is also etched, the thickness becomes thin.

Next, the photoresist residue remaining on the surface of the conductor layer 60 of the channel portion C is removed through ashing.

Next, as shown in FIG. 18, the conductor layer 60 of the channel portion C and the doped amorphous silicon layer 50 under the etching are removed by etching.

Finally, when the photoresist second portion 112 remaining in the data wiring portion A is removed, the first source electrode 621 and the first drain electrode 631 are separated as shown in FIGS. 19A and 19B. The second source electrode 622 and the second drain electrode 632 are separated, and the data wires 611, 612, 613, 621, 622, 631, 632, 633, and 634 and the ohmic contact layers 511 and 521 thereunder. , 531, 532, 522, 512, 513 and the semiconductor layer 413 are completed.

In this way, after forming the data wirings 611, 612, 613, 621, 622, 631, 632, 633, and 634, silicon nitride is deposited in the same manner as in the previous embodiment as shown in Figs. 20A and 20B. As a result, a protective film 70 having a thickness of 3 μm or more is formed and patterned by a third photolithography process to form a contact hole 720.

Finally, as shown in FIGS. 21A and 21B, a transparent conductive material such as ITO or IZO is deposited in the same manner as in the previous embodiment and patterned by a fourth photolithography process to form the pixel electrode 80.

In another embodiment of the thin film transistor substrate according to the present invention, the data wirings 611, 612, 613, 621, 622, 631, 632, 633, and 634, and the ohmic contact layer thereunder, are used as well as the effects of the foregoing embodiments. The 511, 521, 531, 532, 522, 512, and 513 and the semiconductor layer 413 may be formed in one photo process to simplify the manufacturing process.

As described above, in the present invention, one data line is formed on each side of the pixel region so that the variation of pixel voltage due to parasitic capacitance is equal between the divided regions having different degrees of misalignment, and two thin film transistors are formed on each pixel region. The parasitic capacitances of the gate electrode and the drain electrode are equalized between the two divided regions where the misalignment occurs, so that variations in the pixel voltage can be made the same, thereby preventing uneven brightness. In addition, the protective film can be formed thick, and the pixel electrode can be formed so as to overlap the upper portion of the data line, thereby increasing the aperture ratio.

Claims (29)

First insulating substrate, A gate line formed on the first insulating substrate and a gate line connected to the gate line and including first and second gate electrodes positioned at a predetermined distance from each other; First and second data lines and pixel regions defining a pixel area crossing the gate line and positioned at a predetermined distance, and first and second source electrodes that are part of the first and second data lines, respectively, and the first and second source electrodes. A data line including first and second drain electrodes facing each other and insulated from and intersecting the gate line; A pixel electrode formed in each pixel area in a matrix form defined by crossing the gate line and the data line, electrically connected to the first and second drain electrodes, and at least partially overlapping the data line; First domain dividing means formed on the first insulating substrate, A second insulating substrate facing the first insulating substrate, A color filter formed on the second insulating substrate, A common electrode formed on the color filter, and Second domain dividing means formed on the second insulating substrate Including, The same signal is applied to the first and second data lines. delete In claim 1, And a thickness of the passivation layer formed between the data line and the pixel electrode is 3 µm or more. In claim 1, And the first and second domain dividing means is a projection pattern. In claim 1, And the first and second domain dividing means are opening patterns. In claim 1, The liquid crystal display device of any one of the first and second domain dividing means is a projection pattern, and the other domain dividing means is an opening pattern. A gate line including a gate line formed on an insulating substrate and first and second gate electrodes connected to the gate line and positioned at a predetermined distance, A gate insulating film covering the gate wiring, First and second semiconductor layers formed on the first and second gate electrodes, respectively, First and second data lines and pixel regions defining a pixel area crossing the gate line and positioned at a predetermined distance, and first and second source electrodes that are part of the first and second data lines, respectively, and the first and second source electrodes. A data line comprising first and second drain electrodes facing each other, A protective film having at least one first contact hole for electrically connecting the first and second drain electrodes to the pixel electrode; and A pixel electrode electrically connected to the first and second drain electrodes and overlapping the data line Including; The thin film transistor substrate of which the same signal is applied to the first and second data lines. In claim 7, The thin film transistor substrate of which the first and second drain electrodes are connected as one. In claim 7, The data line may be formed on the upper and lower portions of the pixel area, and further includes a data line connection part connecting the first and second data lines. In claim 7, A thin film transistor substrate further comprising a storage capacitor line formed in parallel with the gate line. In claim 10, The thin film transistor substrate further comprising a conductive capacitor pattern formed to overlap the storage capacitor line. In claim 11, And a conductor pattern connection unit connecting the drain electrode of the data line to the storage capacitor conductor pattern. In claim 11, And the first contact hole formed in the passivation layer is formed on the conductive capacitor conductor pattern. In claim 7, The thin film transistor substrate having the same planar shape as the first and second semiconductor layers except for the first source electrode and the first drain electrode and between the second source electrode and the second drain electrode. In claim 7, And a resistive contact layer formed between the first and second semiconductor layers and the data line. The method of claim 15, And the ohmic contact layer and the data line have the same planar shape. In claim 7, The gate line further includes a gate pad for applying a signal to the gate line, and the data line further includes a data pad for applying a signal to the data line. Second and third contact holes are formed in the passivation layer to expose the gate pad and the data pad, respectively. The thin film transistor substrate further comprising an auxiliary gate pad and an auxiliary data pad formed of the same layer as the pixel electrode and connected to the gate pad and the data pad through the second and third contact holes, respectively. delete In claim 7, The protective film formed between the data line and the pixel electrode has a thickness of 3 μm or more. Forming a gate line on the insulating substrate, the gate line including first and second gate electrodes connected to the gate line and positioned at a predetermined distance, Forming a gate insulating film on the gate wiring; Forming first and second semiconductor layers on the gate insulating layer, First and second data lines and pixel regions defining a pixel area crossing the gate line and positioned at a predetermined distance, and first and second source electrodes that are part of the first and second data lines, respectively, and the first and second source electrodes. Forming a data line including first and second drain electrodes facing each other; Forming a passivation film having at least one first contact hole for electrically connecting the first and second drain electrodes to the pixel electrode, and Forming a pixel electrode connected to the first and second drain electrodes and overlapping the data line Method of manufacturing a thin film transistor substrate comprising a. The method of claim 20, And forming a data line connection part connecting the first and second data lines to the data line. The method of claim 20, And forming a storage capacitor line in parallel with the gate line in the forming of the gate line. The method of claim 22, And forming a storage capacitor conductor pattern overlapping with the storage capacitor line in the step of forming the data wiring. The method of claim 23, And forming a conductor pattern connection part connecting the drain electrode and the storage capacitor conductor pattern to form the data line. The method of claim 23, The first contact hole of the passivation layer is formed on the conductive capacitor pattern. The method of claim 20, And the semiconductor layer and the data line are formed together by a photolithography process using a photoresist pattern having a different thickness depending on position. The method of claim 20, Forming a gate pad for applying a signal to the gate line in the gate wiring forming step, and forming a data pad for applying a signal to the data line in the data wiring forming step, Forming second and third contact holes that expose the gate pad and the data pad, respectively, in the forming of the passivation layer; And forming an auxiliary gate pad and an auxiliary data pad in the same layer as the pixel electrode and connected to the gate pad and the data pad, respectively, through the second and third contact holes. The method of claim 20, And the first contact hole has a contact hole exposing the first drain electrode and a contact hole exposing the second drain electrode, respectively. delete

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