KR100752162B1 - Method for fabricating of COMS image sensor - Google Patents

Abstract

The present invention controls the etching amount of the protective film so that the metal pad is not turned off, and then removes only a predetermined thickness from the surface of the protective film, and then protects the metal pad from the subsequent process to reduce the contact resistance and further improve the yield. (CMOS) image sensor manufacturing method comprising the steps of: forming a metal pad in a pad region on a substrate divided into an active region and a pad region; Forming an insulating film on an entire surface of the substrate including the metal pads; Selectively removing the insulating film on the metal pad by a predetermined thickness from a surface to form a preliminary pad opening, and forming a first planarization layer on an active region of the substrate; Forming a color filter layer over said first planarization layer; Forming a second planarization layer on the active region of the substrate including the color filter layer; Forming a microlens on the second planarization layer to correspond to the color filter layer; And removing the insulating film remaining in the pad area to form a pad open part.

CMOS image sensor, metal pad, micro lens, probing test

Description

Method for fabricating CMOS image sensor {Method for fabricating of COMS image sensor}

1 is an equivalent circuit diagram of one pixel of a general CMOS image sensor

2 is a layout view of one pixel of a general CMOS image sensor

3A to 3F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to the prior art.

4A through 4E are cross-sectional views of signal lines and subsequent processes of the CMOS image sensor according to the first embodiment of the present invention;

<Description of Main Parts of Drawing>

200 semiconductor substrate 201 insulating film

202: metal pad 203: protective film

204: photosensitive film 205: pad opening portion

206 and 210: first and second planarization layers 207, 208 and 209 color filter layers

211: microlens

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a CMOS image sensor, and more particularly, to a method for manufacturing a CMOS image sensor, in which metal pad particles generated during pad probing are reduced to improve light reception characteristics. It is about.

In general, an image sensor is a semiconductor device that converts an optical image into an electrical signal, and is generally a charge coupled device (CCD) and CMOS metal (Complementary Metal Oxide Silicon) image. It is divided into Image Sensor.

In the charge coupled device (CCD), a plurality of photo diodes (PDs) for converting a signal of light into an electrical signal are arranged in a matrix form, and the photo diodes in each vertical direction arranged in the matrix form. A plurality of vertical charge coupled device (VCCD) formed between the plurality of vertical charge coupled devices (VCCD) for vertically transferring charges generated in each photodiode, and horizontally transferring charges transferred by the respective vertical charge transfer regions; A horizontal charge coupled device (HCCD) for transmitting to the sensor and a sense amplifier (Sense Amplifier) for outputting an electrical signal by sensing the charge transmitted in the horizontal direction.

However, such a CCD has a disadvantage in that the manufacturing method is complicated because the driving method is complicated, the power consumption is large, and the multi-step photo process is required. In addition, the charge coupling device has a disadvantage in that it is difficult to integrate a control circuit, a signal processing circuit, an analog / digital converter (A / D converter), and the like into a charge coupling device chip, which makes it difficult to miniaturize a product.

Recently, CMOS image sensors have attracted attention as next generation image sensors for overcoming the disadvantages of the charge coupled device. The CMOS image sensor uses CMOS technology that uses a control circuit, a signal processing circuit, and the like as peripheral circuits to form MOS transistors corresponding to the number of unit pixels on a semiconductor substrate, thereby forming the MOS transistors of each unit pixel. The device adopts a switching method that sequentially detects output. That is, the CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel by a switching method by forming a photodiode and a MOS transistor in the unit pixel.

The CMOS image sensor has advantages, such as a low power consumption, a simple manufacturing process according to a few photoprocess steps, by using CMOS manufacturing technology. In addition, since the CMOS image sensor can integrate a control circuit, a signal processing circuit, an analog / digital conversion circuit, and the like into the CMOS image sensor chip, the CMOS image sensor has an advantage of easy miniaturization. Therefore, the CMOS image sensor is currently widely used in various application parts such as a digital still camera, a digital video camera, and the like.

On the other hand, CMOS image sensors are classified into 3T type, 4T type, and 5T type according to the number of transistors. The 3T type consists of one photodiode and three transistors, and the 4T type consists of one photodiode and four transistors. An equivalent circuit and layout of the unit pixels of the 3T-type CMOS image sensor will be described as follows.

FIG. 1 is an equivalent circuit diagram of a general 3T CMOS image sensor, and FIG. 2 is a layout diagram illustrating unit pixels of a general 3T CMOS image sensor.

As shown in FIG. 1, a unit pixel of a general 3T CMOS image sensor includes one photodiode (PD) and three nMOS transistors T1, T2, and T3. The cathode of the photodiode PD is connected to the drain of the first nMOS transistor T1 and the gate of the second nMOS transistor T2.

The sources of the first and second nMOS transistors T1 and T2 are all connected to a power supply line supplied with a reference voltage VR, and the gate of the first nMOS transistor T1 has a reset signal RST. It is connected to the reset line supplied. Further, the source of the third nMOS transistor T3 is connected to the drain of the second nMOS transistor, the drain of the third nMOS transistor T3 is connected to a read circuit (not shown in the drawing) via a signal line, The gate of the third nMOS transistor T3 is connected to a column select line to which a selection signal SLCT is supplied.

Accordingly, the first nMOS transistor T1 is referred to as a reset transistor Rx, the second nMOS transistor T2 is referred to as a drive transistor Dx, and the third nMOS transistor T3 is referred to as a selection transistor Sx.

As shown in FIG. 2, in the unit pixel of a general 3T CMOS image sensor, an active region 10 is defined so that one photodiode 20 is formed in a wide portion of the active region 10. Gate electrodes 120, 130, and 140 of three transistors that overlap each other in the active region 10 of the remaining portion are formed.

That is, the reset transistor Rx is formed by the gate electrode 120, the drive transistor Dx is formed by the gate electrode 130, and the selection transistor Sx is formed by the gate electrode 140. Is formed.

Here, impurity ions are implanted into the active region 10 of each transistor except for lower portions of the gate electrodes 120, 130, and 140 to form source / drain regions of each transistor.

Therefore, a power supply voltage Vdd is applied to a source / drain region between the reset transistor Rx and the drive transistor Dx, and a source / drain region on one side of the select transistor Sx is shown in a read circuit (not shown). Not used).

Although not illustrated in the drawings, the gate electrodes 120, 130, and 140 described above are connected to respective signal lines, and each of the signal lines has a pad at one end thereof and is connected to an external driving circuit.

As described above, each signal line including the pad and the processes proceeding thereafter are described below.

3A to 3F are cross-sectional views illustrating a method of manufacturing a CMOS image sensor according to an exemplary embodiment of the present invention.

First, as shown in FIG. 3A, an insulating film 101 such as a gate insulating film or an interlayer insulating film is formed on the semiconductor substrate 100, and metal pads 102 of respective signal lines are formed on the insulating film 101. In this case, the metal pad 102 may be formed on the same layer as the same material as each of the gate electrodes 120, 130, and 140 as described with reference to FIG. 2, and may be formed of a different material through separate contacts. It can be, and mostly formed of aluminum (Al). A protective film 103 is formed on the entire surface of the insulating film 101 including the metal pad 102. The protective film is formed of an oxide film or a nitride film.

As shown in FIG. 3B, a photosensitive film 104 is formed on the passivation film 103, and exposed and developed using photolithography to expose an upper portion of the metal pad 102. In addition, after the protective film 103 is selectively etched using the photosensitive film 104 as a mask to form the metal pad opening 105 on the metal pad 102, the photosensitive film 104 is removed.

As shown in FIG. 3C, the barrier layer 113 is formed on the entire surface of the substrate on which the metal pad opening 105 is formed.

Here, the barrier layer 113 is formed of a PE (plasma emhancement) oxide film, PE TEOS or PE nitride film, the thickness is about 200 ~ 600 로.

As shown in FIG. 3D, the first planarization layer 106 is deposited on the barrier layer 113, and the photo planar etching process using a mask is used to leave only portions except the metal pad portion.

A blue color filter layer 107, a green color filter layer 108, and a red color filter layer 109 are sequentially formed on the first planarization layer 106 corresponding to each photodiode region (not shown in the figure).

Here, in each of the color filter layer forming methods, the color photosensitive material is coated and the color filter layers are formed by a photolithography process using a separate mask.

As shown in FIG. 3E, the second planarization layer 111 is formed on the entire surface of the substrate including the color filter layers 107, 108, and 109, and the photo-etching process using a mask remains only in the region excluding the metal pad portion. do.

As shown in FIG. 3F, a dielectric material is deposited on the second planarization layer 111, and the dielectric material is selectively removed by a photolithography process to correspond to each color filter layer 107, 108, and 109. The lens 112 is formed.

At this time, the barrier layer 113 of the upper portion of the metal pad 102 is simultaneously removed by blanket etching or the like to expose the metal pad opening 105 without adding a separate mask.

However, in the conventional method of manufacturing a CMOS image sensor as described above has the following problems.

That is, in order to prevent the contamination of the metal pads as the development process is repeated in forming the color filter layer, the process cost and time are increased by adding the barrier layer and the metal pad open process.

The present invention is to solve the above problems, by adjusting the etching amount of the protective film so that the metal pad is not turned off to remove only a predetermined thickness from the surface of the protective film, and then to reduce the contact resistance by protecting the metal pad from the post-process It is an object of the present invention to provide a method for manufacturing a CMOS image sensor capable of improving yield.

Method of manufacturing a CMOS image sensor according to the present invention for achieving the above object comprises the steps of forming a metal pad in a pad region on the substrate divided into an active region and a pad region; Forming an insulating film on an entire surface of the substrate including the metal pads; Selectively removing the insulating layer on the metal pad by a predetermined thickness from a surface to form a preliminary pad opening; Forming a first planarization layer on the active region of the substrate; Forming a color filter layer over said first planarization layer; Forming a second planarization layer on the active region of the substrate including the color filter layer; Forming a microlens on the second planarization layer to correspond to the color filter layer; And removing the insulating film remaining in the pad area to form a pad open part.

Referring to the accompanying drawings, a method of manufacturing a CMOS image sensor according to the present invention having the features as described above in more detail as follows.

4A to 4E are cross-sectional views of a CMOS image sensor according to a first embodiment of the present invention.

First, as shown in FIG. 4A, an insulating film 201 such as a gate insulating film or an interlayer insulating film is formed on the semiconductor substrate 200, and metal pads 202 of each signal line are formed on the insulating film 201.

In this case, the metal pad 202 may be formed on the same layer as the same material as each of the gate electrodes 120, 130, and 140 described with reference to FIG. 2, and may be formed of a different material through a separate contact. It can be, and mostly formed of aluminum (Al).

A protective film 203 is formed on the entire surface of the insulating film 201 including the metal pad 202.

The protective film 203 is formed of USG, oxide film or nitride film.

As shown in FIG. 4B, a photosensitive film 204 is formed on the passivation film 203, and is exposed and developed to selectively pattern the upper portion of the metal pad 202.

Subsequently, the passivation layer 203 is selectively etched only a predetermined thickness from the surface by using the patterned photoresist 204 as a mask to form a preliminary pad opening 205a in the metal pad 202.

Here, the thickness of the protective film 203 remaining on the metal pad 202 is about 400 kPa.

As shown in FIG. 4C, the photoresist layer 204 is removed, the first planarization layer 206 is deposited on the entire surface of the semiconductor substrate 200, and the metal pad portion is formed using a photolithography process using a mask. Only remain in areas except for.

A blue color filter layer 207, a green color filter layer 208, and a red color filter layer 209 are sequentially formed on the first planarization layer 206 corresponding to each photodiode region (not shown in the figure).

Here, in each of the color filter layer forming methods, the color photosensitive material is coated and the color filter layers are formed by a photolithography process using a separate mask.

As shown in FIG. 4D, the second planarization layer 210 is formed on the entire surface of the substrate including the color filter layers 207, 208, and 209, and the photo-etching process using a mask remains only in the region except the metal pad portion. do.

As shown in FIG. 4E, a microlens material layer is deposited on the second planarization layer 210, and the material layer is selectively removed by a photolithography process to form a microlens pattern.

Here, an oxide film such as resist or TEOS may be used as the material layer for the microlens.

Subsequently, a semi-spherical microlens 211 is formed on each of the color filter layers 207, 208, and 209 by performing a reflow process on the semiconductor substrate 201 having the microlens pattern formed at a predetermined temperature (150 to 200 ° C.). do.

In this case, the reflow process may use a hot plate or a furnace. At this time, the curvature of the microlens 36 varies according to the method of shrinkage heating, and the focusing efficiency also varies according to the curvature.

Subsequently, ultraviolet rays are irradiated to the microlenses 211 to be cured. In this case, the microlens 211 may maintain an optimum radius of curvature by irradiating and curing the microlens 211 with ultraviolet rays.

The pad opening 205 is formed by selectively removing the passivation layer 203 remaining on the upper portion of the metal pad 202 by a blanket etch or the like without adding a separate mask.

Meanwhile, in the method of manufacturing the CMOS image sensor according to the first embodiment of the present invention, the pad opening part 205 is formed after the microlens 211 is formed, but the second embodiment of the present invention In the method of manufacturing a CMOS image sensor according to an example, the pad opening part 205 may be formed first, and then the microlens 211 may be formed.

After checking the contact resistance by a probe test of each metal pad 202 of the CMOS image sensor manufactured as described above, if there is no abnormality, the external driving circuit and the metal pad are electrically Connect it.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

As described above, the method of manufacturing the CMOS image sensor according to the present invention has the following effects.

First, the protective film on the upper part of the metal pad is completely removed to form a metal pad open part, and the protective film is selectively removed only from the surface by a predetermined thickness to form a preliminary open part on the upper part of the metal pad. By preventing the pads from corroding, the contact resistance of the metal pads can be reduced.

Second, since the contact resistance of the metal pad is reduced as described above, the photodiode function caused by the metal pad particles is paralyzed since there is no need to perform deep probing to scrape the surface of the metal pad during the probe test. It can prevent.

Claims (4)

Forming a metal pad in a pad region on the substrate divided into an active region and a pad region; Forming an insulating film on an entire surface of the substrate including the metal pads; Selectively removing the insulating layer on the metal pad by a predetermined thickness from a surface to form a preliminary pad opening; Forming a first planarization layer on the active region of the substrate; Forming a color filter layer over said first planarization layer; Forming a second planarization layer on the active region of the substrate including the color filter layer; Forming a microlens on the second planarization layer to correspond to the color filter layer; Forming a pad opening by blanket-etching the insulating film remaining in the pad region, wherein the insulating film remaining in the pad region is formed. delete The method of claim 1, And an insulating film remaining in the preliminary pad opening part is 400 kW thick. The method of claim 1, wherein the insulating film uses a USG film.

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