KR100733417B1 - Saddle type transistor and method for manufacturing the same - Google Patents

Abstract

A saddle type transistor and a manufacturing method thereof are provided to obtain a high satisfaction in a device driving process, to prevent the generation of leakage current, and to improve the yield by preventing the generation of a short channel effect, satisfying a proper channel current and reducing coupling noises. A saddle type transistor includes a plurality of active regions, isolation layers(42) for defining the active regions, a plurality of gate lines and an etch stop layer. The plurality of gate lines cross the active region. A portion of the gate line is overlapped with one end portion of the active region. The other portion of the gate line is overlapped with the isolation layer. The etch stop layer is interposed between the gate line and the isolation layer.

Description

Saddle type transistor and manufacturing method therefor {SADDLE TYPE TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME}

1 is a plan view showing a saddle transistor according to the prior art.

FIG. 2 is a cross-sectional view taken along the cut plane of X-X` of FIG. 1. FIG.

3 is a plan view showing a saddle-type transistor according to an embodiment of the present invention.

4A to 4E are cross-sectional views illustrating a manufacturing process of a saddle-type transistor along a cutting plane taken along the line Y-Y` of FIG.

Explanation of symbols on the main parts of the drawings

41 semiconductor substrate 42 device isolation film

43a: nitride film 45: gate electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method of manufacturing a saddle type transistor in which a fin type and a recessed type are mixed.

In the semiconductor industry, the more chips or dies that can be produced per wafer, the more competitive it can be in cost competition. One of the most direct ways to implement this trend is to reduce the size of the device. In other words, we are working to reduce the line width of the circuit competitively. Reducing the linewidth, however, has caused harms such as Short Channel Effect (SCE), Punch Through Breakdown (PTB), Drain Induced Barrier Lowering (DIBL), and Gate Induced Drain Leakage (GIDL). Or the current trend is to control the ion implantation concentration of impurities in the source / drain junction portion. However, this solution introduces a new problem by bringing low channel current.

In such a situation, the conventional pin transistor has an excellent SCE prevention phenomenon and at the same time secures a high channel current, thereby achieving high integration of the device and prevention of deterioration of characteristics. In particular, the saddle-type transistor using the damascene method has been spotlighted as an easy technique for etching the gate electrode.

1 is a plan view illustrating a saddle transistor according to the prior art.

Referring to FIG. 1, it can be seen that the active region 11 defined by the device isolation layer 12 and the gate electrode 13 intersecting with the active region 11 are formed. Here, the gate electrode 13 is selectively formed in the active region 11 to be formed in the saddle type active region in which the fin transistor and the recess transistor are mixed.

However, in one active region 11, two gate electrodes 13, which may basically serve as transistors, cross each other, and in practice, the active regions 11 adjacent to both edges of the active region 11 cross each other. The gate electrode 13 of) passes. This is called a passing gate (C).

FIG. 2 is a cross-sectional view taken along the cutting plane of X-X ′ of FIG. 1.

Referring to FIG. 2, as described above, the gate electrode 24 is formed in the saddle type active region 22, and the passing gate C is formed at both edges of the active region.

In this structure, the source / drain regions adjacent to the passing gate C are in contact with each other. In general, when the passing gate C and the source / drain regions are in contact with each other, the coupling noise is generated by the interaction, and the transistors have a delicate structure. Control becomes difficult.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a saddle-type transistor that reduces coupling noise caused by passing gates.

According to an aspect of the present invention for achieving the above object, a plurality of active regions, a device isolation film defining the active region, a plurality of gate lines crossing the active region in the uniaxial direction, and among the gate lines A saddle transistor includes a gate line overlapping a portion of one end of the active region and a portion overlapping the device isolation layer and an etch stop layer formed between the device isolation layer.
In addition, according to another aspect of the present invention for achieving the above object, forming an isolation layer in the substrate to define an active region, the step of recessing a portion of the isolation layer, the recess of the isolation layer Forming an etch stop layer on the portion, and forming a plurality of gate lines crossing in the axial direction of the active region, wherein one of the plurality of gate lines partially overlaps one end of the active region, and the other portion The method provides a method of manufacturing a saddle-type transistor, the method including forming an overlap with the etch stop layer.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a plan view illustrating a saddle transistor according to an exemplary embodiment of the present invention.

Referring to FIG. 3, it can be seen that the active region 31 defined by the device isolation layer 32 and the gate electrode 33 crossing the active region 31 are formed. Here, the gate electrode 33 is selectively etched in the active region 31 to be formed in the saddle type active region in which the fin transistor and the recess transistor are mixed. And the passing gate D is also formed.

In addition, as a means for solving the above-described conventional problems, the nitride film 34 may be formed by partially etching the device isolation layer 32 and forming the etch stop layer formed under the passing gate D. FIG.

4A to 4E are cross-sectional views illustrating a manufacturing process of the saddle-type transistor along the cutting line Y-Y` of FIG.

First, as shown in FIG. 4A, a pad layer 43 having a structure in which a pad oxide film and a pad nitride film are sequentially stacked on the semiconductor substrate 41 is formed, and the pad layer 43 is selectively etched to separate devices. Open the area.

Subsequently, the semiconductor substrate 41 is etched using the pad layer 43 as an etch barrier to form the device isolation trench, and a buffer oxide film, a liner nitride film, and an insulation oxide film are sequentially formed in the trench to form the device isolation film 42. ).

In this case, the buffer oxide film may be formed of an oxide film formed by a thermal oxide film or a chemical vapor deposition (CVD) method, and when formed into an oxide film formed by a CVD method, the initial deposition may be performed in a thermal oxidation atmosphere to heal the lattice defect of the substrate. .

Subsequently, a plurality of ion implantation processes may be applied to the substrate on which the upper surface of the active region defined by the device isolation layer 42 is exposed to form wells, channels, and isolation diffusion layers.

Subsequently, a first mask pattern 44 for selectively etching the device isolation layer 42 adjacent to both edges of the active region is formed, and the device isolation layer 42 is recessed as an etching barrier.

Next, as shown in FIG. 4B, after the first mask pattern 44 and the pad layer 43 are removed, the nitride film 45 is formed as an etch stop layer on the entire surface of the substrate on which the recess portion is formed in the device isolation layer 42. Deposit.

The nitride film 45 is formed by LPCVD, PECVD, or ALD.

Next, as shown in FIG. 4C, an etching process using phosphoric acid (H ₃ PO ₄ ) is performed to leave the recess portion of the device isolation layer 42 and the nitride layer 45 over the active region, and The nitride film 45 is removed.

Next, as shown in FIG. 4D, a second mask pattern 46 is formed to form a saddle-shaped active region in the active region of the semiconductor substrate 41, and is etched to form an active region of the semiconductor substrate 41. A recess type active region is formed in the trench, and the device isolation layer 42 under the region where the gate electrode is to be formed is selectively etched to form a fin active region. Finally, a recessed active region and a fin type active region are formed, which are collectively referred to as a saddle-type active region.

In this case, a region through which the passing gate passes is also formed, and the device isolation layer 42 is not etched due to the nitride layer 45. This will be more apparent with reference to the E region.

Next, as shown in FIG. 4E, a gate insulating film, a gate conductive film, and a hard mask are sequentially deposited on the entire surface of the substrate on which the saddle-shaped active region is formed, and then selectively etched to form the gate electrode 47.

As described above, the present invention reduces the coupling noise by reducing the area in which the passing gate is in contact with the source / drain regions of the active region. This will be more apparent when looking at the length of the prior art A of FIG. 2 and the length of B of FIG. 4E which is an embodiment of the present invention.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

As described above, the present invention can reduce the coupling noise in the saddle-type transistor that satisfies the SCE prevention and the channel current amount of the transistor at the same time to satisfy the product satisfaction when driving the circuit of the device.

In addition, the yield improvement effect can be obtained by preventing leakage current, data distortion, and transistor malfunction rate.

Claims (5)

A plurality of active regions; An isolation layer defining the active region; A plurality of gate lines traversing the active region in a uniaxial direction; And An etch stop layer formed between the gate line and a portion of the gate line overlapping one end of the gate line and a portion of the gate line overlapping the device isolation layer Saddle transistor comprising a. The method of claim 1, The etch stop layer is a saddle transistor formed in the recessed portion of the device isolation layer. The method of claim 2, The etch stop layer is a saddle transistor made of a nitride film. Forming an isolation layer in the substrate to define an active region; Recessing a portion of the device isolation film; Forming an etch stop layer on the recess of the device isolation layer; A plurality of gate lines may be formed to cross the axial direction of the active region, wherein one of the plurality of gate lines overlaps one end of the active region, and the other overlaps the etch stop layer. step Saddle transistor manufacturing method comprising a. The method of claim 4, wherein The etch stop film is a nitride film manufacturing method of the saddle transistor.

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