KR100706834B1 - Circuit for controlling substrate bias voltage in semiconductor memory apparatus - Google Patents

Abstract

The present invention provides a substrate bias voltage control circuit of a semiconductor memory device which prevents a phenomenon in which the substrate bias voltage of the semiconductor memory device falls below a set level.

The substrate bias voltage control circuit of the semiconductor memory device of the present invention is a high potential voltage sensing means for outputting a sensing signal according to whether or not the reference level of the high potential voltage VPP is exceeded, and depending on whether the set level of the substrate bias voltage VBB is exceeded. Substrate bias voltage sensing means for outputting a substrate bias voltage enable signal for controlling a substrate bias voltage pumping operation, and setting voltage control means for controlling a set level of the substrate bias voltage VBB in response to an input of the sensing signal; It is characterized by including.

Semiconductor Memory Device, Substrate Bias Voltage, High Potential Voltage

Description

Circuit for Controlling Substrate Bias Voltage in Semiconductor Memory Apparatus

1 is a graph illustrating a substrate bias voltage drop phenomenon in a semiconductor memory device according to the related art;

2 is a block diagram illustrating a configuration of a substrate bias voltage control circuit of a semiconductor memory device according to an embodiment of the present invention;

3 is a detailed configuration diagram of the high potential voltage sensing means shown in FIG.

4 is a detailed configuration diagram of the substrate bias voltage sensing means and the set level control means shown in FIG.

5 is a block diagram showing a configuration of a substrate bias voltage control circuit of a semiconductor memory device according to another embodiment of the present invention;

6 is a detailed configuration diagram of the external power supply detecting means shown in FIG. 4;

7 is a detailed configuration diagram of the substrate bias voltage control circuit shown in FIG. 4;

8 is a graph illustrating a substrate bias voltage control operation of the semiconductor memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10: high potential voltage detection means

20/60: substrate bias voltage sensing means

30/70: setting voltage control means

40: Substrate Bias Voltage Pump

50: external power supply detection means

The present invention relates to a substrate bias voltage control circuit of a semiconductor memory device, and more particularly, to a substrate bias voltage control circuit of a semiconductor memory device which prevents a phenomenon in which the substrate bias voltage of the semiconductor memory device falls below a set level.

In general, a dynamic random access memory (DRAM) receives voltages such as an external supply power supply (VDD) and a ground voltage (VSS) from the outside of the chip to receive internal voltages such as a high potential voltage (VPP) and a substrate bias voltage (VBB). Create and use your own. However, the external power supply VDD supplied at this time does not always maintain a precisely constant level, and the value changes minutely by various factors.

During the refresh operation of the semiconductor memory device, the usage amount of the high potential voltage VPP increases in the chip. When the value of the external supply power supply VDD enters the refresh operation mode when the value of the external supply voltage VDD falls below the set level (hereinafter, referred to as a low VDD region), the value of the high potential voltage VPP falls below the set level. The change in the value of the high potential voltage VPP affects the level of the substrate bias voltage VBB. This is because the well capacitance occurs between the two voltages due to the characteristics of the process of the semiconductor memory device. Therefore, when the high potential voltage VPP falls below the set level, the substrate bias voltage VBB level also falls below the set level.

1 is a graph illustrating a substrate bias voltage drop phenomenon in a semiconductor memory device according to the related art.

The figure shows the change of the high potential voltage VPP and the substrate bias voltage VBB due to the refresh operation in the low VDD region. During the period in which the refresh signal rfsh indicating that the semiconductor memory device has entered the refresh mode is enabled, the high potential voltage VPP drops about 0.5V and the substrate bias voltage VBB drops about 0.3V. You can see that. As described above, when the refresh operation occurs in the low VDD region, a drop phenomenon of the high potential voltage VPP occurs, and thus the substrate bias voltage VBB becomes lower than the set level.

As such, when the substrate bias voltage VBB drop occurs, the threshold voltage of the transistors in the semiconductor memory device is increased, thereby reducing the restore performance of the memory cell during the refresh operation, thereby causing a malfunction of the bit line sensing. Side effects such as

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and when the drop phenomenon of the high potential voltage VPP of a semiconductor memory device occurs, the set level of the substrate bias voltage VBB is increased to drop the substrate bias voltage VBB. There is a technical problem to provide a substrate bias voltage control circuit of a semiconductor memory device that compensates a voltage level due to a phenomenon to prevent a malfunction that may occur due to a change in the threshold voltage of each transistor.

According to another aspect of the present invention, there is provided a substrate bias voltage control circuit of a semiconductor memory device, including: a high potential voltage sensing unit configured to output a sensing signal depending on whether a reference level of the high potential voltage VPP is exceeded; Substrate bias voltage sensing means for outputting a substrate bias voltage enable signal for controlling a substrate bias voltage pumping operation according to whether or not a set level of the substrate bias voltage VBB is exceeded; Setting voltage control means for controlling a setting level of the substrate bias voltage VBB in response to an input of the sensing signal; And a substrate bias voltage pump configured to continuously or stop pumping the substrate bias voltage VBB in response to an input of the substrate bias voltage enable signal.

In addition, the substrate bias voltage control circuit of the semiconductor memory device of the present invention, the external power supply sensing means for outputting a detection signal in accordance with whether or not the reference level of the external power supply (VDD); Substrate bias voltage sensing means for outputting a substrate bias voltage enable signal for controlling a pumping operation of the substrate bias voltage VBB according to whether or not the set level of the substrate bias voltage VBB is exceeded; Setting voltage control means for controlling a setting level of the substrate bias voltage VBB in response to an input of the detection signal and a refresh signal informing the entry into the refresh operation mode; And a substrate bias voltage pump configured to continuously or stop pumping the substrate bias voltage VBB in response to an input of the substrate bias voltage enable signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

2 is a block diagram illustrating a configuration of a substrate bias voltage control circuit of a semiconductor memory device according to an embodiment of the present invention.

The substrate bias voltage control circuit includes a high potential voltage sensing means 10 for outputting a first sensing signal det_1 according to whether a reference level of the high potential voltage VPP is exceeded, and a setting level of the substrate bias voltage VBB is exceeded. The substrate bias voltage sensing means 20 for outputting a substrate bias voltage enable signal VBB_enb for controlling a pumping operation of the substrate bias voltage VBB according to the input of the first sensing signal det_1. The pumping of the substrate bias voltage VBB is continued or stopped in response to an input of the set voltage control means 30 for controlling the set level of the substrate bias voltage VBB and the substrate bias voltage enable signal VBB_enb. And a substrate bias voltage pump 40.

The operation of the substrate bias voltage control circuit configured as described above will be described with reference to the following drawings.

FIG. 3 is a detailed configuration diagram of the high potential voltage sensing unit shown in FIG. 2.

The high potential voltage detecting means 10 divides the high potential voltage VPP to obtain a first divided voltage Vdiv_1 and a level of the first divided voltage Vdiv_1 and a level of the first divided voltage Vdiv_1. Comparator 120 for comparing the level of the reference voltage (Vref_1) and the driver 130 for driving the signal output as a result of the comparison of the comparison unit 120 to output the first detection signal (det_1). .

Here, the voltage divider 110 includes a resistor array that is a combination of a plurality of resistors connected in series and may change the position of the node 1 N1 according to the level of the first division voltage Vdiv_1 to be obtained. have. For example, if the first divided voltage Vdiv_1 is a voltage having a level corresponding to one half of the high potential voltage VPP, the position of the node 1 N1 is located at the same resistance value at both ends. Done.

The comparator 120 is configured as four transistors having the first divided voltage Vdiv_1 and the first reference voltage Vref_1 as inputs, and the high potential voltage VPP and the ground voltage VSS applied thereto, respectively. In the form of a differential amplifier.

In this case, the first reference voltage Vref_1 is a voltage for comparing with the first division voltage Vdiv_1. Since the first division voltage Vdiv_1 is a voltage divided from the high potential voltage VPP, the first reference voltage Vref_1 is a voltage for measuring whether the reference level of the high potential voltage VPP is exceeded. .

The drive unit 130 is composed of an inverter array which is a combination of a plurality of inverters connected in series. Here, the inverter array is shown as an example of implementing an odd number of inverters.

When the high potential voltage VPP is higher than or equal to the reference level, the first division voltage Vdiv_1 has a higher level than the first reference voltage Vref_1. At this time, a low level voltage is applied to the node 2 N2 of the comparator 120. Thereafter, the voltage of the node 2 N2 is again driven by the driver 130 and output as the first detection signal det_1 having a high level.

Meanwhile, when the high potential voltage VPP is less than or equal to a predetermined level, the first division voltage Vdiv_1 has a level lower than the first reference voltage Vref_1. At this time, a high level voltage is applied to the node 2 N2 of the comparator 120. Thereafter, the voltage of the node 2 N2 is driven by the driver 130 again and output as the first detection signal det_1 having a low level.

4 is a detailed configuration diagram of the substrate bias voltage sensing means and the set level control means shown in FIG.

As shown in the drawing, the substrate bias voltage sensing means 20 may determine whether the driving voltage supply unit 210 for supplying the driving voltage Vdrv to the node 3 N3 exceeds the reference level of the substrate bias voltage VBB. Accordingly, the sensing signal controller 220 controls the voltage level of the node 3 N3 and the driver 230 driving the voltage of the node 3 N3 to output the substrate bias voltage enable signal VBB_enb. do.

In this case, the driving voltage Vdrv is a voltage for generating the substrate bias voltage enable signal VBB_enb and may be implemented as a core voltage Vcore, but is not limited thereto.

In addition, the driving voltage supply unit 210 may be implemented as a resistor array that is a plurality of resistors connected in series or a transistor array that is a plurality of transistors connected in series.

The sensing signal controller 220 includes a transistor array configured to sink or maintain the voltage applied to the node 3 N3 to the ground voltage VSS level according to the level of the substrate bias voltage VBB. Here, node 4 (N4) is present between the plurality of transistors of the transistor array and is connected to the set voltage control means 30. The node 4 N4 changes the resistance value of the sensing signal controller 220 according to whether the first sensing signal det_1 is enabled. Therefore, the timing for raising the set level of the substrate bias voltage VBB is determined by the position of the node 4 N4.

In addition, the driver 230 includes an inverter array which is a combination of a plurality of inverters connected in series. Here, the inverter array is shown as an example of implementing an odd number of inverters.

The set voltage control means 30 is the node 4 (N4) of the substrate bias voltage detection means 20 in response to the input of the first detection signal det_1 transmitted from the high potential voltage detection means 10. The switching transistor 302 is configured to sink or maintain the voltage of the ground voltage VSS.

When the first detection signal det_1 is at a high level, that is, when the high potential voltage VPP is higher than or equal to a predetermined level, the switching transistor 302 of the set voltage control means 30 is turned off. Therefore, the set voltage control means 30 has no influence on the substrate bias voltage sensing means 20, and the voltage level of the node 4 N4 is maintained above a predetermined level.

At this time, when the substrate bias voltage VBB falls above an absolute value of the sum of threshold voltages of all the transistors of the sensing signal controller 220 of the substrate bias voltage sensing means 20, the voltage level of the node 3 N3. Goes to the low level. The low level voltage applied to the node 3 N3 is driven by the driver 230 and output as a high level substrate bias voltage enable signal VBB_enb. The high level substrate bias voltage enable signal VBB_enb is transmitted to the substrate bias voltage pump 40 to stop the pumping operation of lowering the substrate bias voltage VBB level.

On the other hand, when the first detection signal det_1 is at a low level, that is, when the high potential voltage VPP is below a predetermined level, the switching transistor 302 of the set voltage control means 30 is turned on. do. Accordingly, the voltage level of the node 4 N4 is sinked to the ground voltage VSS level.

At this time, the substrate bias voltage VBB is equal to the threshold voltage of the transistor existing between the node 3 (N3) and the node 4 (N4) of the sensing signal controller 220 of the substrate bias voltage sensing means 20. The voltage level of the node 3 (N3) becomes a low level as long as it falls below the absolute value. That is, the voltage level of the node 3 N3 becomes a low level at a timing earlier than when the first detection signal det_1 is at the high level. Thereafter, the low level voltage applied to the node 3 N3 is driven by the driver 230 and output as the high level substrate bias voltage enable signal VBB_enb. The high level substrate bias voltage enable signal VBB_enb is transmitted to the substrate bias voltage pump 40 to stop the pumping operation of lowering the substrate bias voltage VBB level.

As such, when the high potential voltage VPP has a value below the reference level, the substrate bias voltage enable signal VBB_enb is enabled at a faster timing than when the high potential voltage VPP has a value above the reference level. The pumping operation for lowering the substrate bias voltage VBB level of the substrate bias voltage pump 40 is stopped at an early timing.

FIG. 5 is a block diagram illustrating a configuration of a substrate bias voltage control circuit of a semiconductor memory device according to another exemplary embodiment of the present invention. VBB) is an embodiment for the case where it is controlled.

The substrate bias voltage control circuit may include an external power supply sensing means 50 for outputting a second detection signal det_2 and a set level of the substrate bias voltage VBB according to whether the reference level of the external power supply VDD is exceeded. The substrate bias voltage sensing means 60 for outputting the substrate bias voltage enable signal VBB_enb for controlling the pumping operation of the substrate bias voltage VBB, the second sensing signal det_2 and the refresh operation mode In response to the input of the refresh signal (rfsh) for notifying the input voltage control means 70 for controlling the setting level of the substrate bias voltage (VBB) and the input of the substrate bias voltage enable signal (VBB_enb) And a substrate bias voltage pump 40 for continuing or stopping the pumping of the substrate bias voltage VBB.

The operation of the substrate bias voltage control circuit configured as described above will be described with reference to the following drawings.

FIG. 6 is a detailed configuration diagram of the external power supply sensing means shown in FIG. 4.

The external power supply sensing means 50 divides the external power supply VDD to obtain a second divided voltage Vdiv_2, and a level and a second level of the second divided voltage Vdiv_2. Comparator 520 for comparing the level of the reference voltage (Vref_2) and a driver 530 for outputting the second detection signal (det_2) by driving the signal output as a result of the comparison of the comparison unit 520. .

The voltage divider 510 may include a resistor array that is a combination of a plurality of resistors connected in series, and may change the position of the node 5 N5 according to the level of the third divided voltage Vdiv_3. . For example, if the second divided voltage Vdiv_2 is a voltage having a level corresponding to one half of the external supply power VDD, the location of the node 5 N5 is located at the same resistance value at both ends. Done.

The comparator 520 is a four transistor that receives the second divided voltage Vdiv_2 and the second reference voltage Vref_2 as an input and is applied with the external power supply VDD and the ground voltage VSS, respectively. It is configured in the form of a differential amplifier implemented.

In this case, the second reference voltage Vref_2 is a voltage for comparing with the second division voltage Vdiv_2. Since the second divided voltage Vdiv_2 is a voltage distributed from the external power supply VDD, the second reference voltage Vref_2 is a voltage for measuring whether or not the reference level of the external power supply VDD is exceeded. .

The driving unit 530 is configured of an inverter array which is a combination of a plurality of inverters connected in series. Here, the inverter array is shown as an example of implementing an odd number of inverters.

When the external supply power source VDD is equal to or greater than the reference level, the second division voltage Vdiv_2 has a higher level than the second reference voltage Vref_2. At this time, a low level voltage is applied to the node 6 N6 of the comparator 520. Thereafter, the voltage of the node 6 N6 is driven again by the driving unit 530 and output as the second detection signal det_2 having a high level.

Meanwhile, when the external supply power source VDD is less than or equal to a predetermined level, the second division voltage Vdiv_2 has a level lower than the second reference voltage Vref_2. At this time, a high level voltage is applied to the node 6 N6 of the comparator 520. Thereafter, the voltage of the node 6 (N6) is again driven by the driver 530 and output as the second detection signal det_2 having a low level.

FIG. 7 is a detailed configuration diagram of the substrate bias voltage sensing means and the set level control means shown in FIG. 4.

As shown in the drawing, the substrate bias voltage detecting means 60 may determine whether the driving voltage supply unit 610 for supplying the driving voltage Vdrv to the node 7 N7 and the reference level of the substrate bias voltage VBB are exceeded. Accordingly, the sensing signal controller 620 for controlling the voltage level of the node 7 (N7) and the driver 630 for driving the voltage of the node 7 (N7) to output the substrate bias voltage enable signal VBB_enb. It is composed.

In this case, the driving voltage Vdrv is a voltage for generating the substrate bias voltage enable signal VBB_enb and may be implemented as a core voltage Vcore, but is not limited thereto.

In addition, the driving voltage supply unit 610 may be implemented as a resistor array that is a plurality of resistors connected in series or a transistor array that is a plurality of transistors connected in series.

The sensing signal controller 620 includes a transistor array configured to sink or maintain the voltage applied to the node 7 N7 to the ground voltage VSS level according to the level of the substrate bias voltage VBB. Here, a node 8 (N8) exists between the plurality of transistors of the transistor array and is connected to the set voltage control means 70. The node 8 N8 changes the resistance value of the sensing signal controller 620 according to whether the second sensing signal det_2 is enabled. Therefore, the timing for raising the set level of the substrate bias voltage VBB is determined by the position of the node 8 N8.

In addition, the driving unit 630 includes an inverter array which is a combination of a plurality of inverters connected in series. Here, the inverter array is shown as an example of implementing an odd number of inverters.

The set voltage control means 70 receives the second detection signal det_2 transmitted from the external supply power detection means 50 and a refresh signal rfsh indicating that the refresh operation mode is enabled. The voltage of the node 8 (N8) of the substrate bias voltage sensing means 60 is received by the NOR gate 702 outputting a signal corresponding to the NOR gate 702 and the signal output from the NOR gate 702. A switching transistor 704 that sinks or maintains a level.

As shown in the drawing, the second detection signal det_2 and the refresh signal rfsh are enabled when the two signals have a low voltage value.

The set voltage control means when the second detection signal det_2 or the refresh signal rfsh is at a high level, that is, when the external power supply VDD is above a predetermined level or the semiconductor memory device does not enter the refresh mode. The switching transistor 804 of 70 is turned off. Therefore, the set voltage control means 70 has no influence on the substrate bias voltage detection means 60, and the voltage level of the node 8 N8 is maintained above a predetermined level.

At this time, when the substrate bias voltage VBB falls below an absolute value of the sum of threshold voltages of all the transistors of the sensing signal controller 620 of the substrate bias voltage sensing means 60, the voltage level of the node 7 N7 is reduced. Goes to the low level. The low level voltage applied to the node 7 N7 is driven by the driver 630 and output as a high level substrate bias voltage enable signal VBB_enb. The high level substrate bias voltage enable signal VBB_enb is transmitted to the substrate bias voltage pump 40 to stop the pumping operation of lowering the substrate bias voltage VBB level.

On the other hand, when the second detection signal det_2 and the refresh signal rfsh are at a low level, that is, when the external power supply VDD is below a predetermined level and the semiconductor memory device enters a refresh mode, the set voltage control is performed. The switching transistor 704 of the means 70 is turned on. Therefore, the voltage level of the node 8 N8 is sinked to the ground voltage VSS level.

At this time, the substrate bias voltage VBB is equal to the threshold voltage of the transistor existing between the node 7 (N7) and the node 8 (N8) of the sensing signal controller 620 of the substrate bias voltage sensing means 60. The voltage level of the node 7 N7 becomes a low level as long as the voltage falls below an absolute value. That is, the voltage level of the node 7 N7 becomes a low level at a timing earlier than when the second detection signal det_2 or the refresh signal rfsh is at the high level. Thereafter, the low level voltage applied to the node 7 N7 is driven by the driver 630 and output as the high level substrate bias voltage enable signal VBB_enb. The high level substrate bias voltage enable signal VBB_enb is transmitted to the substrate bias voltage pump 40 to stop the pumping operation of lowering the substrate bias voltage VBB level.

As such, when the external power supply VDD has a value equal to or less than a reference level, the substrate bias voltage enable signal VBB_enb is enabled at a faster timing than when the external power supply VDD has a value greater than or equal to the reference level. The pumping operation for lowering the substrate bias voltage VBB level of the substrate bias voltage pump 40 is stopped at an early timing.

8 is a graph illustrating a substrate bias voltage control operation of the semiconductor memory device according to the present invention.

The figure shows the change of the high potential voltage VPP and the substrate bias voltage VBB due to the refresh operation in the low VDD region. During the period in which the refresh signal rfsh is enabled, the high potential voltage VPP drops about 0.5V, but the substrate bias voltage VBB is not dropped. As described above, during the refresh operation in the low VDD region, the high potential voltage VPP is dropped, but the substrate bias voltage VBB is dropped because a set level rises at a constant level as the refresh signal rfsh is enabled. Even if a phenomenon occurs, the value is close to the level originally set at the substrate bias voltage VBB.

As such, when the setting level of the substrate bias voltage VBB is increased when the drop of the substrate bias voltage VBB occurs due to the drop of the high potential voltage VPP level, the drop of the substrate bias voltage VBB is prevented. can do. Also, when the refresh mode is entered in the low VDD region that causes the drop of the high potential voltage VPP level, the set level of the substrate bias voltage VBB is increased to prevent the drop of the substrate bias voltage VBB. can do. Therefore, the malfunction caused by the change of the threshold voltage of the transistor due to the drop of the substrate bias voltage VBB can be blocked in advance.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The substrate bias voltage control circuit of the semiconductor memory device of the present invention described above increases the set level of the substrate bias voltage VBB when the drop phenomenon of the high potential voltage VPP of the semiconductor memory device occurs, thereby increasing the substrate bias voltage VBB. By compensating for the voltage level due to the drop phenomenon of, there is an effect of preventing a malfunction that may occur due to the change in the threshold voltage of each transistor.

Claims (20)

High-potential voltage sensing means for outputting a sensing signal depending on whether or not the reference level of the high-potential voltage VPP is exceeded; Substrate bias voltage sensing means for outputting a substrate bias voltage enable signal for controlling a substrate bias voltage pumping operation according to whether or not a set level of the substrate bias voltage VBB is exceeded; Setting voltage control means for controlling a setting level of the substrate bias voltage VBB in response to an input of the sensing signal; And A substrate bias voltage pump that continues or stops pumping the substrate bias voltage VBB in response to an input of the substrate bias voltage enable signal; Substrate bias voltage control circuit of a semiconductor memory device comprising a. delete The method of claim 1, The high potential voltage detection means, A voltage divider for dividing the high potential voltage VPP to obtain a divided voltage; A comparator for comparing the level of the divided voltage with a level of a reference voltage; And A driving unit which outputs the sensing signal by driving a signal output as a result of the comparison of the comparing unit; Substrate bias voltage control circuit of a semiconductor memory device comprising a. The method of claim 3, wherein The division voltage is extracted from the high potential voltage (VPP) applied to the resistor array provided in the voltage divider. The method of claim 3, wherein And the comparator comprises a differential amplifier which receives the divided voltage and the reference voltage as inputs. The method of claim 5, The reference voltage is a substrate bias voltage control circuit of the semiconductor memory device, characterized in that the voltage for measuring whether or not the reference level of the high potential voltage (VPP). The method of claim 1, The substrate bias voltage sensing means, A driving voltage supply unit for supplying a driving voltage to the first node; And A sensing signal controller configured to control a voltage level of the first node according to whether a reference level of the substrate bias voltage VBB is exceeded; And A driver configured to drive the voltage of the first node to output the substrate bias voltage enable signal; Substrate bias voltage control circuit of a semiconductor memory device comprising a. The method of claim 7, wherein And the driving voltage is a core voltage (Vcore). The method of claim 7, wherein The sensing signal controller may include a transistor array configured to sink or maintain a voltage applied to the first node to the ground voltage VSS level according to the level of the substrate bias voltage VBB. And a second node for changing a resistance value of the sensing signal controller according to whether the sensing signal is enabled between transistors. The method of claim 9, The set voltage control means is configured to sink or maintain the voltage of the second node of the substrate bias voltage sensing means to the ground voltage VSS in response to the input of the sensing signal transmitted from the high potential voltage sensing means. A substrate bias voltage control circuit of a semiconductor memory device comprising a switching transistor. External power supply sensing means for outputting a detection signal depending on whether or not the reference level of the external power supply VDD is exceeded; Substrate bias voltage sensing means for outputting a substrate bias voltage enable signal for controlling a pumping operation of the substrate bias voltage VBB according to whether or not the set level of the substrate bias voltage VBB is exceeded; Setting voltage control means for controlling a setting level of the substrate bias voltage VBB in response to an input of the detection signal and a refresh signal informing the entry into the refresh operation mode; And A substrate bias voltage pump that continues or stops pumping the substrate bias voltage VBB in response to an input of the substrate bias voltage enable signal; Substrate bias voltage control circuit of a semiconductor memory device comprising a. delete The method of claim 11, The external power supply detection means, A voltage divider for distributing the external supply power VDD to obtain a divided voltage; A comparator for comparing the level of the divided voltage with a level of a reference voltage; And A driving unit which outputs the sensing signal by driving a signal output as a result of the comparison of the comparing unit; Substrate bias voltage control circuit of a semiconductor memory device comprising a. The method of claim 13, And the division voltage is extracted from the external power supply (VDD) applied to a resistor array provided in the voltage division unit. The method of claim 13, And the comparator comprises a differential amplifier which receives the divided voltage and the reference voltage as inputs. The method of claim 15, The reference voltage is a substrate bias voltage control circuit of the semiconductor memory device, characterized in that the voltage for measuring whether or not the reference level of the external power supply (VDD). The method of claim 11, The substrate bias voltage sensing means, A driving voltage supply unit for supplying a driving voltage to the first node; And A sensing signal controller configured to control a voltage level of the first node according to whether a reference level of the substrate bias voltage VBB is exceeded; And A driver configured to drive the voltage of the first node to output the substrate bias voltage enable signal; Substrate bias voltage control circuit of a semiconductor memory device comprising a. The method of claim 17, And the driving voltage is a core voltage (Vcore). The method of claim 17, The sensing signal controller may include a transistor array configured to sink or maintain the voltage applied to the first node to the ground voltage VSS level according to the level of the substrate bias voltage VBB. And a second node for changing a resistance value of the sensing signal controller according to whether the sensing signal is enabled between transistors. The method of claim 19, The set voltage control means, A nor gate receiving the sensing signal and the refresh signal and outputting a signal corresponding to whether the two signals are enabled or not; And A switching transistor configured to receive a signal output from the NOR gate to sink or maintain the voltage of the second node to the ground voltage level; Substrate bias voltage control circuit of a semiconductor memory device comprising a.

Images