KR100672170B1 - Semiconductor memory device having a circuit for generating precharge voltage of a bit line and method of precharging a bit line thereof - Google Patents

Abstract

A semiconductor memory device having a circuit for generating a bit line precharge voltage and a bit line precharging method thereof are provided to generate a stable bit line precharge voltage by additionally using a reference voltage generator and a precharge voltage driver. A memory cell array(500) includes a bit line. A reference voltage generator(100) is used for generating a reference voltage. A bit line precharge voltage generator(210) is used for generating a bit line precharge voltage for precharging the bit line according to the output of the reference voltage generator. A bit line precharge driver(220) is used for maintaining the bit line precharge voltage constantly by comparing the bit line precharge voltage with the reference voltage.

Description

Semiconductor memory device having a bit line precharge voltage generating circuit and a method of precharging the bit line of the bit line precharge voltage of a bit line and method of precharging a bit line

1 is a bit line precharge voltage generation circuit according to the prior art.

2 is a potential diagram of data input / output lines during successive read and bit line precharge operations of a memory device.

3 is a configuration diagram of a semiconductor memory device having a bit line precharge voltage generation circuit according to the present invention.

4 is a circuit diagram illustrating the reference voltage generator of FIG. 3.

FIG. 5 is a circuit diagram illustrating the bit line precharge voltage driver of FIG. 3.

Description of the main parts of the drawing

10: voltage generator 20: output unit

100: reference voltage generator 200: bit line precharge voltage generator

300: bit line precharge voltage driver

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a bit line precharge voltage generation circuit and a bit line precharge method using the same. In particular, the present invention prevents drop of the bit line precharge voltage, A semiconductor memory device having an improved bit line precharge voltage generation circuit and a bit line precharge method thereof.

In general, a bit line of a semiconductor device is precharged at a half voltage (Vcc / 2) in a standby mode, and when operated in an active mode, data of a cell stored in a cell array is stored in the bit line. Since it is sensed and amplified by the bit line sense amplifier after being transmitted to the bit line has a constant supply voltage (Vcc) or ground voltage (Vss). The precharge voltage Vblp generated from the precharge voltage generation circuit is used to precharge the bit line to the half voltage Vcc / 2.

1 is a bit line precharge voltage generation circuit diagram according to the prior art.

Referring to FIG. 1, the bit line precharge voltage generation circuit is controlled by a voltage generator 10 generating a voltage and a voltage generated by the voltage generator 10 to generate a bit line precharge voltage Vblp. It is configured to include an output unit 20.

The voltage generator 10 includes a plurality of resistors R1 and R2 and transistors NM1 and PM1 connected in series between the power supply voltage Vcc and the ground voltage Vss. The resistor R1 is connected between the power supply voltage Vcc and the node N1. The first NMOS transistor NM1 is connected between the node N1 and the node N2 and the node N1 is connected to the gate. The first PMOS transistor PM1 is connected between the node N2 and the node N3 and the node N3 is connected to the gate. The resistor R2 is connected between the node N3 and the ground power supply Vss. The reference voltage Vref is applied to the node N2.

The output unit 20 is connected in series between the power supply voltage Vcc and the ground voltage Vss, and the second NMOS transistor NM2 and the gate whose gate is connected to the node N1 of the voltage generator 10 are connected to the output voltage 20. And a second PMOS transistor PM2 connected to the node N3 of the voltage generator 10, thereby freeing bit lines at a node between the second NMOS transistor NM2 and the second PMOS transistor PM2. The charge voltage Vblp is output.

A schematic operation of the conventional bit line precharge voltage generation circuit configured as described above is as follows.

First, when the magnitudes of the first and second load resistors R1 and R2 of the voltage generator 10 are sufficiently large, a current of several μA flows through the voltage generator 10, and the output unit 20 receives a few μA. Drive current of mA is generated. At this time, if the magnitudes of the first and second load resistors R1 and R2 are the same, and the threshold voltages of the first NMOS transistor NM1 and the first PMOS transistor PM1 are the same, the output terminal of the output unit 20 The bit line precharge voltage Vblp, which is half of the power supply voltage Vcc, is output. If the bit line precharge voltage Vblp lower than the reference voltage is output because the sizes of the first and second load resistors R1 and R2 are different from each other, between the first NMOS transistor NM1 and the first PMOS transistor PM1. The potential of the third node N3 is increased by the reference voltage Vref applied to the second node N2 of the transistor, thereby decreasing the amount of current flowing through the second PMOS transistor PM2, thereby precharging the bit line. The potential of the voltage Vblp rises.

2 is a potential diagram of data input / output lines during successive read and bit line precharge operations of a memory device.

Referring to FIG. 2, the amount of use of the bit line precharge voltage Vblp increases rapidly due to the continuous read operation and the bit line precharge operation of the memory device. In this case, the bit line precharge voltage generation circuit may not keep up with the usage in terms of driving ability and response speed, and a drop phenomenon may occur in which the potential of the bit line precharge voltage Vblp falls.

Accordingly, the present invention provides a bit line precharge voltage generation circuit in which a precharge voltage is stably generated using a driving circuit for compensating for the drop of the bit line precharge voltage and a variable reference voltage generator to improve driving ability and response speed. There is provided a semiconductor memory device and a bit line precharge method using the same.

A semiconductor memory device having a bit line precharge voltage generation circuit according to the present invention includes a memory cell array having a bit line, a reference voltage generator for generating a reference voltage, and a bit line according to an output of the reference voltage generator. Bit line precharge comprising a bit line precharge voltage generator for generating a bit line precharge voltage for precharging, and a bit line precharge driver for maintaining the bit line precharge voltage constant compared to the reference voltage. It includes a voltage generator circuit.

The bit line precharge voltage driver may include a differential amplifier configured to differentially input the reference voltage and the bit line precharge voltage, and a pull up unit configured to pull up the bit line precharge voltage in response to an output of the differential amplifier.

A bit line precharge method of a semiconductor memory device according to the present invention includes generating a variable reference voltage in a variable reference voltage generator, and generating a bit line precharge voltage in a bit line precharge voltage generation circuit in response to the reference voltage. Applying a bit line precharge voltage to a bit line of a memory cell array to precharge the bit line, and a continuous precharge operation of the semiconductor memory device, thereby lowering the potential of the bit line precharge voltage. And pulling up the bit line precharge voltage to a potential of the reference voltage in the bit line precharge voltage generation circuit.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 is a configuration diagram illustrating a semiconductor memory device including a bit line precharge voltage generation circuit according to the present invention.

Referring to FIG. 3, a semiconductor memory device including a bit line precharge voltage generation circuit according to an embodiment of the present invention receives a reference voltage generator 100 generating a variable reference voltage Vref and a reference voltage Vref. Bit line precharge voltage driver for comparing the bit line precharge voltage generator 210 generating the bit line precharge voltage Vblp with the bit line precharge voltage Vblp and the reference voltage Vref to perform a pull-up operation. A bit line precharge voltage generation circuit 200 including a 220, a stabilization unit 300 for applying a bit line precharge voltage to a bit line of a memory cell, and bit line sensing for sensing data carried on the bit line And a memory cell array 500 having an amplifier 400 and a plurality of memory cells capable of storing data.

FIG. 4 is a circuit diagram illustrating in detail the reference voltage generator 100 of the bit line precharge voltage generator circuit of FIG. 3.

Referring to FIG. 4, the reference voltage generator includes a plurality of resistors R11 to R14, a PMOS transistor PM11, and an NMOS transistor NM11.

The plurality of resistors R11 to R14 are connected in series between the core voltage Vcore and the ground power supply Vss. The PMOS transistor PM11 is connected in parallel with the resistor R11 and a first test signal testmode input1 is applied to the gate terminal. The NMOS transistor NM11 is connected in parallel with the resistor R14, and a second test signal testmode input2 is applied to the gate terminal. The resistor R12 and the resistor R13 may be adjusted with a variable resistor.

Since the bit line precharge voltage generator 210 of FIG. 3 is configured in the same manner as the bit line precharge voltage generator circuit (FIG. 1) according to the related art, a detailed description thereof will be omitted.

 FIG. 5 is a circuit diagram illustrating in detail the bit line precharge voltage driver of FIG. 3.

Referring to FIG. 5, the bit line precharge voltage driver according to the present invention includes a differential amplifier 221, an enable unit 222, and a pull-up unit 223.

The differential amplifier 221 includes a first PMOS transistor PM101 and a second PMOS transistor PM102, a first NMOS transistor NM101, and a second NMOS transistor NM102. Gate terminals are commonly connected to the first PMOS transistor PM101 and the second PMOS transistor PM102 and a power supply voltage Vcc is applied through the common source terminal. The first NMOS transistor NM101 is connected between the node ND11 and the enable unit 222 to receive a reference voltage Vref through the gate terminal. In addition, the second PMOS transistor PM102 is connected between the node ND12 and the enable unit 222 so that the bit line precharge voltage Vblp is applied through the gate terminal.

The enable unit 222 includes a third NMOS transistor NM103 connected between the differential amplifier 221 and the ground power source Vss to apply a reference voltage Vref through a gate terminal to perform a switching operation.

The pull-up unit 223 is connected to the output terminal of the power supply voltage Vcc and the bit line precharge voltage Vblp, and the third PMOS transistor PM103 having a gate terminal connected to the node ND11 of the differential amplifier 221. It is provided.

An operation of a semiconductor memory device having a bit line precharge voltage generation circuit according to the present invention will be described with reference to FIGS. 3 to 5 as follows.

Referring to FIG. 4, the reference voltage generator 100 generates a reference voltage Vref. In detail, the potential of the node ND2 due to the voltage distribution of the resistors R11 to R14 connected in series between the core voltage Vcore and the ground power supply Vss is output as the reference voltage Vref potential. At this time, when the potential of the generated reference voltage Vref is higher or lower than the desired potential, the first and second test signals Testmode inputs 1 and 2 are applied to turn on or turn on the PMOS transistor PM11 and the NMOS transistor NM11. The potential of the reference voltage Vref can be adjusted by turning off the entire resistance value. For example, when the first and second test signals Testmode inputs 1 and 2 are applied at a high level, the PMOS transistor PM11 is turned off and the NMOS transistor NM11 is turned on. Therefore, the potential of the reference voltage Vref is lowered by the ratio of the resistance value of the resistor R11 and the resistor R12 to the resistance value of the resistor R13. In addition, when the first and second test signals Testmode inputs 1 and 2 are applied at a low level, the potential of the reference voltage Vref is increased. In addition, the resistors R12 and R13 are variable resistors, and the potential of the reference voltage Vref may be adjusted by changing the resistance value.

Since the operation of the bit line precharge voltage generator 210 is the same as that of the conventional bit line precharge voltage generator circuit (FIG. 1), a detailed description thereof will be omitted.

An operation of the bit line precharge voltage driver 220 will be described with reference to FIG. 5.

  First, the initial potential of the node ND12 is applied to the gates of the first PMOS transistor PM101 and the second PMOS transistor PM102 to adjust the amount of current of the power supply voltage Vcc applied to the differential amplifier 221. At this time, assuming that the first PMOS transistor PM101 and the second PMOS transistor PM102 are transistors of the same size, there is no potential difference between the node ND11 and the node ND12. Thereafter, the reference voltage Vref is applied to the first NMOS transistor NM101 to adjust the amount of current flowing between the node ND11 and the node ND13. In addition, the bit line precharge voltage Vblp output from the bit line precharge voltage generator is applied to the second NMOS transistor NM102 to adjust the amount of current flowing between the node ND12 and the node ND13. In addition, the reference voltage Vref is applied to the third NMOS transistor NM103 of the enable unit 222 so that the third NMOS transistor NM103 is turned on. Therefore, the ground power supply Vss and the node ND13 are connected. In this case, when a drop phenomenon in which the potential of the bit line precharge voltage Vblp falls due to the continuous read operation and the precharge operation of the semiconductor memory device occurs, the current flows between the node ND12 and the node ND13. It becomes smaller than the amount of current flowing between the node ND11 and the node ND13. As a result, the potential of the node ND12 rises, thereby reducing the amount of current of the power supply voltage Vcc applied to the node ND11d by the first PMOS transistor PM101. Therefore, the potential value of the node ND11 goes down. The potential value of the lowered node ND11 is connected to the gate of the third PMOS transistor PM103 of the pull-up unit 223 so that the third PMOS transistor PM103 is turned on. Accordingly, the bit line precharge voltage Vblp and the power supply voltage Vcc are connected to increase the potential of the bit line precharge voltage Vblp. Therefore, the potential drop of the bit line precharge voltage Vblp is compensated for by the continuous read operation and the precharge operation of the semiconductor memory device.

Although not shown in the drawings of the present invention, the enable portion and the pull-up portion of the bit line precharge voltage driver may be additionally configured with a transistor, a resistor, or a capacitor, and may be used as a test mode or option. In the test mode or option, if the performance of the device is degraded due to the error after the package of the semiconductor memory device, the error of the circuit is broken by breaking the connected line with a laser or by attaching a metal line by shooting a part to be connected with a beam. By correcting this, the driving ability can be improved and the driving speed can be improved.

The generated bit line precharge voltage Vblp is output to the stabilization unit 300. The stabilization unit 300 precharges the bit line by applying the bit line precharge voltage Vblp to the selected bit line BL or / BL in response to the bit line precharge signal.

 Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention, in order to compensate for the potential drop of the bit line precharge voltage due to the continuous read operation and the precharge operation of the semiconductor memory device, a variable reference voltage generator and a bit line precharge voltage driver are additionally configured to provide stable stability. Generate a bit line precharge voltage.

Claims (6)

A memory cell array having bit lines; A reference voltage generator for generating a reference voltage; A bit line precharge voltage generator for generating a bit line precharge voltage for precharging the bit line according to the output of the reference voltage generator; And And a bit line precharge voltage generator circuit for maintaining the bit line precharge voltage constant compared to the reference voltage. The voltage generator of claim 1, wherein the bit line precharge voltage generator comprises: A voltage generator for generating a bias by receiving the reference voltage; And And a bit line precharge voltage generation circuit including an output unit controlled by the bias to generate a bit line precharge voltage. 2. The method of claim 1, wherein the bit line precharge voltage driver A differential amplifier configured to differentially input the reference voltage and the bit line precharge voltage; A switch unit to enable the bit line precharge voltage driver in response to the reference voltage; And And a pull-up unit configured to pull up the bit line precharge voltage in response to an output of the differential amplifier. The method of claim 3, wherein The differential amplifying unit is connected to a current mirror structure to receive a supply power supply circuit; And And a bit line precharge voltage generation circuit comprising a differential input circuit receiving the reference voltage and the bit line precharge voltage. The method of claim 1, The reference voltage generator includes a test unit for controlling a connection of a resistor in response to a control signal; And A semiconductor memory device comprising a bit line precharge voltage generation circuit including a variable resistor section for varying a resistance value and adjusting a potential of an output reference voltage. A bit line precharge method of a semiconductor memory device having a variable reference voltage generator and a bit line precharge voltage generation circuit, Generating a variable reference voltage in the variable reference voltage generator; Generating a bit line precharge voltage in the bit line precharge voltage generation circuit in response to the reference voltage; Precharging the bit line by applying a bit line precharge voltage to a bit line of a memory cell array; And Pulling up the bit line precharge voltage to the potential of the reference voltage in the bit line precharge voltage generation circuit when the potential of the bit line precharge voltage drops due to the continuous precharge operation of the semiconductor memory device; A bit line precharge method for a semiconductor memory device.

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