KR100780633B1 - Over driver control signal generation circuit of semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a bit line overdriving scheme of a semiconductor memory device, and more particularly to a circuit for generating an overdriving pulse for controlling an over driver. An object of the present invention is to provide an over-driver control signal generation circuit of a semiconductor memory device capable of securing a stable voltage level of a normal driving voltage terminal regardless of a power supply voltage (VDD) level. In the present invention, the overdriving section is set relatively long in a low voltage environment, and the overdriving section is set relatively short in a high voltage environment. To this end, the present invention includes first and second pulse generators having different delay values, and multiplexes the pulse width of the over driver control signal according to the detection result of the power supply voltage VDD level.

Description

OVER DRIVER CONTROL SIGNAL GENERATOR IN SEMICONDUCTOR MEMORY DEVICE}

1 is a diagram illustrating a configuration of an array of bit line sense amplifiers using an overdriving scheme.

2 is a block diagram illustrating an overdriving pulse generation path.

3 is a circuit diagram illustrating a configuration of an overdriving pulse generator of FIG. 2.

4 shows the signal waveform of FIG.

5 is a view showing a simulation result of the power supply voltage (VDD) of the over driver circuit according to the prior art.

6 is a block diagram illustrating an overdriving pulse generation circuit of a semiconductor memory device according to an embodiment of the present invention.

7 illustrates a circuit implementation of FIG. 6.

FIG. 8 is a diagram illustrating a simulation result of a power supply voltage VDD of the over driver circuit of FIG. 7. FIG.

* Explanation of symbols for the main parts of the drawings

510: first pulse generator

520: the second pulse generator

530: power supply voltage level detection unit

540: multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design techniques, and more particularly, to a bit line overdriving scheme of a semiconductor memory device, and more particularly to a circuit for generating an overdriving pulse for controlling an over driver.

As the continuous scaling down of the line width and the cell size constituting the semiconductor memory chip proceeds, the voltage reduction of the power supply voltage is accelerated, and accordingly, a design technique for satisfying the performance required in a low voltage environment is required.

Currently, most semiconductor memory chips are provided with an internal voltage generator circuit for generating an internal voltage by receiving an external voltage (power supply voltage) to supply a voltage necessary for the operation of the chip internal circuit. In particular, in the case of a memory device using a bit line sense amplifier such as DRAM, a core voltage VCORE is used to detect cell data.

When the word line selected by the row address is activated, data of a plurality of memory cells connected to the word line is transferred to the bit line, and the bit line sense amplifier senses and amplifies the voltage difference between the pair of bit lines. Thousands of such bitline sense amplifiers operate at a time, consuming a large amount of current from the core voltage stage (VCORE) used to drive the pull-up power line (commonly referred to as RTO) of the bitline sense amplifier. However, it is difficult to amplify the data of many cells in a short time by using the core voltage VCORE in the trend that the operating voltage decreases.

In order to solve this problem, the RTO power line of the bit line sense amplifier is initially higher than the core voltage (VCORE) for a predetermined period of time at the beginning of operation of the bit line sense amplifier (just after the charge sharing between the memory cell and the bit line). A bit line sense amplifier overdriving method driven by voltage (VDD) is adopted.

1 is a diagram illustrating a configuration of a bit line sense amplifier array employing an overdriving scheme.

Referring to FIG. 1, the bit line sense amplifier array may include a bit line sense amplifier 30, an upper bit line separator 10, a lower bit line separator 50, and a bit line regardless of whether overdriving is adopted. An equalization / precharge unit 20, a column selector 40, and a bit line sense amplifier power line driver 60 are included.

Here, the upper bit line separation unit 10 is for separating / connecting the upper memory cell array and the sensing amplifier 30 in response to the upper separation signal BISH, and the lower bit line separation unit 50 is a lower separation signal. In order to disconnect / connect the lower memory cell array and the sense amplifier 30 in response to (BISL).

When the enable signal is activated and the pull-down power line (commonly referred to as SB) and the pull-up power line (RTO) are driven to a predetermined voltage level, the bit line sense amplifier 30 (BL, BLB)-charge sharing With a slight voltage difference as a state, a voltage difference of-is sensed and one is amplified to ground voltage VSS and one to core voltage VCORE.

In addition, the bit line equalizer / precharge unit 20 bits the bit line pairs BL and BLB in response to the bit line equalization signal BLEQ after completing the sensing / amplification and restoring process for the bit line. It is for precharging to the line precharge voltage VBLP-usually VCORE / 2.

When the read command is applied, the column selector 40 transfers the data sensed / amplified by the sense amplifier 30 to the segment data buses SIO and SIOB in response to the column select signal YI.

Meanwhile, the bit line sense amplifier power line driver 60 pulls down the PMOS transistor M2 for driving the RTO power line with a voltage applied to the core voltage terminal VCORE in response to the pull-up power line driving control signal SAP. In response to the power line driving control signal SAN, the NMOS transistor M3 for driving the SB power line with the ground voltage VSS, and the core voltage terminal in response to the overdriving pulse SAOVDP-over driver control signal- And the RTO power line and SB power line of the bit line sense amplifier 30 in response to the PMOS transistor M1-over driver-and the bit line equalization signal BLEQ for driving VCORE to the power supply voltage VDD. And a bit line sense amplifier BLSA power line equalization / precharge unit 62 for precharging to the bit line precharge voltage VBLP.

Here, the case where the over driving pulse SAOVDP is defined as a low active pulse and the over driver is implemented as the PMOS transistor M1 is illustrated. However, an NMOS transistor may be used as the over driver. The same applies to the PMOS transistor M2 controlled by the pull-up power line driving control signal SAP.

2 is a block diagram illustrating a path for generating an overdriving pulse (SAOVDP).

Referring to FIG. 2, an enable signal generator 200 for generating a BLSA enable signal SAEN in response to an active command ACT and a precharge command PCG may be included in an overdriving pulse SAOVDP generation path. And a power line driving control signal generator 210 for generating a pull-up power line driving control signal SAP, a pull-down power line driving control signal SAN, and an overdriving signal OVD using the BLSA enable signal SAEN. ) And an overdriving pulse generator 220 for generating an overdriving pulse SAOVDP by receiving the overdriving signal OVD.

3 is a circuit diagram illustrating the configuration of the overdriving pulse generator 220 of FIG. 2.

Referring to FIG. 3, the overdriving pulse generator 220 receives a delay for delaying the overdriving signal OVD by a predetermined time and an overdriving signal delayed through the overdriving signal OVD and the delay as an input. And a NOR gate NOR10 for outputting the overdriving pulse SAOVDP.

FIG. 4 is a diagram illustrating a signal waveform of FIG. 3. Hereinafter, a description will be given of a driving operation of a bit line sense amplifier (BLSA) power line according to the related art.

First, an active command ACT is applied to activate a word line, and data stored in a cell is induced in the bit line pairs BL and BLB by charge sharing, and then, after a predetermined time, the pull-up power line driving control signal SAP is applied. Is activated to a logic level low, and the pull-down power line drive control signal SAN is activated to a logic level high. At this time, the RTO power line is overdriven by an overdriving pulse SAOVDP activated at a logic level low in advance (at least at the same time) than the pull-up and pull-down power line driving control signals SAP and SAN in response to the active command ACT. . That is, when both pull-up and pull-down power line drive control signals (SAP, SAN) and overdriving pulses (SAOVDP) are activated, transistors M1, M2, and M3 are all turned on to drive the RTO power line to the power supply voltage (VDD), and the SB power supply. The line is driven to the ground voltage (VSS).

Thereafter, after a certain time, the overdriving pulse SAOVDP is deactivated to a logic level high to drive the RTO power line to the core voltage VCORE, and when a precharge command PCG is applied, a pull-up and pull-down power line drive control signal. (SAP and SAN) are deactivated and the RSA power line and the SB power line are precharged to the bit line precharge voltage VBLP level by the BLSA power line equalization / precharge unit 62. The bit line precharge voltage VBLP typically has a VCORE / 2 level.

5 is a diagram illustrating a simulation result of a power supply voltage VDD of an over driver circuit according to the related art.

Referring to FIG. 5, in a low voltage environment in which the power supply voltage VDD is about 1.6V and the core voltage VCORE is about 1.5V, there is no problem in overdriving operation.

This is because, as described above, the voltage reduction trend of the semiconductor memory device is considered from the design stage, and the size of the over driver transistor M1 is also designed to supply an appropriate current to the core voltage terminal VCORE in a low voltage environment.

However, in a high voltage environment in which the power supply voltage VDD is about 2V, the over driver transistor M1 supplies excessive current to the core voltage terminal VCORE in the overdriving period, and the voltage level of the core voltage terminal VCORE is suddenly increased. The core voltage terminal VCORE has an excessive voltage level. As such, when the voltage level of the core voltage terminal VCORE rises excessively, there is a problem of deterioration in operating characteristics.

Meanwhile, as shown in FIG. 5, the activation period (pulse width) of the overdriving pulse SAOVDP in the high voltage environment is somewhat shorter than that in the low voltage environment, which is due to the reduction of propagation delay due to the voltage rise. The effect is negligible.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above problems of the prior art, and is an over-driver control signal generation circuit of a semiconductor memory device capable of securing a stable voltage level of a normal driving voltage terminal regardless of a power supply voltage (VDD) level. The purpose is to provide.

According to an aspect of the present invention for achieving the above technical problem, in the over-driver control signal generation circuit of a semiconductor memory device for generating a bit line over driver control signal by receiving an over-driving signal generated by receiving an active command First pulse generating means for generating a first pulse signal having a first pulse width in response to the overdriving signal; Second pulse generating means for generating a second pulse signal having a second pulse width, which is shorter than the first pulse width, in response to the overdriving signal; Power supply voltage level detecting means for detecting a power supply voltage level; And a multiplexer for selectively outputting the first pulse signal or the second pulse signal as the over driver control signal in response to the detection signal output from the power supply voltage level detecting means. Circuitry is provided.

According to another aspect of the present invention, a method of generating a bit line over driver control signal by receiving an overdriving signal generated by receiving an active command, comprising: a first having a first pulse width in response to the overdriving signal; Generating a pulse signal; Generating the second pulse signal having a second pulse width, which is shorter than the first pulse width, in response to the overdriving signal; Detecting a power supply voltage level; And selectively outputting the first pulse signal or the second pulse signal as the over driver control signal in response to the detection result of the power supply voltage level.

In the present invention, the overdriving section is set relatively long in a low voltage environment, and the overdriving section is set relatively short in a high voltage environment. To this end, the present invention includes first and second pulse generators having different delay values, and multiplexes the pulse width of the over driver control signal according to the detection result of the power supply voltage VDD level.

Hereinafter, preferred embodiments of the present invention will be introduced so that those skilled in the art can more easily implement the present invention.

6 is a block diagram illustrating an overdriving pulse generation circuit of a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 6, the overdriving pulse generation circuit according to the present embodiment may generate a first pulse signal PRE1 having a first pulse width in response to an overdriving signal OVD generated by receiving an active command ACT. A first pulse generator 510 for generating and a second pulse signal PREP2 having a second pulse width, which is shorter than the first pulse width, in response to the overdriving signal OVD. The overdriving pulse SAOVDP in response to the pulse generator 520, the power supply voltage level detector 530 for detecting the power supply voltage VDD level, and the detection signal DETCM output from the power supply voltage level detector 530. ), A multiplexing unit 540 for selectively outputting the first pulse signal PREP or the second pulse signal PREP2.

FIG. 7 is a diagram illustrating a circuit implementation of FIG. 6.

Referring to FIG. 7, the first pulse generator 510 may output a first delay 512 for delaying the overdriving signal OVD, and output signals of the overdriving signal OVD and the first delay 512. A NOR gate NOR12 for outputting the first pulse signal PRE1 as an input is provided. The first pulse generator 510 is identical to the configuration of the overdriving pulse generator 220 of FIG. 3, and the first delay 512 is an overdriving signal at a pulse width of a desired first pulse signal PREP1. The delay time is obtained by subtracting the pulse width of (OVD).

In addition, the second pulse generator 520 may include a second delay 522 for delaying the overdriving signal OVD, an inverter INV10 for inputting an output signal of the second delay 522, and overdriving. And a NAND gate NAND10 for outputting the second pulse signal PREP2 by inputting the signal OVD and the output signal of the inverter INV10. The second delay 522 of the second pulse generator 520 has a delay time corresponding to the pulse width of the desired second pulse signal PREP2. Thus, it is meaningless to discuss the relative long and shortness of the delay times of the first delay 512 and the second delay 522.

The power supply voltage level detector 530 may further include a voltage divider 532 for distributing the power supply voltage VDD at a predetermined ratio, and an output voltage C of the voltage divider 532 in response to the enable signal EN. ) And a comparison unit 534 for comparing the reference voltage (VREF). Here, the voltage divider 532 is implemented with resistors R1 and R2 connected in series between the power supply voltage terminal VDD and the ground voltage terminal VSS. The comparator 534 includes a bias NMOS transistor M4, It can be implemented in the form of a general NMOS bias type current mirror type differential amplifier circuit such as input NMOS transistors M5 and M6 and load PMOS transistors M7 and M8 for current mirrors. When the resistance values of the resistors R1 and R2 of the voltage divider 532 are the same, the reference voltage VREF may be a voltage that targets the VDD / 2 level.

In addition, the multiplexer 540 may include an inverter INV12 that receives the detection signal DETCM output from the power supply voltage level detector 530, an output signal DETCMB of the inverter INV12, and a first pulse generator ( NAND gate NAND12 to which the first pulse signal PREP1 output from 510 is input, inverter INV14 which receives the output signal of NAND gate NAND12, detection signal DETCM and the second pulse. NAND gate NAND14, which receives the second pulse signal PRE2 output from the generation unit 520, inverter INV16, which receives the output signal of the NAND gate NAND14, inverter INV14, and inverter NAND gate NOR14 for inputting the output signal of INV16 and NAND gate for outputting the overdriving pulse SAOVDP with the output signal and enable signal EN of the NOR gate NOR14 as inputs. ).

FIG. 8 is a diagram illustrating a simulation result of a power supply voltage VDD of the over driver circuit of FIG. 7. Here, the case where the high voltage is VDD = 2V, the low voltage is VDD = 1.6V, the reference voltage (VREF) is set to 0.8V and when the VDD = 1.8V, the output node (C) of the voltage divider is referred to as 0.8V The resistance ratio was adjusted to have the same level as the voltage VREF.

The enable signal EN is deactivated to a logic level low when the semiconductor memory device is in an idle state and is activated to a logic level high when the semiconductor memory device is in an active state. In the idle state where the enable signal EN is deactivated to the logic level low, the overdriving pulse SAOVDP is always deactivated to the logic level high.

Referring to FIG. 8, first, in a low voltage environment (VDD = 1.6V), the detection signal DETCM output from the power supply voltage level detector 530 becomes a logic level low. Therefore, when the enable signal EN is activated at a logic level high, the multiplexer 540 blocks the second pulse signal PREP2 and selects the first pulse signal PREP1 to overdrive pulse SAOVDP. Will be output as

As shown in the drawing, the first pulse signal PREP1 has a larger pulse width than the second pulse signal PREP2, thereby securing a sufficient overdriving period, thereby sufficiently maintaining the core voltage stage VCORE even in a low voltage environment. It can be driven.

On the other hand, in the high voltage environment (VDD = 2V), the detection signal DETCM output from the power supply voltage level detection unit 530 becomes logic level high. Therefore, when the enable signal EN is activated at a logic level high, the multiplexer 540 blocks the first pulse signal PREP1 and selects the second pulse signal PREP2 to overdrive pulse SAOVDP. Will be output as

As shown in the drawing, the second pulse signal PREP2 has a shorter pulse width compared to the first pulse signal PREP1, so that the overdriving period is very small, thereby increasing the potential of the core voltage terminal VCORE excessively in a high voltage environment. Can be prevented.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

For example, in the above-described embodiment, the over-driving method in which the normal driver drives the RTO power line and the over driver drives the core voltage terminal VCORE is described as an example. However, the over-driver and the normal driver use the RTO power line in parallel. The present invention also applies to driving.

In addition, in the above-described embodiment, the case in which the core voltage VCORE is used as the normal driving voltage and the power supply voltage VDD as the over driving voltage has been described as an example. This also applies when using.

In addition, in the above-described embodiment, the case where the multiplexer is implemented using only the logic gate has been described as an example. However, the multiplexer may be implemented using two transmission gates.

In addition, the logic gate and the transistor illustrated in the above embodiment should be implemented in different positions and types depending on the polarity of the input signal.

The present invention described above has the effect of ensuring a stable overdriving operation irrespective of the level of the power supply voltage, thereby reducing the operating characteristics of the semiconductor memory device and reducing defects.

Claims (9)

In the over-driver control signal generation circuit of a semiconductor memory device for receiving the over-driving signal generated by receiving an active command to generate a bit line over driver control signal, First pulse generating means for generating a first pulse signal having a first pulse width in response to the overdriving signal; Second pulse generating means for generating a second pulse signal having a second pulse width, which is shorter than the first pulse width, in response to the overdriving signal; Power supply voltage level detecting means for detecting a power supply voltage level; And A multiplexer for selectively outputting the first pulse signal or the second pulse signal as the over driver control signal in response to a detection signal output from the power supply voltage level detecting means An over driver control signal generation circuit of a semiconductor memory device having a. The method of claim 1, The first pulse generating means, A first delay for delaying the overdriving signal; And a first NOR gate for outputting the first pulse signal by inputting the overdriving signal and the output signal of the first delay. The method of claim 2, The second pulse generator, A second delay for delaying the overdriving signal; And a first NAND gate for outputting the second pulse signal by inputting the inverted signal of the output signal of the second delay and the overdriving signal. The method of claim 1, The power supply voltage level detecting means, A voltage divider for dividing the power supply voltage at a predetermined rate; And a comparator for comparing an output voltage of the voltage divider with a reference voltage in response to an enable signal. The method of claim 4, wherein And the voltage divider includes first and second resistors connected in series between a power supply voltage terminal and a ground voltage terminal. The method of claim 5, And the comparator comprises an NMOS bias type current mirror type differential amplifier circuit which uses the output voltage and the reference voltage as differential inputs of the voltage divider. The method of claim 4, wherein The multiplexing means, A second NAND gate inputting the inverted signal of the detection signal and the first pulse signal; A first inverter configured to receive an output signal of the second NAND gate; A third NAND gate which receives the detection signal and the second pulse signal as inputs; A second inverter configured to receive an output signal of the third NAND gate; A second NOR gate for inputting output signals of the first and second inverters; And a fourth NAND gate for outputting the over driver control signal by receiving the output signal of the second NOR gate and the enable signal as inputs. A method of generating a bit line over driver control signal by receiving an overdriving signal generated by receiving an active command, Generating a first pulse signal having a first pulse width in response to the overdriving signal; Generating the second pulse signal having a second pulse width, which is shorter than the first pulse width, in response to the overdriving signal; Detecting a power supply voltage level; And Selectively outputting the first pulse signal or the second pulse signal as the over driver control signal in response to a detection result of the power supply voltage level; An over-driver control signal generation method of a semiconductor memory device comprising a. The method of claim 8, Detecting the power supply voltage level, Distributing the power supply voltage at a predetermined rate; And comparing the divided voltage and the reference voltage in response to the enable signal.

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