KR100640603B1 - Improved solid state image sensing device and driving method for averaging sub-sampled analog signals - Google Patents

Abstract

An improved solid-state imaging device and its driving method for averaging subsampled analog signals are disclosed. In the solid-state imaging device, when capturing a still image, the individual image signal is inputted to each pixel column in a state where the switch for averaging is turned off, and the digital conversion is performed by the CDS method. Digitally convert the averaged video signal through one of the corresponding CDS circuits.

Description

Improved solid state image sensing device and driving method for averaging sub-sampled analog signals

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram showing a general CIS type solid-state imaging device.

2 is a block diagram showing a CIS type solid-state imaging device according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a pixel structure of the APS array of FIG. 2.

4 is a flowchart for describing an operation of the solid-state imaging device of FIG. 2.

5 is a block diagram illustrating a pixel circuit and an analog averaging circuit.

6 is a timing diagram for describing an operation of a circuit of FIG. 5 in a still image driving mode.

7 is a timing diagram for describing an operation of a circuit of FIG. 5 in a video driving mode.

8 is a view for explaining the light accumulation time of the optical device.

9 is a capacitor model for explaining the analog averaging circuit output in the still image mode.

10 is a capacitor model for explaining the analog averaging circuit output in the video mode.

11 is a view for explaining the output timing of the analog averaging circuit according to the magnitude of the video signal.

FIG. 12 is a detailed block diagram of the digital signal output circuit of FIG. 2.

FIG. 13 is another embodiment of the analog averaging circuit of FIG. 2.

FIG. 14 is a detailed diagram of the CDS circuits of FIG. 13.

FIG. 15 is a timing diagram for describing an operation of the circuit of FIG. 14.

16 is a diagram generalizing the analog averaging circuit of FIG. 13.

FIG. 17 is a detailed diagram of each CDS circuit of FIG. 16.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state image sensing device, and more particularly to a circuit for averaging sub-sampled analog signals required for moving picture implementation of a CMOS image sensor (CIS) type solid state imaging device and the solid state imaging. It relates to a method of driving the device.

There are two types of solid-state imaging devices. That is, it is classified into a CIS type or a Charge-Coupled Device (CCD) type. Compared with CCD type, CIS type has lower voltage operation, lower power consumption, uses standard CMOS (complementary metal-oxide-semiconductor) process, and has advantages in integration. have.

The CIS-type solid-state imaging device is mounted on a mobile phone camera, a digital still camera, or the like, and captures an image developed in a field of view, converts the image into an electrical signal, and transmits it to a digital signal processor. The digital signal processing unit processes color image data (R, G, B data) output from the solid state image pickup device to drive a display device such as a liquid crystal display (LCD). In particular, in a system employing a CIS-type solid-state imaging device, the sub-sampling mode driving of the solid-state imaging device is a mode for outputting an image signal by lowering the vertical resolution. This subsampling mode has a high frame rate in a stage that does not need to be displayed at high resolution, such as a video display step, a preview step for confirming before capturing an image to be captured, or an auto focus setting step. It is carried out for support.

1 is a block diagram showing a general CIS type solid-state imaging device 100. Referring to FIG. 1, a general CIS type solid-state imaging device 100 includes an active pixel sensor (APS) array 110, a row driver 120, and an analog-digital converter (ADC). 130 is provided. The row driver 120 receives a control signal from a row decoder (not shown), and the analog-digital converter 130 receives a control signal from a column decoder (not shown). In addition, the solid-state imaging device 100 includes a control unit (not shown) that generates general timing control signals and addressing signals for outputting selected and sensed image signals of each pixel. Typically, in the case of the color solid-state imaging device 100, a color filter is installed to receive only light of a specific color on each pixel forming the APS array 110. At least three kinds of color filters are used to construct a color signal. Place the color filter. The most common color filter array is Bayer, where the patterns of two colors R (red) and G (green) are arranged in one row, and the patterns of two colors G (green) and B (blue) are arranged in another row. ) Has a pattern. At this time, G (green), which is closely related to the luminance signal, is disposed in every row, and R (red) color and B (blue) color are alternately arranged in each row to increase the luminance resolution. Digital still cameras, etc. are applied to a CIS array of many million pixels or more in order to increase the resolution.

In the CIS type solid-state imaging device 100 having such a pixel structure, the APS array 110 detects light using a photodiode and converts the light into an electrical signal to generate an image signal. The video signal output from the APS array 110 is an analog signal of three colors of red (R), green (G), and blue (B). The analog-digital converter 130 receives an analog image signal output from the pixel array 110 and converts the analog image signal into a digital signal.

In the general CIS type solid-state imaging device 100 as shown in FIG. 1, when converting an image signal detected by an optical device into a digital signal by the analog-digital converter 130, a correlated double sampling (CDS) method is used. Such a driving method is well described in the US patent, "USP5,982,318", or "USP6,067,113". In the analog-to-digital conversion of the CDS method, after receiving the reset signal from the pixel array 110, it is divided into two steps of receiving the image signal sensed by the optical device and converting it into a digital signal. Each time the optical device detects a new light at a predetermined period, the pixel array 110 is reset to the analog-digital conversion unit 130 before the optical device outputs the newly detected image signal to the analog-digital conversion unit 130. Output the signal. The analog-digital converter 130 receives the reset signal and resets it, and then converts the video signal received from the optical device into a digital signal and outputs the digital signal. The digital signal converted as described above is output to the digital signal processor and subjected to a predetermined interpolation process. In addition, the subsequent digital signal processor generates drive signals suitable for the corresponding resolution of the display device such as an LCD, and drives the display device.

 In the conventional CIS type solid-state imaging device as described above, when imaging still images, image signals of all pixels detected by photons of the APS array 110 are output. In the sub-sampling mode, however, the vertical resolution is lowered to output the video signal. For example, in the case of the CIS-type solid-state imaging device 100 having the SXGA (Super Extended Graphics Adapter) resolution, the APS array 110 outputs a video signal at the SXGA level when capturing still images, but displays a video. In a subsampling mode operation such as a preview step, or an auto focus setting step, a video signal is output in a VGA (Video Graphics Adapter) level. For reference, the number of pixels of SXGA resolution is 1280 * 1024 and the number of pixels of VGA resolution is 640 * 480. In addition, even in the case of the CIS type solid-state imaging device 100 having the APS array 110 having UXGA (Ultra Extended Graphics Adapter) resolution, the amount of data that is processed by outputting an image signal at VGA resolution or less in the subsampling mode operation Reduce For reference, the number of pixels of UXGA level resolution is 1600 * 1200.

In the sub-sampling mode of the conventional CIS type solid-state imaging device 100, only the specific row and column image signals spaced at regular intervals for the sub-sampling to the analog-to-digital converter 130 are used. Lower the vertical resolution by outputting. In the above example, in order to lower the SXGA resolution to the VGA resolution, only one data intersecting in one row and one column among pixel data corresponding to two rows and two columns is selected, and the other one is removed, and the resolution 1 / 2 Operate in reduced mode. Similarly, if only data corresponding to one row and one column among the data corresponding to more rows and columns are selected, the resolution can be further reduced, and thus the amount of data processed can be further reduced.

However, in the sub-sampling mode of the conventional CIS-type solid-state imaging device 100, since there is data that is not used and discarded, aliasing appears in a zigzag form without diagonal lines connecting smoothly on the display. ) Cause noise. In order to eliminate such distortion, there is a method of averaging and outputting a range of video signals. That is, before the image signal sensed by the pixel is output to the analog-to-digital converter 130, a method of analogizing the range of image signals is analogized, and the corresponding digital signals output from the analog-to-digital converter 130 There is a way to average it. However, such digital averaging requires a large amount of memory, which increases the chip area and increases the power consumption, which makes it difficult to apply. In addition, in the structure of FIG. 1, in order to analogize the image signal sensed by the pixel, two larger capacitors are required for each of the reset signal and the image signal per column, thereby increasing the chip area. As it is difficult to apply to small mobile applications.

Accordingly, the present invention provides a solid-state imaging device that operates efficiently in a chip area and power consumption by driving a subsampling mode for video by analogizing a video signal output from a pixel without a large capacitor. To provide.

 Another object of the present invention is to provide a subsampling mode driving method of the solid-state imaging device.

A solid-state imaging device according to the present invention for achieving the above technical problem is characterized by comprising an APS (active pixel sensor) array, an averaging circuit, and a digital signal output circuit. In the APS array, pixels are arranged in a two-dimensional matrix, and in the selected row when the subsampling mode is driven, each of the two pixels having one column interval includes a first reset signal, a first image signal, and a second reset signal. And generate and output a second video signal. In the sub-sampling mode driving, the averaging circuit uses a signal reflecting an average of the first reset signal and the second reset signal as an amplifier input signal, and the first image signal and the second video signal in response to the amplifier input signal. To generate a signal corresponding to an average of the difference between the first reset signal and the first video signal and the difference between the second reset signal and the second video signal, and modulate the signal into a pulse width signal. . The digital signal output circuit generates a digital signal having a different digital value according to a logic state variation time point of the pulse width signal. The averaging circuit includes a correlated double sampling (CDS) circuit having a predetermined amplifier and provided in each column; And a switch for shorting the input terminals of the two predetermined amplifiers having one column interval in the sub-sampling mode driving, wherein the amplifier input signal is generated at the shorted input terminals. Only one CDS circuit having any one of the two predetermined amplifiers having a column spacing, and the difference between the first reset signal and the first video signal and between the second reset signal and the second video signal. The pulse width signal is generated by comparing the signal corresponding to the average of the difference with the reference voltage.

The sub-sampling mode drive is a video drive. The switch is opened when driving a still image, and the CDS circuits generate a signal corresponding to a difference between a reset signal and a video signal generated at a corresponding pixel of each column when driving a still image, and is proportional to the magnitude of the signal. And modulating the signal into a signal having a pulse width. The pulse width signal may be proportional to a magnitude of a signal corresponding to an average of a difference between the first reset signal and the first video signal and a difference between the second reset signal and the second video signal.

The APS array generates N reset signals and N image signals of the same color column in each of the N rows selected, and the averaging circuit averages each of the N reset signals and image signals, The difference between the averaged video signal with respect to the averaged reset signal is characterized by modulating the pulse width signal.

The averaging circuit comprises a first switch; In one of the columns of the pixel array, the reset signals and the image signals are received, and corresponding averaged reset signals and averaged image signals are generated by a short circuit of the first switch, and a ramp signal and the averaged image signals are generated. A first CDS circuit for generating a first pulse width signal using a reset signal and the averaged video signal; Receiving the reset signals and the image signals in a same color signal column adjacent to a column to which the first CDS circuit belongs, and generating a corresponding averaged reset signal and an averaged video signal by a short circuit of the first switch, And a second CDS circuit configured to generate a second pulse width signal using the ramp signal, the averaged reset signal, and the averaged video signal, wherein the first switch is shorted in the subsampling mode driving. do.

The APS array may generate and output a third reset signal, a third image signal, a fourth reset signal, and a fourth image signal in each of the other two pixels having one column interval in the subsampling mode. The averaging circuit is configured to reflect the third image signal and the fourth image signal to a corresponding amplifier input signal reflecting an average of the third reset signal and the fourth reset signal, so that the third reset signal and the third image signal are reflected. And generating a signal corresponding to an average of the difference between the difference and the difference between the fourth reset signal and the fourth image signal and generating a pulse width signal corresponding to the signal. The first video signal and the second video signal are first color signals, and the third video signal and the fourth video signal are second color signals. The APS array generates the first video signal and the second video signal corresponding to a second color signal in a next selected row, and the third video signal and the fourth video signal corresponding to a third color signal. It characterized in that to generate. The first color signal, the second color signal, and the third color signal constitute a Bayer pattern.

In accordance with another aspect of the present invention, there is provided a method of driving a solid-state imaging device according to the present invention, in an APS array in which pixels are arranged in a two-dimensional matrix. Generating and outputting a first reset signal and a first image signal, and a second reset signal and a second image signal for each pixel; In the sub-sampling mode driving, the first image signal and the second image signal are reflected in an amplifier input signal reflecting an average of the first reset signal and the second reset signal so that the first reset signal and the first image are reflected. Generating a signal corresponding to a difference between the signal and an average of the difference between the second reset signal and the second video signal, and modulating the signal into a pulse width signal; And generating a digital signal having a different digital value according to a logic state variation time point of the pulse width signal.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a block diagram showing a CIS type solid-state imaging device 200 according to an embodiment of the present invention. 3 is a diagram illustrating a pixel structure of the APS array 210 of FIG. 2. The flowchart of FIG. 4 is referred to for describing the operation of the solid-state imaging device 200 of FIG. 2. The solid-state imaging device 200 includes an active pixel sensor (APS) array 210, a row driver 220, and an analog-to-digital conversion unit 230. do. The analog-to-digital converter 230 includes an analog averaging circuit 231 and a digital signal output circuit 232.

As is well known, the solid-state imaging device 200 in the form of a CMOS image sensor (CIS) mounted on a mobile phone camera, a digital still camera, or the like captures an image deployed in a field of view and converts the image into an electrical signal to convert the image signal into an image signal. Outputs The solid-state imaging device 200 detects external light by using photodiodes (PDs) and converts the external light into an electrical signal to output an image signal. These photons PD are present in each of the pixels arranged in a 2D matrix in the APS array 210.

The solid-state imaging device 200 receives a transfer control signal TG generated from the row driver 220, a reset control signal RG, and a row select signal SEL for selecting a row of the APS array 210. By using the reset signal VRES and the image signal VSIG sensed by the photons PD on the APS array 210 are output. The tricolor signals R, G, and B output from the solid-state imaging device 200 are interpolated by a predetermined image signal processor (not shown), and then output to a display device such as a liquid crystal display (LCD). Is displayed.

On the other hand, the CIS-type solid-state imaging device 200 according to an embodiment of the present invention, in the sub-sampling mode driving to lower the vertical resolution, image signals output from the pixel, without the addition of a large capacitor compared to the conventional method By analogizing the (VSIG), it is possible to generate three-color signals (R, G, B) for distortion-free video.

As shown in FIG. 3, pixels are arranged in a 2D matrix in the APS array 210. The pattern of the color filter disposed on the APS array 210 includes a pattern of two colors of a first color signal G and a second color signal B in one row, and a first color signal G in another row. ) And a third color signal R are assumed to have a Bayer pattern repeatedly arranged. However, the pixel array pattern may be configured in various ways, but is not limited thereto.

Under this assumption, first, a mechanical shutter is opened to accumulate signal charges in the optical device PD provided in the APS array 210 for a predetermined time (S410 of FIG. 4). Substantially, as shown in FIG. 8, the amount of signal charge accumulated in the optical device PD is determined by the transfer control signal TG generated by the row driver 220. While signal charges are accumulated in the photons PD, the APS array 210 generates and outputs a reset signal VRES in response to the reset control signal RG. When driving the still image, the APS array 210 outputs each of the first color signal G and the second color signal B photoelectrically converted from the optical device PD in the odd-numbered rows in columns. In the even-numbered rows, each of the third color signal R and the first color signal G, which are photoelectrically converted from the optical device PD, is output in units of columns. In particular, in the sub-sampling mode driving for moving images, the APS array 210 includes two pixels (for example, odd column pixels) having one column spacing in the selected row and the first reset signal VRES1. The first video signal VSIG1, the second reset signal VRES3, and the second video signal VSIG3 are generated and output (S420 of FIG. 4). In addition, in the same row, each of the other two pixels (for example, even-column pixels) having one column spacing may have a third reset signal VRES2 and a third image signal VSIG2 in the same row. And generate and output the fourth reset signal VRES4 and the fourth video signal VSIG4 (S420 of FIG. 4).

For example, when driving the sub-sampling mode, in FIG. 3, when the row select signal “SEL1” for selecting the first row is activated, the APS array 210 may include pixels of the first column and the third column. The first reset signal VRES1 and the first video signal VSIG1, and the second reset signal VRES3 and the second video signal VSIG3 are generated for the first color signal G, respectively. In addition, the APS array 210 may include a third reset signal VRES2 and a third image signal VSIG2, and a fourth reset signal VRES4 for the second color signal B in each of the pixels of the second column and the fourth column. A fourth video signal VSIG4 is generated. In other columns, the reset and video signals are generated by the same operation. The APS array 210 generates a reset signal and a video signal corresponding to the second color signal B and the third color signal R by the same operation in the second row selected next (FIG. 4, S430).

Hereinafter, when the sub-sampling mode is driven, the row selection signal "SEL1" for selecting the first row is activated, and accordingly, the APS array 210 generates a first in each of the pixels of the first column and the third column. A case where the reset signal VRES1 and the first video signal VSIG1 and the second reset signal VRES3 and the second video signal VSIG3 are generated will be described as an example. As described above, the same operation works for other columns and other rows.

In this case, the analog averaging circuit 231 drives the sub-sampling mode by using only the fifth switch 510 (see FIG. 5) that shorts / opens general CDS circuits without adding a large capacitor. 1 generates a signal corresponding to an average of the difference between the reset signal VRES1 and the first video signal VSIG1 (VRES1-VSIG1) and the difference between the second reset signal VRES3 and the second video signal VSIG3 (VRES3-VSIG3), The signal is modulated into a pulse width signal. The digital signal output circuit 232 generates a digital signal having different digital values according to a logic state change point of the pulse width signal. The analog averaging circuit 231 and the digital signal output circuit 232 are described in more detail below.

5 is a block diagram illustrating the pixel circuits 311 and 312 and the analog averaging circuit 231. 5 shows a circuit 211 for a first column, a circuit 212 for a third column, and a fifth switch 510. FIG. 5 illustrates a case in which the first reset signal VRES1 and the first video signal VSIG1, and the second reset signal VRES3 and the second video signal VSIG3 are generated from the pixels of the first column and the third column as in the above example. For example, although the column circuits 211 and 212 for processing these signals are shown as an example, the column circuits for signals generated in other columns also operate in the same configuration. In particular, the fifth switch 510 is disposed between odd columns and even columns to drive a subsampling mode for moving images.

The circuit 211 for the first column includes a first pixel circuit 311 to be selected in the first column, a predetermined current source 312 connected to all pixel circuits in the first column, and the first pixel circuit 311. And a first correlated double sampling (CDS) circuit 313 for processing the first reset signal VRES1 and the first video signal VSIG1 outputted from the < RTI ID = 0.0 > The circuit 212 for the third column includes a second pixel circuit 321 to be selected in the third column, a predetermined current source 322 connected to all pixel circuits of the third column, and the second pixel circuit 321. A second CDS circuit 323 for processing the second reset signal VRES3 and the second video signal VSIG3 outputted from the < RTI ID = 0.0 > Here, the current sources 312 and 322 are provided at the end of each column for all pixel circuits of each column. In particular, the CDS circuits 313 and 323 and the fifth switch 510 are the averaging circuit 231. Is provided. The timing diagram of FIG. 6 is referred to for describing operation in the still image driving mode of the circuit of FIG. 5. The timing diagram of FIG. 7 is referred to for describing the operation in the video driving mode of the circuit of FIG. 5.

As is well known, the pixel circuits 311/321 of the APS array 210, in the row selected by the row select signal SEL, respond to the transfer control signal TG in the optical device PD1 / PD2. The photoelectrically converted video signals VSIG1 / VSIG3 are outputted from the photo signal, and the reset signals VRES / VRES3 are generated and output in response to the reset control signal RG. For example, the first pixel circuit 311 includes four metal-oxide-semiconductor field effect transistors (MMOS) M1 to M4, and one optical device PD1. When the row select signal SEL is activated in a logic high state, the voltage of the node FD1 transmitted from the power supply VDD in response to the reset control signal RG serves as a source follower. It is output through the source terminal of. The voltage of the node FD1 output to the source terminal of M3 is output to the first CDS circuit 313 as a reset signal VRES1 through the source terminal of M1. On the other hand, when the transfer control signal TG is activated in a logic high state, the reset control signal RG is in a logic low state, and in this case, the image signal VSIG1 photoelectrically converted from the optical element PD1. Is output to the first CDS circuit 313 through the source terminal of M1. Similarly, the second reset signal VRES3 and the second video signal VSIG3 are output to the second CDS circuit 323 by the second pixel circuit 321 which performs the same operation.

First, operations of the CDS circuits 313 and 323 when driving still images will be described. The CDS circuits 313 and 323 of the analog averaging circuit 231 receive the reset signal VRES1 / VRES3 and the image signal VSIG1 / VSIG3 in sequence, and the reset signal VRES1 / VRES3 and the image signal The signal corresponding to the difference between the VSIG1 / VSIG3 is the amplifier input signal VIN1, and then compared with the reference voltage VREF to output a signal VCD1 / VCD2 having a different pulse width according to the comparison result. . For example, the first CDS circuit 313 may include a first switch 401, a second switch 402, a third switch 403, a fourth switch 404, a first capacitor 405, and a second capacitor. 406, a third capacitor 407, a first amplifier 408, and a second amplifier 409. During still image driving, as shown in FIG. 6, the fifth switch 510 under the inactive state control of the S5 signal is in an open state. First, in a state where the first switch 401, the second switch 402, the third switch 403, and the fourth switch 404 which are subjected to signal control of S1, S2, S31, and S4 are shorted, The first reset signal VRES1 is input, and at this time, the voltage Vth1 of FIG. 9 is generated at the input terminal node IN1 of the first amplifier 408. Next, when the photoelectrically converted image signal VSIG1 is input from the optical device PD1 in response to the transfer control signal TG, the voltage X1 of FIG. 9 is generated at the input terminal node IN1 of the first amplifier 408. do. FIG. 9 is a capacitor model for the case where the first reset signal VRES1 is input (left) and after that the first image signal VSIG1 is input (right). 9, [Equation 1] to [Equation 6] is established. Here, C0 is the capacitance of the second capacitor 406, Cin is the capacitance of the input terminal node IN1 of the first amplifier 408, Q1 and Q3 are the first reset signal VRES1 is input (left) and thereafter The amount of charges of the second capacitor 405, Q2 and Q4, when the first image signal VSIG1 is input (right) is input when the first reset signal VRES1 is input (left) and then the first image signal ( The amount of charge at the input terminal node IN1 of the first amplifier 408 for the case where VSIG1) is input (right). If C0 is sufficiently larger than Cin in [Equation 6], it is approximated as shown in [Equation 7].

[Equation 1]

Q2-Q1 = Q4-Q3

[Equation 2]

X1 = Q4 / Cin

[Equation 3]

Q1 = (VRES1-Vth1) * C0

[Equation 4]

Q2 = Vth1 * Cin

[Equation 5]

Q3 = (VSIG1-X) * C0

[Equation 6]

X = Vth1-(VRES1-VSIG1) * {C0 / (C0 + Cin)}

[Equation 7]

X = Vth1-(VRES1-VSIG1)

Accordingly, as shown in FIG. 6, when the VRAMP signal is gradually raised, the signal of the IN1 node corresponding to the difference between the first reset signal VRES1 and the first video signal VSIG1 also increases with the VRAMP signal, and the first amplifier ( The 408 compares the increasing signal with the reference voltage VREF and outputs a signal VOUT1 having a different pulse width according to the comparison result. The second amplifier 409 receives and buffers the above signal transmitted through the third capacitor 407 to output the first pulse width signal VCD1. Similarly, the second CDS circuit 323 having the same operation receives the second reset signal VRES3 and the second image signal VSIG3 and outputs a second pulse width signal VCD2.

Next, in the sub-sampling mode driving for driving the video, as shown in FIG. The third switch 503 provided in the second CDS circuit 323 is in an open state. That is, in the subsampling mode driving, the first amplifier 508 and the second amplifier 509 included in the second CDS circuit 323 do not operate, except that the first CDS circuit 323 is provided with the first amplifier. The input terminal node IN2 of the amplifier 508 is shorted to the input terminal node IN1 of the first amplifier 408 of the first CDS circuit 313. That is, the input terminals IN1 and IN2 of the two amplifiers 408 and 508 having one column spacing are shorted, and in this state, the second CDS circuit 323 outputs the normal second pulse width signal VCD2. Instead, only the first CDS circuit 313 normally outputs the first pulse width signal VCD1.

Hereinafter, in driving the sub-sampling mode for driving the video, when the input terminals IN1 and IN2 of the amplifiers 408 and 508 are shorted by the fifth switch 510, averaging of video signals of two columns is performed. Explain how is done.

First, when the switches 401 and 501 of the CDS circuits 313 and 323 are shorted, the amplifiers 408 by the reset signals VRES1 and VRES3 input from the pixel circuits 311 and 321. Signals reflecting an average of the first reset signal VRES1 and the second reset signal VRES3 are generated at the input terminals IN1 and IN2 of the second and second generations 508 and 508. At this time, the voltage of the signal reflecting the average of the first reset signal VRES1 and the second reset signal VRES3 is Vth2 of FIG. 10, and then the photons PD1 in response to the transfer control signal TG. When the image signals VSIG1 and VSIG3 photoelectrically converted from the PD2 are input to the CDS circuits 313 and 323, the voltage X2 of FIG. 10 is generated at the input terminal node IN1 of the first amplifier 408. That is, the first image signal VSIG1 and the second image signal VSIG3 are again applied to an amplifier input signal voltage Vth2 reflecting an average of the first reset signal VRES1 and the second reset signal VRES3. By reflecting, the voltage X2 becomes the voltage of the input terminal node IN1 of the first amplifier 408. FIG. 10 is a capacitor model for the case where the reset signals VRES1 and VRES3 are input (left) and after that the image signals VSIG1 and VSIG3 are input (right). Referring to FIG. 10, Equations 8 to 14 are established. Where C0 is the capacitance of the capacitors 405, 406, 505, 506, Cin is the capacitance of the input nodes IN1, IN2 of the amplifiers 408, 508, Q11 and Q31 are the reset signals VRES1, VRES3. ), The charge amount of the capacitor 406, Q12 and Q32 for the case where the input signal is input (left) and then the image signals VSIG1 and VSIG3 are input (right), and the reset signals VRES1 and VRES3 are input. The amount of charge of the capacitor 506, Q2, and Q4 for the case (left) and then the image signals VSIG1 and VSIG3 are input (right), when the reset signals VRES1 and VRES3 are input (left) And the charge amount of the input node IN1 of the first amplifier 408 for the case where the image signals VSIG1 and VSIG3 are input (right). If C0 is sufficiently larger than Cin in [Equation 14], it is approximated as in [Equation 15].

[Equation 8]

Q2-(Q11-Q12) = Q4-(Q31 + Q32)

[Equation 9]

Q11 = (VRES1-Vth2) * C0

[Equation 10]

Q12 = (VRES3-Vth2) * C0

[Equation 11]

Q2 = Vth2 * Cin

[Equation 12]

Q31 = (VSIG1-X2) * C0

[Equation 13]

Q32 = (VSIG3-X2) * C0

[Equation 14]

X2 = Q4 / Cin

[Equation 15]

X2 = Vth2-{(VRES1-VSIG1) + (VRES3-VSIG3)} * {C0 / (2 * C0 + Cin)}

[Equation 16]

X2 = Vth2-{(VRES1-VSIG1) + (VRES3-VSIG3)} / 2

As such, the first image signal VSIG1 and the second image signal VSIG3 are applied to an amplifier input signal voltage Vth2 reflecting an average of the first reset signal VRES1 and the second reset signal VRES3. By reflecting again, the difference between the first reset signal VRES1 and the first video signal VSIG1 (VRES1-VSIG1) and the difference between the second reset signal VRES3 and the second video signal (VRES3-VSIG3) An average " {(VRES1-VSIG1) + (VRES3-VSIG3)} / 2 " is generated, so that the first amplifier 408 of the first CDS circuit 313 has an IN1 node (corresponding to the average). Or the X2 signal of the IN2 node) into a pulse width signal. When an X2 signal is generated at the input node IN1 of the first amplifier 408, as shown in FIG. 7, the VRAMP signal is enabled to gradually rise, and as shown in FIG. 11, the first amplifier 408 is in accordance with the VRAMP signal. The signal VIN1 of the increasing IN1 node is compared with the reference voltage VREF, and a signal VOUT1 having a different pulse width is output according to the comparison result. The second amplifier 409 receives and buffers the VOUT1 signal transmitted through the third capacitor 407 to output the first pulse width signal VCD1. The pulse width of the first pulse width signal VCD1 may be a difference between the first reset signal VRES1 and the first image signal VSIG1, and the second reset signal VRES3 and the second image signal VSIG3. Is proportional to the magnitude of the X2 signal corresponding to the mean for the difference. As described above, the amplifiers 508 and 509 of the second CDS circuit 323 do not operate normally when moving video.

12 is a detailed block diagram of the digital signal output circuit 232 of FIG. 2. Referring to FIG. 12, the digital signal output circuit 232 includes a counter 241 and a latch circuit 242. The counter 241 starts counting when the ramp signal VRAMP rises and outputs a count value corresponding to the time when the logic state of the second amplifier output VCD1 is changed to the latch circuit 242. The latch circuit 242 stores and outputs the corresponding digital value received from the counter 241.

As described above, in the CIS-type solid-state imaging device 200 according to an embodiment of the present invention, when the still image is captured, the switch 510 for averaging the CDS analog-to-digital conversion unit 230 is turned off. In this state, the individual image signals are input and digitally converted for each pixel column, and when the video is captured, a pair of pairs in the analog-to-digital conversion unit 230 convert the averaged video signals of the image signals of the same color column by the on switch 510. The digital conversion is performed by inputting from one of the CDS circuits. By applying this, it is possible to easily realize a subsampling mode for vertical resolution reduction such as 1/2, 1/3, 1/4, and the like.

FIG. 13 is another embodiment illustrating the analog averaging circuit 231 of FIG. 2. In this case, the sub-sampling mode driving for 1/2 resolution reduction will be described as an example. That is, in the sub-sampling mode, the analog averaging circuit 231 of FIG. 13 performs the odd-numbered and even-numbered two in the column and row units of the reset signal VRES and the video signal VSIG, respectively. Average Referring to FIG. 13, the analog averaging circuit 231 includes a first switch 235, a first CDS circuit 236, and a second CDS circuit 237. The first CDS circuit 236 performs reset signals (eg, VR1R1 and VR3R1 in the first and third rows) in any one column (eg, the first column) of the APS array 210. And a first pulse width signal (eg, VCD1) from the image signals (eg, VR1S1 and VR3S1 in the first and third rows).

The second CDS circuit 237 may include reset signals (eg, first and third) in a same color signal column (eg, a third column) adjacent to a column to which the first CDS circuit 236 belongs. A second pulse width signal (eg, VCD3) is generated from VR1R3 and VR3R3 in the row and the image signals (eg, VR1S3 and VR3S3 in the first and third rows).

The first switch 235 is shorted when driving the sub-sampling mode for averaging and opened when driving the video mode. In the sub-sampling mode driving, the reset signals and the image signals inputted are averaged by a short circuit of the first switch 235, and in any one of the first CDS circuit 236 and the second CDS circuit 237. Normally, the pulse width signals VCD1 / VCD2 are generated. Shorting and opening of the first switch 235 are controlled by a control signal SAVG generated by a controller (not shown).

FIG. 14 is a detailed view of the CDS circuits 236 and 237 of FIG. Referring to FIG. 14, the first CDS circuit 236 may include a second switch 251, a third switch 252, a first image signal averaging unit 253, a first reset signal averaging unit 257, and a first switch. A first comparator 261, a first capacitor 264, and a first amplifier 265 are provided. The second CDS circuit 237 has a symmetrical structure with the first CDS circuit 236, and includes a fourth switch 351, a fifth switch 352, a second image signal averaging unit 353, and a second A reset signal averaging unit 357, a second comparator 361, a second capacitor 364, and a second amplifier 365 are provided.

When the second switch 251 is shorted by a control signal S1 generated by a controller (not shown), the reset signals from the APS array 210 (for example, VR1R1 and VR3R1 in odd rows) and the Image signals (eg, VR1S1 and VR3S1 in odd rows) are transmitted. When the third switch 252 is shorted by the control signal S2 generated by a controller (not shown), the third switch 252 transfers the ramp signal VRAMP. The first video signal averaging unit 253 performs the odd-numbered and even-numbered two video signals transmitted by the second switch 251 by the short circuit of the first switch 235. Average them. The first reset signal averaging unit 257 has two odd and even second reset signals in units of columns and rows transmitted from the second switch 251 by a short circuit of the first switch 235. Average them. When the difference voltage of the averaged video signal with respect to the averaged reset signal is increased in accordance with the ramp signal VRAMP at the IN1 node, the first comparator 261 receives the IN1 node voltage VIN1 and the reference voltage. VREF) is compared and a signal having a different pulse width is output according to the comparison result. The first capacitor 264 receives the output of the first comparator 261 at one end and transfers the output to the other end. The first amplifier 265 buffers and stabilizes the signal transmitted through the first capacitor 264 and outputs the first pulse width signal VCD1.

The fourth switch 351, the fifth switch 352, the second image signal averaging unit 353, the second reset signal averaging unit 357, and the second comparison unit 361 of the second CDS circuit 237. The operation of each of the second capacitor 364 and the second amplifier 365 is performed by the second switch 251, the third switch 252, and the first image signal averaging unit of the first CDS circuit 236. 253, the first reset signal averaging unit 257, the first comparator 261, the first capacitor 264, and the first amplifier 265, and thus description thereof will be omitted. The second CDS circuit 237 outputs a second pulse width signal VCD3 in the same manner as the first CDS circuit 236.

FIG. 15 is a timing diagram for describing the circuit operation of FIG. 14. The operation of the CDS circuits 236 and 237 of FIG. 14 will be described in more detail with reference to FIG. 15. In FIG. 14, capacitances CS1, CS2, CS3, and CS4 of the capacitors 254, 255, 354, and 355 constituting the first image signal averaging unit 253 and the second image signal averaging unit 263 are represented by FIG. Assume all are the same. In addition, the capacitances CR1, CR2, CR3, and CR4 of the capacitors 259, 260, 359, and 360 constituting the first reset signal averaging unit 257 and the second reset signal averaging unit 267 are the same. Assume In FIG. 6, VR1R1 and VR3R1 are reset signals of any one column (eg, the first column) of two adjacent odd rows (eg, the first row and the third row), and VR1S1 and VR3S1 are the reset signals. It is an image signal of any one column (e.g., the first column) of neighboring two odd rows (e.g., the first row and the third row). In addition, VR1R3 and VR3R3 are reset signals of a column (eg, third column) neighboring the VR1R1 and VR3R1 generation columns of neighboring two-hole performances (eg, first row and third row), and VR1S3. VR3S3 is an image signal of a column (eg, a third column) neighboring the VR1R1 and VR3R1 generation columns of two adjacent odd rows (eg, the first row and the third row). In FIG. 14, signals S1, S2, S31, S32, S4, SSIG, and the signals that control the switches 251, 252, 262, 266, 256, 258, or 351, 352, 362, 366, 356, 358, and SRES is generated in a predetermined controller (not shown), and when the switches are activated from the first logic state (logical low state) to the second logic state (logical high state) as shown in FIG. 15, the switches 251, 252, 262, Suppose 266, 256, 258, or 351, 352, 362, 366, 356, 358 are shorted.

Under this assumption, the section 1 of FIG. 15 is a section for sampling the reset signals VR1R1 and VR1R3 of the first row when the first switch 235 is short-circuited, wherein the switches 251 and 252 , 262, 266, 256, 258, or 351, 352, 362, 366, 356, and 358 are all shorted, and the reset signals VR1R1 and VR1R3 of the first row are averaged, as shown in Equation 17. The relationship is established. In Equation 17, Q is a corresponding charge amount, and C _R1,2,3,4 represents CR1, CR2, CR3, or CR4.

[Equation 17]

The section 2 of FIG. 15 is a section for sampling the video signals VR1S1 and VR1S3 of the first row, and the switches 262, 266, 362, and 366 controlled by S31 and S4 are opened, and the first The video signals VR1S1 and VR1S3 in the row are averaged, and a relationship as shown in Equation 18 is established. In Equation 18, Q is a corresponding charge amount, and C _S1,2,3,4 represents CS1, CS2, CS3, or CS4.

Equation 18

Section 3 of FIG. 15 is a section for sampling the reset signals VR3R1 and VR3R3 of the third row, and the switches 256, 258, 356, and 358 controlled by SSIG and SRES are opened, and the third row is displayed. The reset signals VR3R1 and VR3R3 are averaged, and the relationship as shown in Equation 19 is established. In Equation 19, Q is a corresponding charge amount, and C _R2,4 represents CR2 or CR4.

[Equation 19]

The section 4 of FIG. 15 is a section for sampling the video signals VR3S1 and VR3S3 of the third row, and the switches 256, 258, 262, 266, 356, and 358 controlled by SSIG, SRES, S31, and S4. , 362 and 366 are opened, and the image signals VR3S1 and VR3S3 in the third row are averaged, and a relationship as shown in Equation 20 is established. In Equation 20, Q is a corresponding charge amount, and C _S2,4 represents CS2 or CS4.

[Equation 20]

The section 5 of FIG. 15 is a section averaging four video signals VR1S1, VR1S3, VR3S1, and VR3S3 in the first row and the third row, and is controlled by the switches 256, 258, and SSIG. 356, 358), and the relationship as shown in [Equation 21] and [Equation 22] is established.

[Equation 21]

[Equation 22]

Referring to FIG. 11, the first comparator 261 and the second comparator 271 of the CDS circuits 236 and 237 may perform the averaged video signal with respect to the averaged reset signal (Equation 21). When the difference voltage VIN1 of Equation 22 is increased according to the ramp signal VRAMP, the voltage VIN1 of the increased IN1 node is different from each other when the voltage VIN1 is greater than or less than the reference voltage VREF. The first pulse width signal VCD1 having a logic state is generated. In the sub-sampling mode during video driving, the switch 362 controlled by the control signal S32 is opened, and the second comparator 361 and the second amplifier 365 do not operate normally.

Accordingly, when the ramp signal VRAMP rises, the counter 241 of FIG. 12 starts counting and a digital value corresponding to a count value corresponding to a time when a logic state of the comparison signal VCD is changed. Is output to the latch circuit 242, and the latch circuit 242 stores a digital value received from the counter 241, and stores the digital value for the averaged reset signal (Equation 21). It can be generated and output as a digital signal corresponding to the difference of the averaged video signal (Equation 22).

Although the sub-sampling mode driving for reducing the resolution of the circuit of FIG. 14 has been described as an example, in the still image mode, the first switch 235 is opened, whereby the image signals detected by the photons of the APS array 210 are stored. Without being averaged, both of the CDS circuits 236 and 237 generate separate normal first pulse width signal CDS1 and second pulse width signal CDS2.

In order to drive the subsampling mode for reducing the 1 / N resolution, the analog averaging circuit 231 of FIG. 13 is changed as shown in FIG. 16. 16 is a diagram generalizing the analog averaging circuit 231 of FIG. Referring to FIG. 16, the analog averaging circuit 231 may average the odd-numbered N and even-numbered reset signals VRES and image signals VSIG in column and row units in the subsampling mode. N CDS circuits 280 in each column that perform the same operations as the CDS circuits 236/237 of FIG. 13 should be connected by a switch 290 controlled by the SAVG signal.

FIG. 17 is a detailed view of the CDS circuit 290 of each of FIG. 16. Referring to FIG. 17, the CDS circuit 290 of FIG. 16 has the same structure as that of FIG. 14, and includes a sixth switch 291, a seventh switch 292, a third image signal averaging unit 293, and a third structure. A reset signal averaging unit 302, a third comparator 311, a third capacitor 314, and a third amplifier 315 are provided. The operation of such circuits is almost the same as the operation of the circuit of FIG. However, each of the third image signal averaging unit 293 and the third reset signal averaging unit 302 includes N capacitors 297 to 301 for storing the reset signal VRES and the video signal VSIG of each row. 306-310). Just before the ramp signal VRAMP rises, such capacitors 297 to 301 and 306 to 310 are all shorted by the switches 294 to 296 and 303 to 305, so that N * N reset signals ( VRES) and the video signal VSIG are averaged. Those skilled in the art can fully understand the circuit operation of FIG. 17 according to the description of FIG. 14, and thus, detailed description of FIG. 17 will be omitted.

On the other hand, the analog-to-digital converter 230 digitally converts the analog signal corresponding to the difference between the averaged video signal (Equation 22) with respect to the averaged reset signal (Equation 21). As a result of converting the signal into a signal, the following predetermined image signal processor performs a predetermined interpolation process and outputs the same to a display device such as an LCD.

As described above, the CIS-type solid-state imaging device 200 according to another exemplary embodiment of the present invention may include photoelectric conversion of the image signals VSIG of all the pixels of the APS array 210 when the sub-sampling mode is driven. In order to avoid discarding the video signal, an analog averaging circuit 231 outputs a video signal obtained by averaging the video signals in the row and column directions from the N rows. The signal VCD output from the analog averaging circuit 231 is input to the digital signal output circuit 232, converted into a digital signal, and output.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, in the CIS-type solid-state imaging device 200 according to the present invention, the sub-sampling mode for video can be driven by analogizing the video signals output from the pixels without a large capacitor. By this function, the driving frequency of the CDS can be lowered and a high frame rate can be ensured when the moving image is captured. In addition, it is possible to make it possible to capture a still image at high resolution and to capture a moving image at low power consumption.

In addition, when driving the sub-sampling mode, the video signals of all rows and columns are used without any video signals that are not output and are discarded. Therefore, the signal size is increased to improve the dynamic range of the output signal and to suppress zigzag noise appearing on the display. As a result, the display quality can be improved when applied to mobile application systems such as mobile phone cameras or digital still cameras. In addition, since the analog averaging method is applied, there is an effect of not increasing the chip size without using a memory.

Claims (28)

The pixels are arranged in a two-dimensional matrix, and in the selected row when the subsampling mode is driven, each of the two pixels having a column spacing is the first reset signal and the first image signal, and the second reset signal and the second image. An active pixel sensor (APS) array for generating and outputting a signal; In the sub-sampling mode driving, a signal reflecting an average of the first reset signal and the second reset signal is used as an amplifier input signal, and the first input signal and the second video signal are reflected in the amplifier input signal. An averaging circuit generating a signal corresponding to an average of a difference between a first reset signal and the first video signal and a difference between the second reset signal and the second video signal and modulating the signal into a pulse width signal; And A digital signal output circuit for generating a digital signal having a different digital value according to a logic state variation time point of the pulse width signal, The averaging circuit, Correlated double sampling (CDS) circuits each having a predetermined amplifier and provided in each column; And In the sub-sampling mode driving, a switch for shorting the input terminals of the two predetermined amplifiers having one column spacing, And said amplifier input signal is generated at said shorted input stages. delete The method of claim 1, wherein the CDS circuits provided in each column, 2 pairs each, Only one CDS circuit of the pair of CDS circuits, The pulse width signal is generated by comparing a reference voltage with a signal corresponding to an average of the difference between the first reset signal and the first image signal and the difference between the second reset signal and the second image signal. Solid-state image sensor made into. The method of claim 1, wherein the subsampling mode driving is performed. A solid-state imaging device, characterized in that the video drive. The method of claim 4, wherein the switch, When the still image is driven, the CDS circuits generate a signal corresponding to the difference between the reset signal and the image signal generated in the corresponding pixel of each column during the still image driving, and generate a pulse width proportional to the magnitude of the signal. A solid-state imaging device, characterized in that the modulated to the signal to output. The method of claim 1, wherein the APS array, Generate N reset signals and N image signals of the same color column in each of a plurality of selected N rows; The averaging circuit, And averaging each of the N reset signals and the image signals, and modulating a difference in the averaged image signal with respect to the averaged reset signal into a pulse width signal. The method of claim 6, wherein the averaging circuit, A first switch; In one of the columns of the pixel array, the reset signals and the image signals are received, and corresponding averaged reset signals and averaged image signals are generated by a short circuit of the first switch, and a ramp signal and the averaged image signals are generated. A first CDS circuit for generating a first pulse width signal using a reset signal and the averaged video signal; And Receiving the reset signals and the image signals in the same color signal column adjacent to the column to which the first CDS circuit belongs, and generating a corresponding averaged reset signal and an averaged image signal by a short circuit of the first switch, and A second CDS circuit for generating a second pulse width signal using the ramp signal, the averaged reset signal, and the averaged video signal; And said first switch is short-circuited in said subsampling mode driving. The method of claim 7, wherein each of the first CDS circuit and the second CDS circuit, A second switch transferring the reset signal and the video signal when a short circuit occurs; A third switch transferring the lamp signal in a short circuit; An image signal averaging unit for averaging the image signals transmitted from the second switch by a short circuit of the first switch; A reset signal averaging unit for averaging reset signals transmitted from the second switch by a short circuit of the first switch; And When the difference voltage of the averaged video signal with respect to the averaged reset signal is increased in accordance with the ramp signal, the pulse width signal having a different logic state in each case where the increased voltage is greater than or less than a reference voltage is obtained. A solid-state imaging device comprising a comparison unit to generate. The method of claim 8, wherein each of the first CDS circuit and the second CDS circuit, A capacitor receiving the pulse width signal at one end and transferring the pulse width signal to the other end; And And an amplifier configured to buffer and output the comparison signal transmitted through the capacitor. The method of claim 1, wherein the pulse width signal, And a magnitude of a signal corresponding to an average of a difference between the first reset signal and the first image signal and a difference between the second reset signal and the second image signal. The method of claim 1, wherein the APS array, In the sub-sampling mode, each of the other two pixels having one column interval generates and outputs a third reset signal, a third video signal, a fourth reset signal, and a fourth video signal, The averaging circuit, The difference between the third reset signal and the third image signal is reflected by reflecting the third image signal and the fourth image signal to a corresponding amplifier input signal reflecting an average of the third reset signal and the fourth reset signal. And generating a pulse width signal corresponding to the average of the difference between the reset signal and the fourth video signal. The method of claim 11, wherein the first video signal and the second video signal, And a third color signal and a fourth color signal are second color signals. The method of claim 12, wherein the APS array, In the next selected row, the first video signal and the second video signal corresponding to the second color signal are generated, and the third video signal and the fourth video signal corresponding to the third color signal are generated. Solid-state image sensor made into. The method of claim 13, wherein the first color signal, the second color signal, and the third color signal, A solid-state imaging device comprising a Bayer pattern. In an APS array in which pixels are arranged in a two-dimensional matrix, in a row selected when driving a subsampling mode, each of two pixels having a column spacing includes a first reset signal, a first image signal, and a second reset signal. Generating and outputting a second video signal; In the sub-sampling mode driving, the first image signal and the second image signal are reflected in an amplifier input signal reflecting an average of the first reset signal and the second reset signal so that the first reset signal and the first image are reflected. Generating a signal corresponding to a difference between the signal and an average of the difference between the second reset signal and the second video signal, and modulating the signal into a pulse width signal; And Generating a digital signal having a different digital value according to a logic state variation time point of the pulse width signal, In the sub-sampling mode driving, the input terminals of the two predetermined amplifiers having each predetermined amplifier and having one column spacing among the predetermined amplifiers provided in the CDS circuits provided in each column are shorted, so that the shorted input terminals are shorted. And generating the amplifier input signal in a solid state image pickup device. delete The method of claim 15, wherein the CDS circuits provided in each column, 2 pairs each, Only one CDS circuit of the pair of CDS circuits, The pulse width signal is generated by comparing a reference voltage with a signal corresponding to an average of the difference between the first reset signal and the first image signal and the difference between the second reset signal and the second image signal. A solid-state image sensor drive method. The method of claim 15, wherein the sub-sampling mode driving, A solid-state imaging device driving method characterized in that the video drive. 19. The method of claim 18, wherein the input ends of the two predetermined amplifiers having a column spacing, When the still image is driven, the CDS circuits generate a signal corresponding to the difference between the reset signal and the image signal generated in the corresponding pixel of each column during the still image driving, and generate a pulse width proportional to the magnitude of the signal. And modulating the signal into a signal and outputting the modulated signal. The method of claim 15, wherein the solid-state image sensor driving method, Generating N reset signals and N image signals of the same color column in each of the N rows selected from the APS array; And And averaging each of the N reset signals and the image signals, and modulating a difference of the averaged image signal with respect to the averaged reset signal into a pulse width signal. The method of claim 20, wherein the averaging step, Receiving the reset signals and the image signals in one column of the pixel array and generating corresponding averaged reset signals and averaged image signals by a short circuit of a predetermined switch; And Receiving the reset signals and the image signals in the same color signal column adjacent to the column, and generating a corresponding averaged reset signal and an averaged image signal by a short circuit of the predetermined switch, And said predetermined switch is short-circuited in said subsampling mode driving. The method of claim 21, wherein the pulse width signal generating step, Increasing a difference voltage of the averaged video signal with respect to the averaged reset signal according to a ramp signal; And wherein the pulse width signal has a different logic state in each case where the increased voltage is greater than or less than a reference voltage. The method of claim 22, wherein generating the pulse width signal, Receiving the pulse width signal at one end of the capacitor and transferring the pulse width signal to the other end of the capacitor; And And buffering and outputting the pulse width signal transmitted through the capacitor. The method of claim 15, wherein the pulse width signal, And a magnitude of a signal corresponding to an average of a difference between the first reset signal and the first image signal and a difference between the second reset signal and the second image signal. The method of claim 15, wherein the solid-state image sensor driving method, In the sub-sampling mode, generating and outputting a third reset signal, a third image signal, a fourth reset signal, and a fourth image signal by each of the other two pixels having one column interval in the APS array; And The difference between the third reset signal and the third image signal is reflected by reflecting the third image signal and the fourth image signal to a corresponding amplifier input signal reflecting an average of the third reset signal and the fourth reset signal. And generating a pulse width signal corresponding to the average of the difference between the reset signal and the fourth image signal, and generating a pulse width signal corresponding to the signal. The method of claim 25, wherein the first video signal and the second video signal, And the third image signal and the fourth image signal are second color signals. 27. The method of claim 26, wherein in the next selected row of the APS array, the first video signal and the second video signal corresponding to a second color signal are generated, and the third video signal corresponding to a third color signal and And generating the fourth image signal. The method of claim 27, wherein the first color signal, the second color signal, and the third color signal, A solid-state imaging device driving method comprising a Bayer pattern.

Images