JP2005333522A - Solid-state image pickup device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state image pickup device capable of reducing the amplitude of an image signal which is outputted when photoelectric conversion portions of horizontally adjacent pixels are coupled. <P>SOLUTION: Horizontally adjacent pixels G11, G21 are defined as one group unit, a MOS transistor T7 of the pixel G21 is turned off and a MOS transistor T9 is turned on, so that photo-diodes PD of the pixels G11, G21 can be coupled. At such a time, the pixel G21 operates as an invalid pixel but the voltage value of a signal ϕVRS applied to MOS transistors T6, T8 of the pixel G21 is made lower than a DC voltage VRS, thereby reducing the amplitude of an image signal comprised of outputs of valid and invalid pixels. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device including a plurality of pixels, and more particularly to a solid-state imaging device capable of changing sensitivity and resolution according to a subject and an imaging operation.

  Conventionally, in a solid-state imaging device that performs a linear conversion operation that linearly converts the amount of incident light, its dynamic range is as narrow as two orders of magnitude, so when imaging a subject that constitutes a luminance distribution in a wide luminance range, other than the dynamic range The luminance information in the range is not output. Further, as a conventional solid-state imaging device, there is one that performs a logarithmic conversion operation for logarithmically converting the amount of incident light (see Patent Document 1). In this solid-state imaging device, the dynamic range is as wide as 5 to 6 digits. Therefore, even if an image of a subject constituting a luminance distribution in a slightly wide luminance range is captured, all luminance information in the luminance distribution is converted into an electrical signal. Can be output. However, since the imageable area becomes wider with respect to the luminance distribution of the subject, an area without luminance data is formed in the low luminance area or the high luminance area in the imageable area. On the other hand, the present applicant has proposed what can switch between the above-described linear conversion operation and logarithmic conversion operation (see Patent Document 2).

  When realizing a high frame rate in a solid-state imaging device including these solid-state imaging elements, if the number of pixels included in the solid-state imaging element is large, it is necessary to increase the frequency of a pulse signal for operating the solid-state imaging element. . When driven by a high-frequency pulse signal in this way, the power consumption increases. In addition, since the operation time of one cycle is shortened, the exposure time is also shortened, so that a sufficient exposure amount cannot be obtained in each pixel, and the signal level obtained from the solid-state imaging device is lowered. Therefore, an image captured by such a solid-state imaging device becomes an image with low contrast. Therefore, conventionally, the frequency of the driving pulse signal is lowered by setting the pixels to be operated and the pixels not to be operated for each line and performing thinning scanning.

In addition, as a conventional technique, a solid-state imaging device capable of performing high-sensitivity imaging by coupling a photoelectric conversion portion including a photodiode and a capacitor formed in each pixel adjacent in the vertical direction is proposed. (See Patent Document 3). In this solid-state imaging device, a MOS transistor serving as one output stage is provided for every two rows, and a switch for electrically connecting / disconnecting the MOS transistor serving as the output stage to the connection node of the photodiode and the capacitor Provided for each pixel.
JP-A-11-313257 JP 2002-77733 A Japanese Patent Laid-Open No. 9-46596

  However, according to such thinning scanning, since there are pixels that are not operated, fewer photoelectric conversion elements are used, so the solid-state imaging element used in this solid-state imaging device is equivalent to a solid-state imaging element with a low aperture ratio. And the sensitivity becomes low. Further, according to the solid-state imaging device disclosed in Patent Document 3, since pixel combination is performed only in the vertical direction, it is not possible to perform flexible sensitivity switching with respect to the resolution in the vertical direction and the horizontal direction. In addition, since there is one MOS transistor as an output stage for every two rows, when reading out an electrical signal from all pixels, this output stage is common to two vertically adjacent pixels, so that the control operation Becomes complicated.

  On the other hand, when combining the photoelectric conversion portions of pixels adjacent in the horizontal direction as compared with the case of combining in the vertical direction as in Patent Document 3, the effective pixel that outputs the image signal and the invalid pixel that does not output the image signal Are arranged every other pixel. Further, when the solid-state imaging device outputs an image signal for one frame, horizontal synchronization for a plurality of cycles as shown in FIG. 21 (b) with respect to a vertical synchronization signal for one cycle as shown in FIG. 21 (a). A signal is output. In accordance with the period of one cycle of the horizontal synchronizing signal as shown in FIG. 21B, an image signal is output from pixels for one row adjacent in the horizontal direction as shown in FIG.

  Therefore, when all the pixels adjacent in the horizontal direction work as effective pixels, the change in the signal level of the image signal output from each pixel is as shown in FIG. When combined and an invalid pixel is arranged every other pixel, the change in the signal level of the image signal output from each pixel is as shown in FIG. As can be confirmed from FIG. 22, when two adjacent pixels in the horizontal direction are combined, the signal level of the image signal output from the invalid pixel becomes the value at the time of resetting. Compared to 22 (a), the rate of change of the image signal between adjacent pixels is increased.

  As a result, the image signal output from the solid-state imaging device when the photoelectric conversion portions of pixels adjacent in the horizontal direction are combined is a high-frequency signal having a large amplitude. Therefore, a sample and hold circuit or an amplifier circuit to which an image signal from the solid-state imaging device is input needs to operate with sufficient response even with a high-frequency signal having a large amplitude, and high frequency characteristics are required.

  In view of such a problem, an object of the present invention is to provide a solid-state imaging device capable of reducing the amplitude of an image signal output when the photoelectric conversion portions of pixels adjacent in the horizontal direction are combined. And

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a photoelectric conversion unit that outputs an electric signal corresponding to incident light, and a signal output unit that outputs an electric signal corresponding to an output from the photoelectric conversion unit. In a solid-state imaging device including a plurality of pixels configured as described above, a plurality of adjacent pixels are set as one group unit, and each photoelectric conversion unit is coupled to at least one set of pixels in the group for each group unit. A switching unit for switching between a non-coupled state and a non-coupled state, and selecting one pixel of the plurality of pixels in which the photoelectric conversion unit is coupled by the switch unit as an effective pixel, and the signal output unit of the selected effective pixel When the selection unit for outputting an electrical signal from each other and the photoelectric conversion unit of at least one set of pixels adjacent in the horizontal direction are combined for each group unit, the voltage supplied to the effective pixel, and the effective image The difference between the output from the effective pixel and the output from the invalid pixel is adjusted by adjusting at least one of the voltage supplied to the invalid pixel including the photoelectric conversion unit coupled to the photoelectric conversion unit. And a pixel supply voltage adjusting unit that makes the output difference between the pixel and the invalid pixel less than the output difference when the voltage supplied to the invalid pixel is not adjusted.

  In such a solid-state imaging device, the DC voltage applied when resetting each of the effective pixel and the invalid pixel may be a different voltage value. At this time, the DC voltage supplied to the photoelectric conversion unit may be different, or the DC voltage supplied to the signal output unit may be different.

  In addition, reference voltages applied to the signal output units of the effective pixels and the invalid pixels may be different voltage values. At this time, the signal output unit may be configured by an integration circuit that integrates an electric signal from the photoelectric conversion unit, and the reference voltage may be supplied to the integration circuit. The signal output unit may be configured by a sample hold circuit that samples and holds an electric signal from the photoelectric conversion unit, and the reference voltage may be supplied to the sample hold circuit.

  Further, the solid-state imaging device of the present invention includes a plurality of photoelectric conversion units that output an electric signal corresponding to incident light and a signal output unit that outputs an electric signal corresponding to the output from the photoelectric conversion unit. And a plurality of outputs which are provided in accordance with a plurality of pixels arranged in the horizontal direction and which are output from the signal output unit of each of the plurality of pixels and output to one output signal line In a solid-state imaging device including a circuit, a plurality of adjacent pixels are set as one group unit, and each photoelectric conversion unit is connected to a combined state and a non-bonded state for at least one set of pixels in the group for each group unit. And a switching unit for switching at the same time, and one pixel of the plurality of pixels to which the photoelectric conversion unit is coupled by the switching unit is selected as an effective pixel, and an electric signal is output from the signal output unit of the selected effective pixel Make And a voltage supplied to a first output circuit connected to the effective pixel when the photoelectric conversion unit of at least one set of pixels adjacent in the horizontal direction is coupled for each group unit; By adjusting at least one of the voltage supplied to the second output circuit connected to the invalid pixel including the photoelectric conversion unit coupled to the photoelectric conversion unit of the pixel, the output from the first output circuit and the first An output circuit supply voltage adjusting unit that makes a difference from an output from the two output circuit smaller than a difference between outputs from at least one of the first output circuit and the second output circuit when the voltage to be supplied is not adjusted; It is characterized by having.

  In such a solid-state imaging device, each of the output circuits includes a sample hold unit that samples and holds the electrical signal output from the pixel, and the output circuit connected to each of the effective pixel and the invalid pixel. The reference voltage supplied to the sample hold unit may have a different voltage value. Further, a DC voltage having a predetermined voltage value may be forcibly input to the output circuit connected to each invalid pixel.

  In these solid-state imaging devices, the photoelectric conversion unit of each pixel may output the electrical signal that linearly changes with respect to the amount of incident light. In the photoelectric conversion unit of each pixel, The electric signal that changes logarithmically with respect to the amount of light may be output.

  Further, a plurality of pixels adjacent in the vertical direction and a plurality of pixels adjacent in the horizontal direction are set as one group unit, and the photoelectric conversion unit is combined for each of the group units (a) for all the pixels. One of the pixels to which the photoelectric conversion unit is combined can be switched to any one of (1) combining all the pixels arranged in the vertical direction, and (c) combining all the pixels arranged in the horizontal direction. The electric signal may be output from the signal output unit of the pixel.

  According to the present invention, since a DC voltage having a different voltage value is supplied to each of the effective pixel and the invalid pixel, the difference in signal level between the electric signals output from the effective pixel and the invalid pixel adjacent in the horizontal direction is reduced. can do. Therefore, since the amplitude of the image signal by the electrical signal output from each pixel can be reduced, even when the solid-state imaging device has a large number of pixels and the image signal becomes a high-frequency signal, the subsequent circuit can respond. be able to.

  Further, in order to supply direct current voltages having different voltage values to the output circuits connected to the effective pixels and the ineffective pixels, the signal levels of the electric signals output from the effective pixels and the ineffective pixels adjacent to each other in the horizontal direction. The difference can be reduced. Therefore, similarly, the amplitude of the image signal by the electric signal output from each pixel can be reduced, and the subsequent circuit can respond to the image signal that becomes a high-frequency signal. Furthermore, since the voltage values of the DC voltage applied to the output circuit are different, the pixel configurations of the effective pixel and the invalid pixel can be made the same, and the effective pixel and the invalid pixel can be operated in the same manner.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of a solid-state imaging device that is common to the following embodiments.

  The solid-state imaging device of FIG. 1 includes a solid-state imaging device 1 in which a plurality of pixels are arranged in a matrix, a vertical scanning circuit 2 that outputs a signal for scanning the solid-state imaging device 1 in the vertical direction, and the solid-state imaging device 1. A horizontal scanning circuit 3 that outputs a signal for scanning the image in the horizontal direction, a coupling control circuit 4 that controls coupling of photoelectric conversion units in each pixel in the solid-state imaging device 1 described later, and a photoelectric conversion unit of each pixel The pixel output control circuit 5 for controlling the connection with the signal output unit, and the timing for giving the timing signals for setting the operation timings of the vertical scanning circuit 2, the horizontal scanning circuit 3, the coupling control circuit 4 and the pixel output control circuit 5, respectively. And a generator 6. Although not shown in FIG. 1, an output amplifier that amplifies an electrical signal from the solid-state imaging device 1 and outputs the amplified signal to the outside of the apparatus is also provided.

  According to the solid-state imaging device having such a configuration, each of the solid-state imaging device 1 is provided with a signal synchronized with the timing signal from the timing generator 6 to the vertical scanning circuit 2 and the horizontal scanning circuit 3 to the solid-state imaging device 1. An electrical signal corresponding to the amount of light incident on the photoelectric conversion unit of the pixel is sequentially output to the output amplifier. Then, in the output amplifier, the electric signal that is output from each pixel is amplified and output to the outside of the apparatus as an image signal.

  The coupling control circuit 4 is adjacent to the solid-state imaging device 1 in the vertical direction with a signal φSh that controls the coupling of photoelectric conversion units of a pixels (a is an integer of 2 or more) adjacent in the horizontal direction. A signal φSv for controlling coupling of photoelectric conversion units of b pixels (b is an integer of 1 or more) is provided. The combined pixels are specified by the combination of the signals φSh and φSv, and the number of combined pixels is thereby determined. That is, switching means for switching the photoelectric conversion units between the coupled state and the uncoupled state for at least one set of pixels in each group by the coupling control circuit 4 that generates the signals φSh and φSv and a switch Sa described later. Is configured.

  A signal indicating a pixel to be combined is supplied from the combination control circuit 4 to the pixel output control circuit 5. The pixel output control circuit 5 to which the signal from the coupling control circuit 4 is given has a × b pixel groups coupled by a combination of the signals φSh and φSv as one group unit, and is placed at the same position for each group unit. The a × b type signals φS11 to Sab for connecting / separating the electrical connection between the photodiode of each pixel to be arranged and another element are output to the solid-state imaging element 1.

  When each pixel in the solid-state imaging device 1 is configured by a P-channel MOS transistor, when the signal φSh that is low is supplied from the coupling control circuit 4 to the solid-state imaging device 1, the solid-state imaging device 1 is adjacent in the horizontal direction. When the photoelectric conversion units of a pixels are combined and a low signal φSv is given from the coupling control circuit 4 to the solid-state imaging device 1, the photoelectric conversion of b pixels adjacent in the vertical direction in the solid-state imaging device 1 is performed. The conversion units are combined. Further, when a low signal φSxy (1 ≦ x ≦ a, 1 ≦ y ≦ b) is given from the pixel output control circuit 5 to the solid-state imaging device 1, it is arranged at the position of x rows and y columns for each group unit. The photoelectric conversion unit and the signal output unit of the pixel are electrically connected, and the electrical signal generated by the photoelectric conversion unit of the pixel can be output from the signal output unit.

  The configuration and operation of the solid-state imaging device 1 in the solid-state imaging device configured as described above will be described in the following embodiments. The configuration of the solid-state imaging device shown in FIG. 1 is a common configuration in the following embodiments.

<First Embodiment>
A first embodiment of the present invention will be described with reference to the drawings. FIG. 2 is a block diagram showing an internal configuration of the solid-state imaging device in the present embodiment. In this embodiment, a pixel group of 1 row and 2 columns is set as one group unit. In the present embodiment, since the photoelectric conversion unit is not coupled in the vertical direction, only the signal φSh is output from the coupling control circuit 4.

  In the solid-state imaging device 1 of FIG. 2, the group units U11 to Umn that are composed of two pixels G11 and G21 and a switch Sa that electrically connects and separates the photoelectric conversion units in the pixels G11 and G21 include n rows m. Arranged in a matrix of columns. The signal lines 11a-1 to 11a-m and 11b-1 to 11b-m are installed for each column. .., 11a-m are connected to the pixels G11 of the group units U11 to U1n, U21 to U2n,..., Um1 to Umn, respectively, and the signal lines 11b-1, 11b- , 11b-m are connected to the respective pixel G21 of the group units U11 to U1n, U21 to U2n,..., Um1 to Umn.

  The signal lines 11a-1 to 11a-m and 11b-1 to 11b-m are connected to the sources of the MOS transistors Q1a-1 to Q1a-m and Q1b-1 to Q1b-m, and the switch Sha-1. To one end of each of ~ SHa-m and SHb-1 to SHb-m. The switches SHa-1 to SHa-m, SHb-1 to SHb-m are respectively connected to capacitors Ca-1 to Ca-m, Cb-1 to Cb-m having a DC voltage VPS applied to one end. The other ends are connected to the gates of the MOS transistors Q2a-1 to Q2a-m and Q2b-1 to Q2b-m.

  Further, the drains of the MOS transistors Q3a-1 to Q3a-m and Q3b-1 to Q3b-m are connected to the sources of the MOS transistors Q2a-1 to Q2a-m and Q2b-1 to Q2b-m, respectively. The drain of the MOS transistor Q4 is connected to the sources of the transistors Q3a-1 to Q3a-m and Q3b-1 to Q3b-m via the final output signal line 12. At this time, the DC voltage VPS is applied to the sources of the MOS transistors Q1a-1 to Q1a-m, Q1b-1 to Q1b-m, Q4, and the MOS transistors Q2a-1 to Q2a-m, Q2b-1 to Q2b. -DC voltage VPD is applied to each drain.

  The DC voltage VG is applied to the gates of the MOS transistors Q1a-1 to Q1a-m, Q1b-1 to Q1b-m, and Q4. The gates of the MOS transistors Q3a-1 to Q3a-m and Q3b-1 to Q3b-m are connected to the horizontal scanning circuit 2. MOS transistors Q1a-1 to Q1a-m, Q1b-1 to Q1b-m, Q2a-1 to Q2a-m, Q2b-1 to Q2b-m, Q3a-1 to Q3a-m, Q3b-1 to Q3b- m and Q4 are P-channel MOS transistors, respectively.

  By configuring the solid-state imaging device 1 in this way, the MOS transistors Q1a-1 to Q1a-m and Q1b-1 to Q1b-m in which a DC voltage is applied to the gate and source are equivalent to resistors or constant current sources. A MOS transistor T3 (to be described later) in the pixels G11 and G21 of the group units U11 to Umn and a source follower type amplifier circuit are configured. Therefore, by turning on the switches SHa-1 to SHa-m and SHb-1 to SHb-m, the output voltage appearing at the drains of the MOS transistors Q1a-1 to Q1a-m and Q1b-1 to Q1b-m The amplified image signals of each pixel for one row are sampled and held in the capacitors Ca-1 to Ca-m and Cb-1 to Cb-m.

  Further, each of the MOS transistors Q3a-1, Q3b-1, Q3a-2, Q3b-2,..., Q3a-m, Q3b-m is sequentially turned on by applying a signal to the gates of the MOS transistors Q3a-1, Q3b-1, Q3b-2,. The drain of the transistor is sequentially connected to the source of the MOS transistor Q4. At this time, the MOS transistor Q4 in which a DC voltage is applied to the gate and the source is equivalent to a resistor or a constant current source, and each of the MOS transistors Q2a-1 to Q2a-m and Q2b-1 to Q2b-m is a source follower type. An amplifier circuit is configured. Therefore, the output voltages sampled and held in the capacitors Ca-1 to Ca-m and Cb-1 to Cb-m are amplified and sequentially output from the output signal line 12 to the outside as image signals.

  FIG. 3 shows the configuration of the pixels G11 and G21 provided in each group unit Ukl in the solid-state imaging device 1 having such a configuration. The pixels G11 and G21 have substantially equivalent circuit configurations. In each of the pixels G11 and G21 in FIG. 3, the pn photodiode PD functions as a photosensitive element. The anode of the photodiode PD is connected to the drain of the MOS transistor T7, and the source of the MOS transistor T7 is connected to the gate and drain of the MOS transistor T1 and the gate of the MOS transistor T2. The other end of the capacitor C1 to which the DC voltage VPS is applied at one end is connected to the source of the MOS transistor T2. The drain of the MOS transistor T5 and the drain of the MOS transistor T8 are connected to a connection node between the capacitor C1 and the source of the MOS transistor T2.

  The source of the MOS transistor T5 is connected to the other end of the capacitor C2 to which the signal φVD is applied at one end, the gate of the MOS transistor T4, and the drain of the MOS transistor T6. The source of the MOS transistor T4 is connected to the drain of the MOS transistor T3, and the source of the MOS transistor T3 is connected to the signal lines 11a and 11b (signal lines 11a-1 to 11a-m, 11b-1 to 11b-m in FIG. 2). Connected to the corresponding). Further, a DC voltage VPD is applied to the cathode of the photodiode PD and the drains of the MOS transistors T2 and T4. On the other hand, the signal φVPS is input to the source of the MOS transistor T1. Further, signals φV, φSW, φRSa, and φRSb are input to the gates of the MOS transistors T3, T5, T8, and T6, respectively. The MOS transistors T1 to T8 are P-channel MOS transistors, respectively.

  In the pixel thus configured, the drains of the MOS transistors Qa and Qb (MOS transistors Q1a-1 to Q1a-m, Q1b-1 to Q1b- in FIG. 2) are connected via the MOS transistor T3 and the output signal lines 11a and 11b. (corresponding to m) is connected to the source of the MOS transistor T4. Therefore, when the MOS transistor T3 is ON, the MOS transistor T4 operates as a source follower MOS transistor, and outputs voltage signals amplified by the amplifier circuits of the MOS transistors Qa and Qb to the signal lines 11a and 11b.

  In the pixels G11 and G21 having these common configurations, the control signal applied to the MOS transistor T7 and the voltage applied to the sources of the MOS transistors T6 and T8 are different. That is, in the pixel G11, the signal φS11 is given to the gate of the MOS transistor T7, the DC voltage VRS that is close to the DC voltage VPS is applied to the sources of the MOS transistors T6 and T8, and the MOS transistor T7 in the pixel G21. The signal φS21 is applied to the gate of the transistor and the signal φVRS is applied to the sources of the MOS transistors T6 and T8.

  In the pixels G11 and G21, the photodiode PD and the MOS transistors T1 and T7 constitute a photoelectric conversion unit, and the other MOS transistors T2 to T6 and T8 and the capacitors C1 and C2 constitute a signal output unit. The Between the pixels, there is provided a MOS transistor T9 having a drain connected to the anode of the photodiode PD of the pixel G11 and a source connected to the anode of the photodiode PD of the pixel G21. The MOS transistor T9 is also a P-channel MOS transistor, and operates as the above-described switch Sa when a signal φSh is applied to its gate.

  Note that the control signal φV for the intra-pixel switch for reading the signal to the signal line is given by the vertical scanning circuit 2, and the output circuit switch Q 3 is controlled by the horizontal scanning circuit 3. Various signals such as φVRS, φRSb, φRSa, φVD, φVPS, and φSW may be supplied from the vertical scanning circuit 2 or the horizontal scanning circuit 3, or may be supplied from a separate power source. The same applies to later embodiments.

  When the solid-state imaging device 1 is configured in this way, the values of the signals φS11 and φS21 given to the gates of the MOS transistors T7 in the pixels G11 and G21 constituting the group units U11 to Umn are switched by the pixel output control circuit 5. At the same time, the value of the signal φSh given to the gate of the MOS transistor T9 provided in each of the group units U11 to Umn is switched by the coupling control circuit 4, whereby the number of horizontal effective pixels to be read is switched. That is, the MOS transistors T7, T9 and their control signals φS11, φS21, φSh constitute selection means for outputting an electric signal from the signal output unit of the selected effective pixel, and the signals φS11, φS21, φSh, respectively. The horizontal resolution is set by switching the value of. Below, operation | movement of a solid-state imaging device provided with such a solid-state image sensor 1 is demonstrated below.

  The signal φVPS is a binary voltage signal. When the amount of incident light exceeds a predetermined value, the voltage for operating the MOS transistor T1 in the subthreshold region is set to low, and a signal φVPS higher than this voltage is given. The voltage that allows a larger current to flow through the MOS transistor T2 is set to high. The signal φVD is also a binary voltage signal, the voltage value when the capacitor C2 is integrated is VH, and the voltage value when the image signal is read is VL lower than that during the integration operation. The signal φVRS is also a binary voltage signal, a voltage value equal to the DC voltage VRS is set to Vh, and a voltage value lower than the voltage value Vh is set to Vl.

1. All-pixel readout When reading out each pixel output without performing pixel combination (referred to as “all-pixel readout” in this specification), a signal φSh that is set to high by the coupling control circuit 4 Given to the gate of the MOS transistor T9 in each of the units U11 to Umn, the MOS transistor T9 is turned off. Further, the pixel output control circuit 5 sets the switching timings of the signals φS11 and φS21 to the same timing, and operates the MOS transistors T7 in the pixels G11 and G21 in the group units U11 to Umn of the solid-state imaging device 1 at the same timing. Let Further, the signal φVRS is set to Vh, and the voltage value is made equal to the DC voltage VRS, and is given to the sources of the MOS transistors T6 and T8 in the pixels G11 and G21 in the group units U11 to Umn of the solid-state imaging device 1, respectively.

  The imaging operation by the pixels G11 and G21 of the group units U11 to Umn will be described below with reference to the drawings. FIG. 4 is a timing chart showing the transition of each signal applied to the pixels G11 and G21 constituting the group units U11 to Umn as shown in FIG.

  When an imaging operation is performed in the pixels G11 and G21 in FIG. 3, the signals φS11 and φS21 are set low to turn on the MOS transistor T7 and the signal φVPS is set to low, so that the photocharge corresponding to the amount of incident light is received from the photodiode PD. Flows into the MOS transistor T1. Therefore, a voltage corresponding to the amount of incident light appears at the gates of the MOS transistors T1 and T2 of the pixels G11 and G21, and a current corresponding to the amount of incident light flows through the MOS transistor T2. At this time, since the signals φRSa and φSW are set to high and the MOS transistors T5 and T8 of the pixels G11 and G21 are turned off, negative charge flows into the capacitor C1 through the MOS transistor T2, and an integration operation is performed.

  At this time, if the luminance of the subject is low, the MOS transistor T1 is in a cut-off state, so that photocharge is accumulated at the gate of the MOS transistor T1, and linearly with respect to the incident light quantity at the gates of the MOS transistors T1 and T2. A proportional voltage appears. The voltage appearing at the connection node between the capacitor C1 and the MOS transistor T2 becomes a value linearly proportional to the integral value of the incident light quantity. When the luminance of the subject is high and the voltage corresponding to the amount of photocharge accumulated at the gate of the MOS transistor T1 is low, the MOS transistor T1 operates in the subthreshold region, so that the logarithm of the incident light amount is natural logarithmically. A proportional voltage appears at the gate of the MOS transistor T1. The voltage appearing at the connection node between the capacitor C1 and the MOS transistor T2 is a value that is naturally logarithmically proportional to the integrated value of the incident light quantity.

  Then, by setting the signal φRSb to low and turning on the MOS transistor T6, the voltage at the connection node between the gate of the MOS transistor T4 and the capacitor C2 is reset, and then a low pulse signal φSW is applied to turn on the MOS transistor T5. And Thus, when the MOS transistor T5 is turned on, the voltage appearing at the connection node between the source of the MOS transistor T2 and the capacitor C1 is sampled and held in the capacitor C2.

  In this way, when the voltage appearing at the connection node between the source of the MOS transistor T2 and the capacitor C1 is sampled and held in the capacitor C2, the signal φSW becomes high. Thereafter, a low level pulse signal φV is applied to turn on the MOS transistor T3, and the voltage value of the signal φVD is switched from VH to VL. At this time, in the MOS transistor T4, a current corresponding to a voltage corresponding to the integrated value of the incident light quantity sampled and held by the capacitor C2 flows. Therefore, the image signals of the pixels G11 and G21 each having a voltage value linearly or logarithmically proportional to the integrated value of the incident light amount appear on the signal lines 4a and 4b, respectively.

  Thereafter, the signal φV is set high to turn off the MOS transistor T3 and the voltage value of the signal φVD is set to VH. Then, the signals φS11 and φS21 are set high and the MOS transistor T7 is turned off, whereby the photodiode PD and the MOS transistor T1 are turned off. , T2 is electrically disconnected. At this time, positive charges flow from the source side of the MOS transistor T1, and the negative charges accumulated in the gate and drain of the MOS transistor T1 and the gate of the MOS transistor T2 are recombined, and to some extent, the gate of the MOS transistor T1. And the potential of the drain increases.

  Then, by raising the signal φVPS and increasing the source voltage of the MOS transistor T1, the amount of positive charges flowing from the source side of the MOS transistor T1 increases, and the gate and drain of the MOS transistor T1 and The negative charges accumulated at the gate of the MOS transistor T2 are quickly recombined. At this time, the signal φRSa is set to low, the MOS transistor T8 is turned on, and the voltage at the connection node between the capacitor C1 and the gate of the MOS transistor T2 is initialized.

  Thereafter, the signals φS11 and φS21 are set to low to turn on the MOS transistor T7, and the MOS transistors T1 and T2 and the photodiode PD are electrically connected. Then, after negative charges remaining in the photodiode PD are recombined to initialize the potential of the photodiode PD and the MOS transistors T1 and T2, the signal φVPS is set low and the signal φRSa is set high. To prepare for the imaging operation.

  Thus, by giving each signal to the pixels G11 and G21, each of the pixels G11 and G21 can be operated as an effective pixel. At this time, by operating the pixels G11 and G21 constituting the group units U11 to Umn in the order of the group units U11 to Um1, U12 to Um2, ..., U1n to Umn, an image signal is output for each row. Can do. Then, by turning on the switches SHa-1 to SHa-m and SHb-1 to SHb-m, the image signals output from the pixels G11 and G21 are converted to capacitors Ca-1 to Ca-m, Cb-1 to Sample hold for each row in Cb-m.

  When the image signals for one row are sampled and held in the capacitors Ca-1 to Ca-m and Cb-1 to Cb-m in this way, the horizontal scanning circuit 2 causes the MOS transistors Q3a-1, Q3b-1, Signals are sequentially applied to the gates of Q3a-2, Q3b-2,..., Q3a-m, Q3b-m to turn it ON. In this way, the image signals for one row sampled and held in the capacitors Ca-1 to Ca-m and Cb-1 to Cb-m are sequentially amplified, and the output signal is output as an image signal for each pixel. Output from line 12.

2. Horizontal two-pixel combined readout When the photodiodes of a plurality of pixels included in each group are electrically connected (referred to as “pixel combined readout” in this specification), a signal that becomes low by the coupling control circuit 4 φSh is given to the gate of the MOS transistor T9 in each of the group units U11 to Umn of the solid-state imaging device 1, and the MOS transistor T9 is turned on. Further, the pixel output control circuit 5 sets the signal φS21 to high, and turns off the MOS transistor T7 in the pixel G21 in each of the group units U11 to Umn of the solid-state imaging device 1.

  Therefore, the photodiodes PD of the pixels G11 and G21 are electrically connected through the MOS transistor T9, and the photoelectric charges generated by the two photodiodes PD flow into the MOS transistor T1 of the pixel G11. Further, the signal φVRS is set to Vl, and the voltage value is set to a value lower than the DC voltage VRS, and is given to the sources of the MOS transistors T6 and T8 in the pixel G21 in each of the group units U11 to Umn of the solid-state imaging device 1. As will be apparent from the following description, a pixel supply voltage adjusting means for adjusting the voltage supplied to the invalid pixel by the control signal φVRS is configured.

  The imaging operation by the pixels G11 and G21 of the group units U11 to Umn will be described below with reference to the drawings. FIG. 5 is a timing chart showing the transition of each signal applied to the pixels G11 and G21 constituting the group units U11 to Umn as shown in FIG. Further, signals other than the signals φS11, φS21, φVRS, and φSh are signals common to the pixels G11 and G21.

  When an imaging operation is performed in the pixels G11 and G21 in FIG. 3, the signal φS11 is set low, the MOS transistor T7 of the pixel G11 is turned ON, and the signal φVPS is set low. At this time, since the signal φS21 is high and the signal φSh is low, the MOS transistor T7 of the pixel G21 is OFF and the MOS transistor T9 is ON. Therefore, photoelectric charges corresponding to the amount of incident light flow from the photodiode PD of the pixels G11 and G21 into the MOS transistor T1 of the pixel G11, and a voltage corresponding to the amount of incident light appears at the gates of the MOS transistors T1 and T2 of the pixel G11. Current corresponding to the amount of incident light flows through the MOS transistor T2. At this time, the signals φRSa and φSW are set high, the MOS transistors T5 and T8 are turned OFF, negative charges flow into the capacitor C1 of the pixel G11 through the MOS transistor T2, and an integration operation is performed.

  Then, by setting the signal φRSb to low and turning on the MOS transistors T6 of the pixels G11 and G21, the voltage at the connection node between the gate of the MOS transistor T4 and the capacitor C2 is reset. At this time, in the pixel G11, the voltage at the connection node between the gate of the MOS transistor T4 and the capacitor C2 is reset to a voltage value close to the DC voltage VRS applied to the source of the MOS transistor T6. In the pixel G21, the voltage at the connection node between the gate of the MOS transistor T4 and the capacitor C2 is higher than the voltage value corresponding to the voltage value Vl of the DC voltage φVRS applied to the source of the MOS transistor T6, that is, the DC voltage VRS. Reset to a lower voltage value.

  Thereafter, a low pulse signal φSW is applied to turn on the MOS transistors T5 of the pixels G11 and G21. Thus, in the pixel G11, when the MOS transistor T5 is turned on, the voltage appearing at the connection node between the source of the MOS transistor T2 and the capacitor C1 is sampled and held in the capacitor C2. In addition, in the pixel G21, the voltage value at the time of reset appears in the capacitor C2.

  When the signal φSW is high, a low level pulse signal φV is applied to turn on the MOS transistors T3 of the pixels G11 and G21, and the voltage value of the signal φVD is switched from VH to VL. At this time, in the pixel G11, a current corresponding to a voltage corresponding to the integrated value of the incident light quantity sampled and held by the capacitor C2 flows in the MOS transistor T4. Therefore, an image signal of the pixel G11 having a voltage value linearly or naturally logarithmically proportional to the integral value of the incident light amount appears on the signal line 4a. In the pixel G21, a current corresponding to the reset voltage (voltage lower than the DC voltage VRS) of the capacitor C2 flows in the MOS transistor T4. Therefore, an image signal of the pixel G21 having a value corresponding to the voltage value Vl of the DC voltage φVRS appears on the signal line 4b.

  Thereafter, the signal φV is set to high to turn off the MOS transistors T3 of the pixels G11 and G21, and the voltage value of the signal φVD is set to VH. Then, the signal φS11 is set to high and the MOS transistor T7 is turned off. The diode PD and the MOS transistors T1 and T2 are electrically disconnected, and the reset operation is started. Then, the signal φVPS is set to high to reset the gate and drain of the MOS transistor T1 and the gate of the MOS transistor T2 of the pixels G11 and G21.

  At this time, the signal φRSa is set to low, the MOS transistor T8 is turned on, and the voltage at the connection node between the capacitor C1 and the gate of the MOS transistor T2 is initialized. Thus, in the pixel G11, the voltage at the connection node between the gate of the MOS transistor T2 and the capacitor C1 is reset to a voltage value close to the DC voltage VRS applied to the source of the MOS transistor T8. In the pixel G21, the voltage at the connection node between the gate of the MOS transistor T2 and the capacitor C1 is higher than the voltage value corresponding to the voltage value Vl of the DC voltage φVRS applied to the source of the MOS transistor T8, that is, the DC voltage VRS. Reset to a lower voltage value.

  Thereafter, the signal φS11 is set to low, the MOS transistor T7 of the pixel G11 is turned on, and the MOS transistors T1, T2 and the photodiode PD are electrically connected. In this way, the negative charge remaining in the photodiode PD is recombined to initialize the photodiode PD of the pixels G11 and G21 and the potentials of the MOS transistors T1 and T2, and then the signal φVPS is set to low. And the signal φRSa is set high to prepare for the next imaging operation.

  Thus, by giving each signal to the pixels G11 and G21, the pixel G11 can be operated as an effective pixel, and the pixel G21 can be operated as an invalid pixel. At this time, the switches SHa-1 to SHa-m, SHb-1 to SHb-m, and the MOS transistors Q3a-1 to Q3b-m, Q3b-1 to Q3b-m are operated in the same manner as in the case of all pixel readout. Thus, an image signal for each pixel is output from the output signal line 12. At this time, as shown in FIG. 6, the image signals from the effective pixels and the invalid pixels are alternately output, but the voltage value of the image signal output from the invalid pixels can be lowered as compared with the conventional case. it can. Therefore, the difference in signal level between the effective pixel image signal and the invalid pixel image signal is reduced, and the amplitude of the image signal output from the solid-state imaging device 1 can be reduced.

<Second Embodiment>
A second embodiment of the present invention will be described with reference to the drawings. In addition, about the outline of the internal structure of the solid-state image sensor in this embodiment, it becomes a structure like FIG. 2 similarly to 1st Embodiment. FIG. 7 is a circuit diagram showing an internal configuration of each group unit Ukl provided in the solid-state imaging device according to the present embodiment. Also in this embodiment, a pixel group of one row and two columns is set as one group unit.

  Pixels G11 and G21 provided in each group unit Ukl shown in FIG. 7 are different from FIG. 3 in that the DC voltage VRS is applied to the sources of the MOS transistors T6 and T8 of the pixel G21 instead of the signal φVRS. Is given. Further, the signal φVDx is given to the capacitor C2 of the pixel G21 instead of the signal φVD. This signal φVDx is a ternary voltage signal, and is switched between voltage values VH and VL similar to the signal φVD and a voltage value VLx that is lower than the voltage value VL. The other configurations are the same as those shown in FIG. 3, and thus detailed description thereof is omitted.

  When the solid-state imaging device 1 is configured in this way, the values of the signals φS11 and φS21 are switched by the pixel output control circuit 5 and the value of the signal φSh is switched by the coupling control circuit 4 as in the first embodiment. As a result, the number of effective pixels in the horizontal direction to be read is switched. In this way, as in the first embodiment, by switching the values of the signals φS11, φS21, and φSh, an all-pixel reading operation or a horizontal two-pixel combined reading operation is performed.

  When the all-pixel readout operation is performed, the signal φVDx is switched between the two voltage values VH and VL as in the case of the signal φVD. When the horizontal-direction two-pixel combined readout operation is performed, the signal φVDx is Switching between the two voltage values VH and VLx is performed. The switching timing of each signal during the all-pixel reading operation in this embodiment is shown in the timing chart of FIG. 8, and the switching timing of each signal during the horizontal two-pixel combined reading operation is shown in FIG. It is represented by the timing chart.

  That is, in this embodiment, as in the first embodiment, when the values of the signals φS11 and φS21 are switched at the same timing and the signal φSh is always set to high, and the solid-state imaging device 1 performs the all-pixel reading operation, While the pulse signal φV is applied, the voltage value of the signal φVDx is switched from VH to VL in the same manner as the signal φVD. As described above, the operation timing of each signal other than switching the voltage value of the signal φVDx from VH to VL is the same as that of the first embodiment, and thus the description thereof is omitted.

  Similarly to the first embodiment, when the value of the signal φS21 is always high and the signal φSh is always low, and the solid-state imaging device 1 performs the horizontal two-pixel combined readout operation, the low pulse signal φV is given. Meanwhile, unlike the signal φVD, the voltage value of the signal φVDx is switched from VH to VLx. As described above, the operation timing of each signal other than switching the voltage value of the signal φVDx from VH to VLx is the same as that in the first embodiment, and thus the description thereof is omitted.

  Thus, in the present embodiment, during the horizontal two-pixel combined readout operation, when the voltage value of the signal φVDx applied to the sample-hold capacitor C2 provided in the pixel G21 serving as the invalid pixel is operated as the valid pixel. And a different voltage value. That is, when an image signal is output from the pixel G21 that is an invalid pixel, the voltage value of the signal φVDx is set to VLx that is lower than the voltage value VL when the pixel is operated as a valid pixel. The voltage value of the image signal can be lowered. In this way, as in the first embodiment, the difference in signal level between the image signal of the effective pixel and the image signal of the invalid pixel can be reduced, and the amplitude of the image signal output from the solid-state imaging device 1 can be reduced. can do.

  In the first and second embodiments, the configuration of the pixels G11 and G21 provided in each group unit Ukl is the same as in FIGS. 10 and 11, except that the MOS transistors T5 and T8 and the capacitor C1 are deleted. The source of the MOS transistor T2 may be connected to the connection node between the capacitor C2x and the gate of the MOS transistor T4. That is, the signal output unit is composed of MOS transistors T2 to T4 and T6 and a capacitor C2x.

  At this time, unlike the first and second embodiments, the capacitor C2x performs an integration operation similar to that of the capacitor C1 instead of the sample hold operation. Then, as shown in FIG. 10, the signal φVRS given to the source of the MOS transistor T6 of the pixel G21 or the signal φVDx given to the capacitor C2x as shown in FIG. In this case, the amplitude of the image signal can be reduced.

<Third Embodiment>
A third embodiment of the present invention will be described with reference to the drawings. In addition, about the outline of the internal structure of the solid-state image sensor in this embodiment, it becomes a structure like FIG. 2 similarly to 1st Embodiment. FIG. 12 is a circuit diagram showing an internal configuration of each group unit Ukl provided in the solid-state imaging device according to the present embodiment. Also in this embodiment, a pixel group of one row and two columns is set as one group unit.

  The pixels G11 and G21 provided in each group unit Ukl shown in FIG. 12 are different from FIG. 3 in that the drain of the MOS transistor T3 is connected to the source of the MOS transistor T2, and the MOS transistors T4 to T6 and T8 and the capacitors C1, The configuration is such that C2 is removed. That is, the signal output unit is composed of MOS transistors T2 and T3. Further, a signal φVPSx which is a ternary voltage signal is given to the source of the MOS transistor T1 of the pixel G21.

  In the present embodiment, the voltage value when the signal φVPS is high is Vx, and the voltage value when the signal φVPS is low is Vy. At this time, the signal φVPSx is switched between voltage values Vx and Vy similar to the signal φVPS and a voltage value Vz that is lower than the voltage value Vy. This embodiment has a circuit configuration in which the MOS transistors T4 to T6, T8 and the capacitors C1 and C2 are omitted from the configuration of FIG. 3, and after resetting the MSO transistor T1 and the photodiode PD, the MOS transistor T1 is connected to the gate of the MOS transistor T1. The pixel output is obtained based on the voltage value that appears, but since the signal is amplified and output in common with the configuration of FIG. 3, only the characteristic portion will be described in detail.

  When the solid-state imaging device 1 is configured in this way, the values of the signals φS11 and φS21 are switched by the pixel output control circuit 5 and the value of the signal φSh is switched by the coupling control circuit 4 as in the first embodiment. As a result, the number of effective pixels in the horizontal direction to be read is switched. In this way, as in the first embodiment, by switching the values of the signals φS11, φS21, and φSh, an all-pixel reading operation or a horizontal two-pixel combined reading operation is performed.

  Then, during the all-pixel readout operation, the signal φVPSx is switched between two voltage values Vx and Vy, similarly to the signal φVPS, and during the horizontal two-pixel combined readout operation, the signal φVPSx is 2 It is switched between two voltage values Vx, Vz. Note that the switching timing of each signal during the all-pixel readout operation in this embodiment is represented by the timing chart of FIG. 13, and the switching timing of each signal during the horizontal two-pixel combined readout operation is shown in FIG. It is represented by the timing chart.

  Specifically, in the present embodiment, when the solid-state imaging device 1 performs the all-pixel reading operation, when the pulse signal φV is given and the signal reading is performed, the imaging operation is ended and the resetting operation is started. In the reset period, the signals φS11 and φS21 are switched from low to high to turn off the MOS transistors T7 of the pixels G11 and G21, and the voltage values of the signals φVPS and φVPSx are switched from Vy to Vx. Thereafter, the signals φS11 and φS21 are switched from high to low to turn on the MOS transistors T7 of the pixels G11 and G21, and then the reset operation is completed by setting the voltage values of the signals φVPS and φVPSx to Vy again. The next imaging operation is started.

  On the other hand, when the solid-state imaging device 1 performs the two-pixel combined readout operation in the horizontal direction, the voltage value of the signal φVPS given to the MOS transistor T1 of the pixel G11 is Vy while performing the imaging operation in each of the pixels G11 and G21. The voltage value of the signal φVPSx given to the MOS transistor T1 of the pixel G21 is Vz. When the pulse signal φV is applied and the imaging operation is completed and the reset operation is started, first, the signal φS11 is switched from low to high to turn off the MOS transistor T7 of the pixel G11, and then the voltage value of the signal φVPS is set to Vy. Is switched from Vz to Vx, and the voltage value of the signal φVPSx is switched from Vz to Vx. Thereafter, the signal φS11 is switched from high to low to turn on the MOS transistor T7 of the pixel G11, and then the voltage values of the signals φVPS and φVPSx are set to Vy and Vz again to complete the reset operation and Perform imaging operation.

  As described above, in the present embodiment, the voltage value of the signal φVPSx given to the source of the photoelectric conversion MOS transistor T1 provided in the pixel G21 which is an invalid pixel during the horizontal two-pixel combined readout operation is used as an effective pixel. The voltage value is different from that when operating. That is, when the pixel G21 that is an invalid pixel performs an imaging operation, the voltage value of the signal φVPSx is set to Vz that is lower than the voltage value Vy when operated as an effective pixel, so that the image signal output in the invalid pixel The voltage value can be lowered. In this way, as in the first embodiment, the difference in signal level between the image signal of the effective pixel and the image signal of the invalid pixel can be reduced, and the amplitude of the image signal output from the solid-state imaging device 1 can be reduced. can do.

<Fourth Embodiment>
A fourth embodiment of the present invention will be described with reference to the drawings. In addition, about the outline of the internal structure of the solid-state image sensor in this embodiment, it becomes a structure like FIG. 2 similarly to 1st Embodiment. FIG. 15 is a circuit diagram showing the internal configuration of each group unit Ukl provided in the solid-state imaging device according to this embodiment. Also in this embodiment, a pixel group of one row and two columns is set as one group unit.

  Unlike in FIG. 12, the pixels G11 and G21 provided in each group unit Ukl shown in FIG. 15 include a MOS transistor T10 whose drain is connected to the source of the MOS transistor T7, and the drain and MOS of the MOS transistor T10. The gate of the MOS transistor T2 is connected to the connection node with the source of the transistor T7, and the MOS transistor T1 is removed. That is, the signal output unit is composed of a photodiode PD and MOS transistors T7 and T10. Further, the signal φRS is input to the gates of the MOS transistors T10 in the pixels G11 and G21.

  At this time, the DC voltage VRS is applied to the source of the MOS transistor T10 of the pixel G11, and the signal φVRS that is a binary voltage signal is applied to the source of the MOS transistor T10 of the pixel G21. In the present embodiment, the signal φVRS has a voltage value equal to the DC voltage VRS as Vh and a voltage value lower than the voltage value Vh as Vl, as in the first embodiment. Other configurations are the same as those shown in FIG. 12, and detailed description thereof is omitted.

  When the solid-state imaging device 1 is configured in this way, the values of the signals φS11 and φS21 are switched by the pixel output control circuit 5 and the value of the signal φSh is switched by the coupling control circuit 4 as in the first embodiment. As a result, the number of effective pixels in the horizontal direction to be read is switched. In this way, as in the first embodiment, by switching the values of the signals φS11, φS21, and φSh, an all-pixel reading operation or a horizontal two-pixel combined reading operation is performed.

  As in the first embodiment, during the all-pixel reading operation, the voltage value of the signal φVRS is set to Vh to be equal to the DC voltage VRS, and during the horizontal two-pixel combined reading operation. The voltage value of the signal φVRS is set to Vl, which is lower than the DC voltage VRS. The switching timing of each signal during the all-pixel reading operation in the present embodiment is shown in the timing chart of FIG. 16, and the switching timing of each signal during the horizontal two-pixel combined reading operation is shown in FIG. It is represented by the timing chart.

  That is, in this embodiment, when the solid-state imaging device 1 performs the all-pixel reading operation, when the pulse signal φV is given and the imaging operation is completed, the signals φS11 and φS21 are set to high and the MOS transistors T7 of the pixels G11 and G21 are turned off. In addition, the signal φRS is set low to turn on the MOS transistor T10. Therefore, the gate voltage of the MOS transistor T2 of each of the pixels G11 and G21 is reset to a voltage value corresponding to the DC voltage VRS. Thereafter, the signal φRS is set to high to turn off the MOS transistor T10, and the signals φS11 and φS21 are switched from high to low to turn on the MOS transistors T7 in the pixels G11 and G21. Then, after temporarily setting the signal φRS to low and turning on the MOS transistor T10, the signal φRS is set to high and the MOS transistor T10 is turned off again, and the reset operation is terminated and the next imaging operation is performed.

  On the other hand, when the solid-state imaging device 1 performs the two-pixel combined readout operation in the horizontal direction, when the pulse signal φV is given and the imaging operation is finished, the signal φS11 is set high and the MOS transistor T7 of the pixel G11 is turned off. The signal φRS is set to low to turn on the MOS transistors T10 of the pixels G11 and G21. Therefore, the gate voltage of the MOS transistor T2 in the pixel G11 is reset to a voltage value corresponding to the DC voltage VRS, and the voltage value corresponding to the voltage value Vl in which the gate voltage of the MOS transistor T2 in the pixel G21 is lower than the DC voltage VRS. Reset to.

  Thereafter, as in the all-pixel reading operation, the signal φRS is set to high to turn off the MOS transistors T10 for the pixels G11 and G21, and the signal φS11 is switched from high to low to turn on the MOS transistor T7 of the pixel G11. Then, after temporarily setting the signal φRS to low, the signal φRS is set to high again, the MOS transistor T10 is turned off, the reset operation is terminated, and the next imaging operation is performed.

  Thus, in this embodiment, during the horizontal two-pixel combined readout operation, the voltage value of the signal φVRS given to the source of the reset MOS transistor T10 provided in the pixel G21 serving as an invalid pixel operates as an effective pixel. The voltage value is different from that when That is, when the pixel G21 which is an invalid pixel performs a reset operation, the voltage value of the signal φVRS is set to Vl lower than the voltage value Vh (= VRS) when operated as a valid pixel, so that the invalid pixel outputs The voltage value of the image signal to be generated can be lowered. In this way, as in the first embodiment, the difference in signal level between the image signal of the effective pixel and the image signal of the invalid pixel can be reduced, and the amplitude of the image signal output from the solid-state imaging device 1 can be reduced. can do.

<Fifth Embodiment>
A fifth embodiment of the present invention will be described with reference to the drawings. FIG. 18 is a block diagram illustrating an internal configuration of the solid-state imaging device according to the present embodiment. In this embodiment, a pixel group of 1 row and 2 columns is set as one group unit. In the configuration of the solid-state imaging device in FIG. 18, the same parts as those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  18 differs from the solid-state imaging device 1 of FIG. 2 in that the solid-state imaging device 1a (corresponding to the solid-state imaging device 1 of FIG. 1) has a signal instead of the DC voltage VPS for the capacitors Cb-1 to Cb-m. The configuration is such that φVPSy is given. This signal φVPSy is a binary voltage signal, and a voltage value equal to the DC voltage VPS is V1, and a voltage value lower than the voltage value V1 is V2. In the all-pixel reading operation, the voltage value of the signal φVPSy is set to V1 to be equal to the DC voltage VPS. In the horizontal two-pixel combined reading operation, the voltage value of the signal φVPPSy is V2. The voltage value is lower than the DC voltage VPS. As will be apparent from the following description, the signal φVPSy constitutes output circuit supply voltage adjusting means for adjusting the voltage supplied to the output circuit connected to the invalid pixel.

  In addition, the configuration of the pixels G11 and G21 provided in each group unit Ukl in the solid-state imaging device 1a configured as described above is the same as any of the configurations in the first to fourth embodiments described above. . At this time, with respect to signals other than the signals φS11 and φS21 given to the MOS transistor T7, the signals given to the pixels G11 and G21 may be the same signal. That is, in the configuration as shown in FIG. 3, FIG. 10 or FIG. 15, the DC voltage VRS is applied to the sources of the MOS transistors T6, T8, T10 of the pixel G21, and the configuration as shown in FIG. In this case, the signal φVD is applied to the capacitor C2 of the pixel G21, and in the configuration shown in FIG. 12, the signal φVPS is applied to the source of the MOS transistor T1 of the pixel G21.

  In the pixels G11 and G21 provided in each group unit Ukl, the switching timing of each signal other than the signal φS21 is the group unit Ukl provided in the solid-state imaging device 1 in the first to fourth embodiments described above. This is the same as the pixel G11 provided inside. Similarly to the first to fourth embodiments, the signal φS21 is switched at the same timing as the signal φS11 during the all-pixel reading operation, and when the horizontal two-pixel combined reading operation is performed. Is always high. Therefore, the operation of the pixels G11 and G21 provided in each group unit Ukl is referred to the first to fourth embodiments described above, and detailed description thereof is omitted.

  When the solid-state imaging device 1a is configured in this way, the values of the signals φS11 and φS21 are switched by the pixel output control circuit 5 and the value of the signal φSh is switched by the coupling control circuit 4 as in the first embodiment. As a result, the number of effective pixels in the horizontal direction to be read is switched. In this way, as in the first embodiment, by switching the values of the signals φS11, φS21, and φSh, an all-pixel reading operation or a horizontal two-pixel combined reading operation is performed.

  In the all-pixel readout operation, as in the first embodiment, when the image signals are output from the pixels G11 and G21 in each row, the switches SHa-1 to SHa-m and SHb-1 to SHb-m are turned on. As a result, the capacitors Ca-1 to Ca-m and Cb-1 to Cb-m are sampled and held. At this time, the signal φVPSy is set to V1, and the voltage value applied to the capacitors Cb-1 to Cb-m is set equal to the voltage value VPS. In this way, for example, when the image signals of the pixels G11 and G21 in each of the group units U1l to Uml are output, the image signals from the pixels G11 of the group units U1l to Uml are output from the capacitors Ca-1 to Ca. -M is sampled and held, and image signals from the pixels G21 in the group units U1l to Uml are sampled and held in the capacitors Cb-1 to Cb-m.

  Then, signals are sequentially applied to the gates of the MOS transistors Q3a-1, Q3b-1, Q3a-2, Q3b-2,..., Q3a-m, Q3b-m to turn them on. By doing so, the voltage signals sampled and held in the capacitors Ca-1, Cb-1, Ca-2, Cb-2,..., Ca-m, Cb-m are sequentially supplied by the MOS transistor Q4. Amplified by MOS transistors Q2a-1, Q2b-1, Q2a-2, Q2b-2,..., Q2a-m, Q2b-m constituting the source follower amplifier. The image signals of the pixels G11 and G21 in the group units U1l to Uml thus amplified are output from the output signal line 12 for each pixel.

  On the other hand, in the horizontal two-pixel combined readout operation, the switches SHb-1 to SHb-m are always turned OFF, and the switches SHa-1 to SHa-m are output when the image signals are output from the pixels G11 and G21 in each row. Only the image signal from the pixel 11 is sampled and held in the capacitors Ca-1 to Ca-m. At this time, the signal φVPSy is set to V2, and the voltage value applied to the capacitors Cb-1 to Cb-m is set to a value lower than the voltage value VPS.

  Then, similarly to the all-pixel reading operation, signals are sequentially applied to the gates of the MOS transistors Q3a-1, Q3b-1, Q3a-2, Q3b-2,..., Q3a-m, Q3b-m to turn them ON. By doing so, the voltage signals sampled and held in the capacitors Ca-1, Cb-1, Ca-2, Cb-2,..., Ca-m, Cb-m are sequentially supplied by the MOS transistor Q4. Amplified by MOS transistors Q3a-1, Q2b-1, Q2a-2, Q2b-2,..., Q2a-m, Q2b-m constituting the source follower amplifier.

  At this time, the voltage signals of the capacitors Cb-1 to Cb-m are voltage signals corresponding to the voltage value V2 of the signal φVPSy, and are voltage signals having a voltage value lower than the DC voltage VPS. The image signals from the pixels G11 of the group units U1l to Uml thus amplified and the voltage signals for the pixels G21 of the group units U1l to Uml thus amplified alternately are output signals for every one pixel. Output from line 12. That is, the image signal from the pixel G11 that is an effective pixel and the voltage signal corresponding to the invalid pixel G21 are alternately output from the output signal line 12, but the voltage signal corresponding to the invalid pixel G21 is lower than the DC voltage VPS. The signal is an amplified voltage value. Therefore, the difference between the signal levels of the effective pixel image signal and the invalid pixel voltage signal can be reduced, and the amplitude of the image signal output from the solid-state imaging device 1a can be reduced.

<Sixth Embodiment>
A fifth embodiment of the present invention will be described with reference to the drawings. FIG. 19 is a block diagram illustrating an internal configuration of the solid-state imaging device according to the present embodiment. In this embodiment, a pixel group of 1 row and 2 columns is set as one group unit. In the configuration of the solid-state imaging device in FIG. 19, the same parts as those in the configuration in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The solid-state imaging device 1b (corresponding to the solid-state imaging device 1 in FIG. 1) of FIG. 19 has a configuration similar to that of the solid-state imaging device 1 in FIG. 2, with a DC voltage V2 applied to one end and a MOS transistor Q3b at the other end. The switches Sb-1 to Sb-m connected to the gates of -1 to Q3b-m are added. Note that the DC voltage V2 is a voltage value lower than the DC voltage VPS, like the voltage value V2 in the signal φVPSy of the fifth embodiment. The switches Sb-1 to Sb-m are turned off during the all-pixel reading operation, and the switches Sb-1 to Sb-m are turned on during the horizontal two-pixel combined reading operation. The The switches Sb-1 to Sb-m constitute output circuit supply voltage adjusting means for adjusting the voltage supplied to the output circuit connected to the invalid pixel.

  At this time, the configurations of the pixels G11 and G21 provided in each group unit Ukl in the solid-state imaging device 1b are the same as any of the configurations in the first to fourth embodiments described above, as in the fifth embodiment. The configuration. For signals other than the signals φS11 and S21 given to the MOS transistor T7, the signals given to the pixels G11 and G21 may be the same signal.

  When the solid-state imaging device 1b is configured in this manner, the values of the signals φS11 and φS21 are switched by the pixel output control circuit 5 and the value of the signal φSh is switched by the coupling control circuit 4 as in the first embodiment. As a result, the number of horizontal pixels to be read is switched. In this way, as in the first embodiment, by switching the values of the signals φS11, φS21, and φSh, an all-pixel reading operation or a horizontal two-pixel combined reading operation is performed.

  In the all-pixel readout operation, as in the fifth embodiment, when the image signals are output from the pixels G11 and G21 in each row, the switches SHa-1 to SHa-m and SHb-1 to SHb-m are turned on. As a result, the capacitors Ca-1 to Ca-m and Cb-1 to Cb-m are sampled and held. At this time, the switches Sb1 to Sb-m are turned off. Then, signals are sequentially given to the gates of the MOS transistors Q3a-1, Q3b-1, Q3a-2, Q3b-2,..., Q3a-m, Q3b-m to turn them on, and in each of the amplified group units U1l to Uml. The image signals of the pixels G11 and G21 are output from the output signal line 12 for each pixel.

  On the other hand, in the horizontal two-pixel combined readout operation, the switches SHb-1 to SHb-m are always turned off and the switches Sb-1 to Sb-m are always turned on. Therefore, as in the fifth embodiment, when outputting image signals from the pixels G11 and G21 in each row, only the switches Sha-1 to SHa-m are turned ON, so that only the image signal from the pixels 11 is output from the capacitor Ca. Sampled and held at −1 to Ca−m. At this time, since the switches Sb-1 to Sb-m are always turned on, a voltage value V2 lower than the voltage value VPS is applied to the gates of the MOS transistors Q2b-1 to Q2b-m.

  Then, similarly to the all-pixel reading operation, signals are sequentially applied to the gates of the MOS transistors Q3a-1, Q3b-1, Q3a-2, Q3b-2,..., Q3a-m, Q3b-m to turn them ON. In this way, the image signals sampled and held in the capacitors Ca-1 to Ca-m are amplified by the MOS transistors Q2a-1 to Q2a-m and given through the switches Sb-1 to Sb-m. The voltage value V2 obtained is amplified by the MOS transistors Q2b-1 to Q2b-m.

  Therefore, as in the fifth embodiment, the amplified image signal from the pixel G11 of each of the group units U1l to Uml and the voltage signal for the pixel G21 of each of the group units U1l to Uml that are amplified in the same manner are one pixel. The signal is alternately output from the output signal line 12 every minute. That is, the image signal from the pixel G11 that is an effective pixel and the voltage signal corresponding to the invalid pixel G21 are alternately output from the output signal line 12, but the voltage signal corresponding to the invalid pixel G21 is lower than the DC voltage VPS. The signal is an amplified voltage value. Therefore, the difference between the signal levels of the effective pixel image signal and the invalid pixel voltage signal can be reduced, and the amplitude of the image signal output from the solid-state imaging device 1a can be reduced.

  In the first to sixth embodiments, for each of the group units U1l to Uml, the pixel group composed of the pixels G11 and G21 in one row and two columns is set as one group unit. It is not limited to being formed. Therefore, for example, for each of the group units U11 to Uml, the pixel group of the pixels G11 to G22 in 2 rows and 2 columns may be set as one group unit, or the pixel group of the pixels G11 to G32 in 2 rows and 3 columns may be One group unit may be used.

  At this time, for example, when each of the group units U11 to Uml is configured by four pixels G2 to G22 of 2 rows and 2 columns, the pixels G11 and G21 adjacent in the horizontal direction in the group unit Ukl as shown in FIG. A switch Sa1 that performs electrical contact / separation of each photoelectric conversion unit, a switch Sa2 that performs electrical contact / separation of each of the photoelectric conversion units adjacent to the pixels G12 and G22 in the horizontal direction, and a pixel G11 adjacent in the vertical direction , G12 includes a switch Sc1 that electrically contacts and separates the photoelectric conversion units, and a switch Sc2 that electrically connects and separates the photoelectric conversion units of the pixels G21 and G22 adjacent in the vertical direction.

  In FIG. 20, the configuration of only the group unit Ukl is shown, and the photodiode PD and the MOS transistor T7 which are a part of the pixels G11 to G22 are shown. Therefore, the contacts of the switches Sa1, Sa2, Sc1, and Sc2 are connected to the connection node between the anode of the photodiode PD and the drain of the MOS transistor T7. Although not shown, for example, when the configurations of the pixels G11 and G21 are as shown in FIG. 3, the pixel G12 is configured similarly to the pixel G11, and the pixel G22 is configured similar to the pixel G21. The pixels G12 and G22 are configured as shown in FIG. In the following description, it is assumed that the configurations of the pixels G11 and G21 and the configurations of the pixels G12 and G22 are as shown in FIG.

  In such a configuration, in the all-pixel reading operation, the switches Sa1, Sa2, Sc1, and Sc2 are turned off, and the MOS transistors T7 of the pixels G11 to G22 are operated at the same timing for each row. . At this time, since the pixels are not coupled in the horizontal direction, the signal φVRS is set to a voltage value Vh equal to the DC voltage VRS. In the vertical two-pixel combined readout operation, the switches Sa1 and Sa2 are turned off, the switches Sc1 and Sc2 are turned on, the MOS transistors T7 of the pixels G12 and G22 are turned off, and the pixels The MOS transistors T7 of G11 and G21 are operated at the same timing for each row. At this time, since the pixels are not coupled in the horizontal direction, the signal φVRS is set to a voltage value Vh equal to the DC voltage VRS as in the case of the all-pixel reading operation.

  In the horizontal two-pixel combined readout operation, the switches Sa1 and Sa2 are turned on, the switches Sc1 and Sc2 are turned off, the MOS transistors T7 of the pixels G21 and G22 are turned off, and the pixels The MOS transistors T7 of G11 and G12 are operated at the same timing for each row. At this time, since the pixels are coupled in the horizontal direction, the signal φVRS is set to a voltage value Vl lower than the DC voltage VRS. Further, during the four-pixel combined readout operation, the switches Sa1, Sa2, Sc1, and Sc2 are turned on, and the MOS transistors T7 of the pixels G12, G21, and G22 are turned off. At this time, since the pixels are combined in the horizontal direction, the pixels are combined in the horizontal direction as in the case of the horizontal two-pixel combined read operation, so that the signal φVRS is set to a voltage value Vl lower than the DC voltage VRS. .

  Thus, when the pixels are combined in the horizontal direction, by changing the reset voltage for the pixels that are combined and become invalid pixels, or by changing the potential state at the time of output, An offset voltage is applied to an output voltage from a pixel that becomes an invalid pixel. Therefore, the voltage difference from the output voltage from the effective pixels adjacent in the horizontal direction can be reduced, and the amplitude of the image signal output from the solid-state imaging device 1 can be reduced. In the above description, the MOS transistor constituting each pixel in the solid-state imaging device 1 is a P-channel MOS transistor, but may be an N-channel MOS transistor. At this time, the polarity and the relationship between applied voltages are opposite to each other, but the connection relationship, signal switching timing, and the like are the same as those in the above-described embodiments.

These are block diagrams which show the internal structure of the solid-state imaging device which is embodiment of this invention. These are block diagrams which show the internal structure of the solid-state image sensor in the solid-state imaging device of 1st-6th embodiment. These are circuit diagrams which show the structure of the pixel which comprises one group unit provided in the solid-state image sensor of 1st Embodiment. FIG. 4 is a timing chart showing an operation at the time of reading all pixels in the solid-state imaging device having the pixel configuration of FIG. 3. These are timing charts showing the operation at the time of horizontal two-pixel combined readout in the solid-state imaging device having the pixel configuration of FIG. These are figures which show the state of the image signal output from the solid-state image sensor of FIG. These are circuit diagrams which show the structure of the pixel which comprises one group unit provided in the solid-state image sensor of 2nd Embodiment. FIG. 8 is a timing chart showing an operation at the time of reading all pixels in the solid-state imaging device having the pixel configuration of FIG. 7. FIG. 8 is a timing chart showing an operation at the time of horizontal two-pixel combined readout in the solid-state imaging device having the pixel configuration of FIG. 7. These are circuit diagrams which show another structure of the pixel which comprises one group unit provided in the solid-state image sensor of FIG. These are circuit diagrams which show another structure of the pixel which comprises one group unit provided in the solid-state image sensor of FIG. These are circuit diagrams which show the structure of the pixel which comprises one group unit provided in the solid-state image sensor of 3rd Embodiment. FIG. 13 is a timing chart showing an operation at the time of reading all pixels in the solid-state imaging device having the pixel configuration of FIG. FIG. 13 is a timing chart showing an operation at the time of horizontal two-pixel combined readout in the solid-state imaging device having the pixel configuration of FIG. 12. These are circuit diagrams which show the structure of the pixel which comprises one group unit provided in the solid-state image sensor of 4th Embodiment. FIG. 16 is a timing chart showing an operation at the time of reading all pixels in the solid-state imaging device having the pixel configuration of FIG. FIG. 16 is a timing chart showing an operation at the time of horizontal two-pixel combined readout in the solid-state imaging device having the pixel configuration of FIG. 15. These are block diagrams which show the internal structure of the solid-state image sensor in the solid-state imaging device of 5th Embodiment. These are block diagrams which show the internal structure of the solid-state image sensor in the solid-state imaging device of 6th Embodiment. These are block diagrams which show another structure for one group unit provided in the solid-state image sensor. These are the timing charts which show the state of the signal in the conventional solid-state imaging device. These are figures which show the state of the image signal output from the solid-state image sensor of the conventional solid-state imaging device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Solid-state image sensor 2 Vertical scanning circuit 3 Horizontal scanning circuit 4 Coupling control circuit 5 Pixel output control circuit 6 Timing generator 11a-1 to 11a-m, 11b-1 to 11b-m Signal line 12 Output signal line

Claims (8)

In a solid-state imaging device including a plurality of pixels configured by a photoelectric conversion unit that outputs an electric signal according to incident light and a signal output unit for outputting an electric signal according to an output from the photoelectric conversion unit,
A plurality of adjacent pixels as one group unit, and a switching unit for switching each photoelectric conversion unit between a coupled state and a non-coupled state for at least one set of pixels in the group for each group unit;
A selection unit for selecting one of the plurality of pixels in which the photoelectric conversion unit is combined by the switching unit as an effective pixel, and outputting an electric signal from the signal output unit of the selected effective pixel;
When the photoelectric conversion units of at least one set of pixels adjacent in the horizontal direction are combined for each group unit, the voltage supplied to the effective pixel and the photoelectric conversion unit combined with the photoelectric conversion unit of the effective pixel The voltage supplied to at least one of the effective pixel and the invalid pixel is determined by adjusting at least one of the voltage supplied to the invalid pixel and the difference between the output from the effective pixel and the output from the invalid pixel. A pixel supply voltage adjustment unit that makes the output difference between the two when not adjusted,
A solid-state imaging device.   2. The solid-state imaging device according to claim 1, wherein the DC voltage applied when resetting each of the effective pixel and the invalid pixel is set to a different voltage value.   The solid-state imaging device according to claim 1, wherein reference voltages given to the signal output units of the effective pixels and the ineffective pixels are set to different voltage values. A plurality of pixels configured by a photoelectric conversion unit that outputs an electrical signal according to incident light and a signal output unit for outputting an electrical signal according to an output from the photoelectric conversion unit, and a plurality of pixels arranged in a horizontal direction A solid-state imaging device comprising: a plurality of output circuits that are provided in accordance with the pixels of the plurality of pixels and that amplify the electrical signal output from the signal output unit of each of the plurality of pixels and output the signal to one output signal line.
A plurality of adjacent pixels as one group unit, and a switching unit for switching each photoelectric conversion unit between a coupled state and a non-coupled state for at least one set of pixels in the group for each group unit;
A selection unit for selecting one of the plurality of pixels in which the photoelectric conversion unit is combined by the switching unit as an effective pixel, and outputting an electric signal from the signal output unit of the selected effective pixel;
A voltage supplied to a first output circuit connected to the effective pixel when the photoelectric conversion units of at least one set of pixels adjacent in the horizontal direction are coupled for each group unit; and the photoelectric conversion unit of the effective pixel The output from the first output circuit and the output from the second output circuit are adjusted by adjusting at least one of the voltage supplied to the second output circuit connected to the invalid pixel including the photoelectric conversion unit coupled to An output circuit supply voltage adjustment unit that makes the difference between the output voltage and the output voltage of at least one of the first output circuit and the second output circuit smaller than the difference between the outputs of the two when not adjusted,
A solid-state imaging device. Each of the output circuits includes a sample hold unit that samples and holds the electrical signal output from the pixel,
The solid-state imaging device according to claim 4, wherein in the output circuit connected to each of the effective pixel and the invalid pixel, the reference voltage supplied to the sample and hold unit is set to different voltage values.   The solid-state imaging device according to claim 4, wherein a DC voltage having a predetermined voltage value is forcibly input to the output circuit connected to each of the invalid pixels.   The solid-state imaging device according to claim 1, wherein the photoelectric conversion unit of each pixel outputs the electric signal that linearly changes with respect to an incident light amount.   The solid-state imaging device according to any one of claims 1 to 6, wherein the photoelectric conversion unit of each pixel outputs the electrical signal that varies logarithmically with respect to an incident light amount.

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