KR100576472B1 - Address latch circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address latch circuit for use in a semiconductor memory device. In particular, when a previous address signal latched at an output terminal is fed back and a potential is compared with a next input signal signal, the circuit operation is disabled. Thus, the present invention relates to an address latch circuit that significantly reduces standby current to realize low power.

Description

Address latch circuit

1 is a circuit diagram showing an example of a conventional address latch circuit;

FIG. 2 is a result of simulating a current change for the address latch circuit shown in FIG.

3 is a circuit diagram showing an example of an address latch circuit according to the present invention;

<Description of Symbols for Major Parts of Drawings>

10: comparison unit 20: transmission unit

30, 50: latch portion 40: clock synchronization portion

60: output driver

The present invention relates to an address latch circuit used in a semiconductor memory device, and more particularly, to disable an address latch operation when it is determined to be the same address by a potential comparison between a previous address signal and a next input address signal latched at an output terminal. The present invention relates to an address latch circuit for reducing standby current to realize low power.

In general, a memory system using synchronous DRAM requires very little current consumption, and the amount of current consumption in a battery-mounted field such as a notebook is one of the main factors to be treated very sensitively.

In addition, in the synchronous DRAM, an internal clock signal is generated in synchronization with an external clock signal. Since the internal clock signal is used for latching an internal address, the potential discharge and charging of the latch circuit output node is repeated every clock. Current consumption.

1 is a circuit configuration diagram showing an example of an address latch circuit used in the related art, comprising: two NMOS transistors MN11 and MN12 that receive complementary potential signals of external input address signals to respective gate ends; The power supply voltage is applied between the drain terminals of the NMOS transistors MN11 and MN12 by the nodes N1 and N2, respectively, and the gates are cross-coupled by the two nodes N1 and N2. Two MOS transistor pairs MP11 and MN13 and MP12 and MN14 connected to each other; Two PMOS transistors MP13 and MP14 connected between a power supply voltage applying terminal and the two nodes N1 and N2, respectively, and having an internal clock signal int_clk commonly applied to each gate terminal; A PMOS transistor MP15 connected between the drain terminals of the two PMOS transistors MP13 and MP14 and to which the internal clock signal int_clk is applied to a gate terminal; An NMOS transistor MN15 connected between a common source terminal and a ground terminal of the two NMOS transistors, and to which the internal clock signal int_clk is applied as a gate terminal; Respective inverters IV11 and IV12 for inverting the potential of each of the two nodes N1 and N2; Latch element consisting of two NOR gates NOR11 and NOR12 which use the output signals of the output terminals N3 and N4 of each of the two inverters IV11 and IV12 as one input signal and receive the output signals of each other and apply them to the other input terminal. Wow; And buffering elements IV13 and IV14 for buffering and outputting the output signal of the latch element.

The operation of the address latch circuit having the above configuration is as follows.

First, when the internal clock signal int_clk is 'logic low', the potentials of the two nodes N1 and N2 are supplied with a power supply voltage by the PMOS transistors MP13 to MP15 that are turned on, thereby 'logic high'. It is then precharged, and the potentials of the two nodes N3 and N4 are 'logic low' via the respective inverters IV11 and IV12 to latch the output terminal potential to the previous value.

Thereafter, when the external input clock signal rises to 'logic high' and is applied as the input address signal add_in, one of the two nodes N1 and N2 is discharged to transition to the 'logic low' level. For example, if the input address signal add_in is 'logic high', the node N2 is discharged. If the input address signal add_in is 'logic low', the node N1 is discharged.

The internal clock signal int_clk swings back to the logic low level to latch the previous address potential value.

As such, regardless of whether the potential of the input address signal value is logic high or logic low, current flows through the NMOS transistor MN15 for address latching at all times, resulting in unnecessary current consumption in this process. The waste of power becomes a bigger problem as the number of address pins increases rapidly.

FIG. 2 is a simulation result of the current change of the address latch circuit shown in FIG. 1. As can be seen from the figure, the instant when the potential of the internal clock signal int_clk transitions from logic low to logic high is shown in FIG. Each time is followed by a large current consumption, this phenomenon is aggravated in the case of high-speed operation, that is, the shorter clock cycle to increase the current consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and an object of the present invention is to receive a previous address signal latched at an output terminal and compare the result with a next address signal inputted to disable the address latch operation if the address is the same. The present invention provides an address latch circuit that reduces current consumption required to realize low power.

In order to achieve the above object, the address latch circuit according to the present invention comprises a comparison unit for comparing the external input address signal and the potential of the previous address signal fed back from the output driver to determine whether or not the same; A transmission unit which receives an external input address signal and selectively outputs the output signal according to the output of the comparison unit; A first latch unit which receives the output of the transfer unit and latches the output; A clock synchronizer configured to receive an output of the first latch unit and to output the first latch unit in synchronization with an internal clock signal; A second latch unit which receives the output of the clock synchronizing unit and latches the output; And an output driver configured to receive and amplify the output of the second latch unit.

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The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a circuit diagram illustrating an example of an address latch circuit according to an embodiment of the present invention, in which an external input address signal add_in and a previous address signal add_out latched at an output terminal are fed back to these two address signals add_in and add_out. The comparison unit 10 and the switching unit 10 are configured to determine whether the potentials are the same by comparing the potentials of the switching units, and the switching is controlled according to the output result of the comparing unit 10 so that the external input address signal add_in is selectively selected. An internal clock for transmitting the transmission unit 20, the first latch unit 30 which latches the address signal passing through the transmission unit 20 constantly, and the address signal latched by the first latch unit 30. To the clock synchronizer 40 for synchronizing and transmitting the signal, the second latch unit 50 for constantly latching the address signal transmitted through the clock synchronizer 40, and the second latch unit 50. Amplified latched address signal Further included is an output driver 60 which forces.

The comparator 10 is connected to each other in series by each drain terminal N1, and a previous address signal latched to the output terminal is applied to each gate terminal, and the authenticity of the external input address signal is applied to each source terminal. And a PMOS transistor MP31 and an NMOS transistor MN31 to which a complementary potential signal is applied, respectively.

The transfer unit 20 includes a transfer transistor MT31 whose turn-on is controlled by a signal of the output terminal N1 of the comparator.

The first and second latch units 30 and 50 are connected to two inverters IV31 and IV32 and IV33 and IV34 connected to each other by an annular input / output terminal.

 In addition, the clock synchronizer 40 is connected in series between a power supply voltage applying terminal and a ground terminal, and a PMOS transistor MP32 and an NMOS to which a complementary potential signal and an authenticity potential signal of the internal clock signal are applied to each gate terminal. A transistor MN32 and; The PMOS transistor MP33 and the NMOS transistor MN33 are connected in series between the two MOS transistors MP32 and MN32, and the output signal of the first latch unit 30 is commonly applied to the respective gate terminals. It is equipped with.

The output driver 60 is configured as an inverter IV35 that receives the output signal of the second latch unit and inverts the signal to the output terminal.

Hereinafter, the operation of the present invention having the above configuration will be described in detail with reference to the drawings.

First, when the next address signal is input from the outside while the address signal is latched to the output terminal, the comparator 10 receives the previous address signal add_out latched to the output terminal and feeds back the external input address signal add_in. The potentials are compared.

For example, when the potential of the address signal add_in input from the outside when the potential of the previous address signal add_out latched at the output terminal is 'logic high' is applied in the state of 'logic high', the comparison unit 10 The PMOS transistor MP31 is turned off, while the NMOS transistor is turned on to make the potential of its output node N1 'logic low'. Accordingly, the transfer transistor MT31 as the switching element in the transfer unit 20 in the rear stage is turned off, thereby preventing the external input address signal add_in from being transferred to the output terminal.

Accordingly, since the potential of the output node N2 in the clock synchronizer 40 is 'logic high' even when the internal clock signal int_clk is transmitted to the address latch circuit, it passes from the power supply voltage supply terminal to the node N2. By blocking the current path to the ground terminal, it is possible to prevent the current consumption.

On the other hand, when the potential of the address signal add_in input from the outside is applied as 'logic low' while the potential of the previous address signal add_out latched at the output terminal is 'logic low', the PMOS in the comparison unit 10 is applied. Since the transistor MP31 is turned on, while the NMOS transistor is turned off, the potential of the external logic input address signal add_in of 'logic low' is transferred to the output node N1, so that the transfer unit 20 at the rear end is provided. By turning off the transfer transistor MT31 as a switching element in the circuit, the external input address signal add_in is blocked from being transferred to the output terminal.

In this case as well, even if the internal clock signal int_clk is transmitted to the address latch circuit, the potential of the output node N2 in the clock synchronizer 40 becomes 'logic high'. The current path formed through the node N2 to the ground terminal is blocked to prevent unnecessary current consumption.

However, when the potential of the previous address signal add_out fed back from the output terminal and the potential of the external input address signal add_in are different, that is, add_in = 'logic high', add_out = 'logic low', or add_in = ' Logic low 'and add_out = logic high to make the output terminal N1 potential of the comparator 10' logic high 'to transfer the transfer transistor MT31 which is a switching element in the transfer unit 20 at the rear stage. It will turn on.

Accordingly, the external input address signal add_in is transmitted to the output terminal in synchronization with the internal clock signal int_clk.

Therefore, the address latch circuit according to the present invention compares the address signal add_out latched to the output terminal with the next address signal inputted, and if it is the same, disables the address latch circuit to prevent unnecessary current consumption in order to prevent its transfer. Higher speed operation is possible for addresses requiring high speed address strobing operation while minimizing consumption, thereby preventing degradation of chip performance.

As described above, according to the address latch circuit according to the present invention, by receiving a previous address signal latched at an output terminal and comparing the potential with an input address signal input next time, by controlling the circuit operation to be disabled when it is determined to be the same address, There is an excellent effect that can realize a low power by greatly reducing the standby current.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to make various modifications, changes, additions, etc. within the spirit and scope of the present invention, such modifications and modifications belong to the scope of the claims You will have to look.

Claims (4)

A comparator for comparing the external input address signal and the potential of the previous address signal fed back from the output driver to determine whether they are the same; A transmission unit which receives the external input address signal and selectively outputs the output signal according to the output of the comparison unit; A first latch unit receiving the output of the transfer unit and latching the output; A clock synchronizing unit configured to receive an output of the first latch unit and to output the first latch unit in synchronization with an internal clock signal; A second latch unit receiving the output of the clock synchronizing unit and latching the output; And The output driver for receiving and amplifying and outputting the output of the second latch unit Address latch circuit comprising a. The method of claim 1, The comparator includes a PMOS transistor connected in series with each drain terminal to apply the previous address signal to each gate terminal, and an authenticity and inversion potential signal of the external input address signal to each source terminal. An address latch circuit comprising an NMOS transistor. The method of claim 1, And the transfer unit includes a transfer transistor whose turn-on is selectively controlled by an output signal of the comparator. The method of claim 1, The clock synchronizing unit may be connected in series between a power supply voltage applying terminal and a ground terminal, and may include a first PMOS transistor and a first NMOS transistor to which an inverted potential signal and an authentic potential signal of the internal clock signal are applied to respective gate terminals; And a second PMOS transistor and a second NMOS transistor connected in series between the first PMOS transistor and the first NMOS transistor, and to which an output signal of the first latch unit is commonly applied to each gate terminal. Address latch circuit.

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