KR100443064B1 - Image Reversal Method for Forming Small Scale Structures in Integrated Circuits - Google Patents

Abstract

The present invention provides a method of manufacturing a small scale structure to be employed in an integrated circuit formed on a semiconductor substrate 12. Examples of such small scale structures include contacts, biases and metal lines. The method of the present invention employs image reversal technology to obtain improved feature resolution. In forming features 28 in layer 16 of material, a clear field reticle is used to form patterned segments of photoresist 18, each of which forms within layer 16 of material. As long as the feature 28 is substantially the same size, shape, and position. This method is used in place of the dark field reticle forming the window in the photoresist, each of the windows being substantially the same size, shape and position as the size, shape and location of the patcher 28 formed in the layer 16 of material. And position. For small scale structures, openings or windows in the photoresist are more difficult to form than patterned segments of the photoresist 18. The inventive method of using a clear field reticle to form a mask comprising patterned segments of photoresist 18 removes the restriction of patterning small windows of photoresist using dark field reticles. Thus, the accuracy of forming the small scale structure is improved.

Description

Image Reversal Method for Forming Small Scale Structures in Integrated Circuits

Current integrated circuit devices are formed on silicon substrates and include doped regions in the substrate where the source or drain connections are separated into gate control regions. Electrical connections to the source, gate, and drain electrodes are formed by interconnects, for example metal interconnects, supported on the substrate by an interlayer dielectric.

Typical integrated circuits use multiple levels of interconnects. For example, the first level of patterned interconnects contact the source and drain contacts with the gate electrode in a desired pattern. Typically, a first level of patterned interconnect is formed and then oxide is deposited on the semiconductor substrate. These oxides form an interlayer dielectric. These oxides are sequentially patterned and etched to form contact / via openings. The contact / via opening of the interlayer dielectric is filled with a metal plug using etching back or polishing followed by blanket metal deposition. A layer of patterned metal lines, including a second level of patterned interconnects, is formed on the interlayer dielectric. The metal plug forms an electrical contact between the first level of patterned interconnect and the second level of patterned interconnect. Additional levels of patterned metal lines or interconnects may also be formed, with each level of interconnect being also separated by an interlayer dielectric layer. Electrical connections between different levels of interconnects are provided by additional metal plugs.

A photoresist is formed thereon to etch the contact / via openings with an interlayer dielectric. The photoresist is exposed to light, leaving a designated area of exposed oxide, i.e., developed without forming a photoresist thereon. Exposed regions of the oxide are etched to create contact / empty openings.

In general terms, openings or small windows are formed in the photoresist that expose the underlying material layer (eg, oxide) to the next process (eg, etching). Such small windows in the photoresist exposing the underlying material layer are formed by developing the photoresist by exposing the photoresist to light.

In principle, the photoresist consists of a positive photoresist or a negative photoresist. However, positive photoresists are typically used to pattern small structures, i.

For the positive photoresist, a portion of the photoresist exposed to light is developed. A portion of the unexposed photoresist is left in place to provide a mask of patterned photoresist that protects the underlying material formed immediately below during the next treatment.

In contrast, for negative photoresists, a portion of the photoresist that is not exposed to light is developed. A portion of the exposed photoresist is left in place to provide a mask of patterned photoresist that protects the underlying material formed immediately below during the next treatment.

However, the negative photoresist used to limit the small scale structure, i.e., size of 0.5 mu m or less, cannot be used. The minimum feature size that can be patterned using currently available negative photoresists is no less than 1.0 μm. In contrast, currently available positive photoresists can be used to pattern structures as small as 0.25 to 0.3 [mu] m in size. As a result, positive photoresists are typically used to pattern small scale structures. Thus, hereinafter, the term "photoresist" is indicated identically to "positive photoresist" unless otherwise specified.

To expose the photoresist, ultraviolet light is passed through a reticle mask having a desired pattern formed on the reticle mask. The pattern of the reticle mask consists of opaque and transparent areas, ie dark areas and clear areas. The photoresist below the clear area of the reticle is exposed to uv light, while the photoresist below the dark area of the reticle mask remains unexposed.

Thus, uv light is transmitted through the clear area of the reticle mask, including the dark area, to form a single window in the photoresist, ie the positive photoresist. The clear area is surrounded by the rock area. As a result, such reticle masks are commonly referred to as dark field reticles.

It develops by exposing the photoresist just below the clear area of the dark field reticle. Thus, the layer of material underlying the photoresist is exposed to the next treatment to form an open like shape. For example, in order to etch the contact openings on the oxide formed under the positive photoresist, a dark field reticle is used to develop the openings or windows of the photoresist for subsequent etching of the oxide. The photoresist with the formed window serves as a mask. The windows of the photoresist have a size, shape and location substantially the same as the size, shape and location of the contact openings formed in the oxide.

In contrast, the patterned segment of the photoresist (instead of the window of the photoresist) may pattern the photoresist to have a size, shape, and location that is substantially the same as the size, shape, and location of the shape formed within the sublayer of material. Patterned segments of the photoresist are formed to protect the underlying layer (eg oxide) of the material from subsequent processing (eg etching). The patterned segment of the photoresist is depicted by the dark area of the reticle mask including the clear area. The dark area of the reticle mask is surrounded by the clear area of the reticle mask. As such, such a reticle mask is commonly referred to as a clear field reticle.

The photoresist immediately below the dark area of the reticle mask, ie the positive photoresist, is not exposed to ultraviolet light and is not developed. Thus, the layer of material under the photoresist is protected during the next treatment, allowing some form to form in the underlying material. For example, a clear field reticle is used to form any shape in the polysilicon layer formed under the positive photoresist. The dark area in the clear field reticle (ie, the reticle mask) prevents the photoresist immediately below it from developing, forming a patterned segment of the photoresist that protects the layer of material underneath the photoresist from subsequent processing.

As device geometries become smaller, window fabrication of photoresists becomes increasingly difficult due to the physical limitations of the small clear areas of the dark field reticles used to form the windows. For small windows, the width of the clear area of the dark field reticle is therefore small. As a result, insufficient amount of light passes through such a small clear area of the reticle mask. Thus, Fidelity between the pattern of the dark field reticle and the resultant pattern formed in the photoresist is degraded. For example, a dark field reticle that creates a rectangular contact / via opening instead may create a rounded contact / via opening.

A conventional solution to the problem of insufficient transmission of light through the dark field reticle is to over expose the photoresist. To overexpose the photoresist, either increase the intensity of the uv source or expose the photoresist for longer periods of time. Typically, in order to overexpose the photoresist, the photoresist is exposed for a longer time.

Overexposure of the photoresist is an acceptable solution when using dark field reticles to pattern contact / via openings, with each contact / via opening having the same size. However, such a solution, if both small and large windows can be formed on the same photoresist mask, for example a single photoresist mask not only forms a metal line in a predetermined length, width and shape, but also 0.5 Inappropriate when patterning two contact / empty openings smaller than [mu] m. (As used herein, the term “metal line” refers to the conductive line used to electrically connect the device on the same level). The clear area of the dark field reticle, which exhibits small contact / empty openings, limits light throughput. In contrast, the clear area of the dark field reticle, which represents a larger metal line, does not conversely limit throughput. As a result, the overexposure of the photoresist causes too much light to pass through the larger clear area of the dark field reticle and the pattern is distorted. The fidelity between the pattern of the dark field reticle and the composite pattern formed in the photoresist is degraded. The window of the photoresist becomes large, but the remaining photoresist is smaller than intended. Rounding of edges or corners of the photoresist may also occur.

Throughput of uv light when representing small-scale structures with a clear field reticle used to create patterned segments of photoresist having a size, shape, and location substantially the same as the size, shape, and location of the shapes formed in the sublayer of the material. There are very few problems with. For masks consisting of such patterned segments of photoresist, the small scale structure is represented by the small dark area of the clear field reticle opposite the small clear area of the dark field reticle. To form a mask consisting of such patterned segments of photoresist, uv light is transmitted through a large clear area surrounding the small dark area of the clear field reticle. Thus, a significant amount of light is achieved to adequately expose the photoresist without resorting to overexposure techniques. The photoresist, ie, the window of the positive photoresist, may be determined to be more difficult to manufacture than the patterned segment of the photoresist or the patterned segment of the photoresist when the size of the window is small (≦ 0.5 μm). As a result, the contact / via openings and metal lines are better formed with a mask consisting of patterned segments of the photoresist than a mask consisting of windows formed in the photoresist.

(In principle, negative photoresists can be used to form contact / via openings and metal lines with clear field reticles. However, as described above, it is necessary to define a small structure, i. Negative photoresist for use is not available.)

Forming small structures such as contacts / via openings and metal lines using patterned segments of positive photoresist having a size, shape and location substantially the same as the sizes, shapes and locations of the contacts / via openings and metal lines. The method is known in the art. For example, U.S. Patent No. 5,283,208, issued February 1, 1994, describes one method whereby a mandrel or sacrificial stud, ie, a block of material with nearly vertical sidewalls, is described. It is formed around. The size and location of this mandrel is indicated by the patterned segment of the photoresist. The mandrel is removed, leaving a cavity in the insulating layer. These cavities are filled with materials that will form the desired structure. The cavity in the insulating layer may be filled with a metal plug or metal line. As such, the mandrel defines the size and location of the metal plug or metal line represented by the patterned segment of the photoresist as described above. Thus, the metal plug or metal line is marked with a clear field reticle. However, this method is complicated by the requirement for the sacrificial material layer to form the mandrel.

Accordingly, there is a need for an alternative method of forming metal lines and contact / via openings using clear field reticles to solve the above problems.

FIELD OF THE INVENTION The present invention generally relates to the fabrication of small scale structures (sizes of less than 0.5 μm) such as contacts, biases and metal lines used in integrated circuits formed on semiconductor substrates, in particular when forming such small structures It is about how to make (clear field reticle) available.

The drawings described herein are understood to be reduced except as noted. Moreover, the drawings only illustrate some of the integrated circuits manufactured in accordance with the present invention.

1 to 8 are cross-sectional views at various stages in the processing of a semiconductor substrate according to the present invention;

1 illustrates a conventional semiconductor structure before performing first masking and etching.

2 shows the structure after exposing and developing the first layer of photoresist.

3 illustrates the steps in a layer of oxide formed by etching an oxide.

4 shows the structure after removing the first layer of photoresist.

5 shows a second layer of photoresist formed on an oxide layer.

6 shows a second layer of photoresist after etching to expose the step.

7 shows the openings formed in the layer of oxide by etching the oxide.

8 shows the structure after removing the second layer of photoresist and filling the openings with metal.

According to the invention, a mask comprising a patterned segment of photoresist formed from a first layer of photoresist using a clear field reticle to pattern each opening having a size, shape and location of a layer of material formed on a semiconductor substrate. A method of forming is provided. This way,

(1) forming a first layer of photoresist on a layer of material formed on a semiconductor substrate,

(2) a clear area for directing light onto a portion of the first layer of photoresist that will be an exposed area, and a dark area for not exposing a portion of the first layer of photoresist that will be an unexposed area Exposing a first layer of photoresist by transmitting light through a clear field reticle having a non-exposed area, the unexposed area being substantially the same size, shape and location as the size, shape and location of the openings formed in the layer of material. Exposing the first layer of photoresist having a location,

(3) developing the first layer of photoresist to remove the exposed areas of the first layer of photoresist, wherein the unexposed areas remain intact, forming patterned segments of the photoresist, Each patterned segment having a size, shape and location substantially the same as the size, shape location of the openings formed in the layer of material,

(4) etching a layer of material to form one step directly below each patterned segment of photoresist that acts as a mask during etching, each step being of the size, shape, and shape of one opening formed in the layer of material; Having substantially the same size, shape and position as the position,

(5) removing the first layer of photoresist,

(6) exposing each step in the layer of material by removing a portion of the layer of planarizable material over the layer of material;

(7) etching the layer of material to form openings therein, wherein the layer of planarizable material consists of acting as a mask during etching.

After etching the layer of material to form each opening therein, the layer of planarizable material may be removed. Such openings may be filled with metal to form contacts, biases or metal lines. If the openings are filled with metal, the layer of material is a dielectric such as an oxide, nitride or polyimide.

The present invention provides a method of manufacturing a small scale structure to be employed in an integrated circuit formed on a semiconductor substrate. (Small structure means a structure of 0.5 µm or less in size, such as contacts, bias, and metal lines.)

The method of the present invention improves the resolution of patterned features, such as contacts or biases, in a layer of material.

As mentioned above, for small scale structures, the openings or windows of the photoresist are more difficult to form than the patterned segments of the photoresist. In the method of the invention, a clear field reticle is used to form patterned segments of each photoresist having a size, shape and location substantially the same as the size, shape and location of one feature formed in the layer of material. . This method is used instead of using a dark field reticle that forms a window of each photoresist having a size, shape and location substantially the same as the size, shape and location of a feature formed in the layer of material. As a result, there is no restriction to pattern small windows of the photoresist. Thus, the method of the present invention improves the accuracy in forming such small scale structures.

Other objects, features and advantages of the present invention will become apparent with reference to the following detailed description and the accompanying drawings, in which like reference characters designate the same features.

Reference will now be made in detail to certain embodiments of the invention, which illustrate the best mode by the inventors for carrying out the invention. In addition, alternative embodiments are described as easily as applicable.

The present invention provides a method for producing small scale structures (structures of 0.5 [mu] m or less in size, such as contacts, bias and metal lines) to be employed in integrated circuits formed on semiconductor substrates. Typically, a positive photoresist (hereinafter referred to as a photoresist) is used to limit the small scale structure.

The method of the present invention employs image reversal technology to obtain improved feature resolution. To form the feature in the layer of material, a clear field reticle is used to form the patterned segment of the photoresist. Each of the segments has a size, shape, and location substantially the same as the size, shape, and location of a patcher formed in the layer of material. This method is used in place of the dark field reticle that forms a window in the photoresist, each of the windows having a size, shape and location substantially the same as the size, shape and location of a feature formed in the layer of material. The clear field reticle produces an image or pattern on the surface of the substrate that is negative (ie, reverse) of the image generated by the dark field reticle. Image reversal means that the clear field reticle is used to form a pattern with a reverse image instead of the dark field reticle.

A mask consisting of patterned segments of each photoresist having a size, shape, and location substantially the same as the size, shape, and location of one feature formed, such that a small structure, such as a small contact / empty opening, provides a small It is indicated by the small opacity or dark area of the clear field reticle opposite the clear or clear area. In order to form patterned segments of the photoresist, uv light is transmitted through a large transparent area surrounding a small dark area of the clear field reticle. Thus, sufficient light is achieved to adequately expose the photoresist without resorting to overexposure techniques.

In particular, the method utilizes a clear field reticle that will form a mask adapted to pattern openings in a layer of material formed on a semiconductor substrate. The patterned segment of the photoresist protects the underlying layer of the material (eg, oxide) from subsequent processing (eg, etching). The patterned segment of the photoresist is represented by the dark area of the clear field reticle that prevents a portion of the photoresist from being exposed to ultraviolet light and is unshaped. According to the present invention, each opening in the layer of material has a size, shape and location substantially the same as one patterned segment of the photoresist.

The method of the present invention,

(1) forming a first layer of photoresist on a layer of material formed on a semiconductor substrate,

(2) a clear area for directing light onto a portion of the first layer of photoresist that will be an exposed area, and a dark area for not exposing a portion of the first layer of photoresist that will be an unexposed area Exposing a first layer of photoresist by transmitting light through a clear field reticle having a non-exposed area, the unexposed area being substantially the same size, shape and location as the size, shape and location of the openings formed in the layer of material. Exposing the first layer of photoresist having a location,

(3) developing the first layer of photoresist to remove the exposed areas of the first layer of photoresist, wherein the unexposed areas remain intact, forming patterned segments of the photoresist, Each patterned segment having a size, shape and location substantially the same as the size, shape location of the openings formed in the layer of material,

(4) etching a layer of material to form one step directly below each patterned segment of photoresist that acts as a mask during etching, each step being of the size, shape, and shape of one opening formed in the layer of material; Having substantially the same size, shape and position as the position,

(5) removing the first layer of photoresist,

(6) depositing a layer of planarizable material, eg, a second layer of photoresist, on the layer of material,

(7) exposing each step in the layer of material by removing a portion of the layer of planarizable material over the layer of material;

(8) etching the layer of material to form openings therein, wherein the layer of planarizable material consists of acting as a mask during etching.

For small scale structures, the windows of the photoresist are more difficult to form than the patterned segments of the photoresist. As a result, the contacts / via openings and metal lines formed rather than the mask containing the windows of each photoresist having a size, shape and location substantially the same as the sizes, shapes and positions of the contacts / via openings and metal lines to be formed. The contact / empty openings and metal lines are better formed with a mask comprising patterned segments of each photoresist having a size, shape, and location substantially the same as the size, shape, and location. Using a clear field reticle to form a mask containing patterned segments of the photoresist removes the restriction of patterning small windows of the photoresist using the dark field reticle. Thus, the method of the present invention using a clear field reticle to form a mask comprising patterned segments of photoresist improves the accuracy of forming such small scale structures.

In the manufacture of a semiconductor integrated circuit, a doped region 10 is formed in the major surface of the semiconductor substrate 12 or in an epitaxial layer formed thereon (not shown) as shown in FIG. An oxide region, such as field oxide 14, is formed to isolate one device from another.

If such a device is limited to various masking, etching, doping, oxide forming steps, etc., it is necessary to insulate the devices from each other to form interconnects, for example metal interconnects, to provide a conductive path to an external circuit.

Typically, the interconnects are formed, followed by a layer of dielectric or patternable material 16 covering all lower conductive regions and field oxide 14 to prevent shorting to the interconnects. Such lower conductive regions may include polysilicon that may be used in the formation of doped regions 10 and gate control regions in semiconductor substrates, such as, for example, source / drain regions. Dielectric layer 16 is referred to as a first interlayer dielectric.

The method of the present invention begins with the formation of such dielectric layer 16. Dielectric layer 16 consists of an oxide, referred to herein as an oxide layer. This oxide layer 16 is formed to a conventional thickness employed in this technique by conventional processes. Preferably, oxide layer 16 is planarized. Such planarization can be accomplished by etch back or polishing. Such polishing may include chemical mechanical polishing.

According to the present invention, the mask comprising the patterned segments of the photoresist exhibits a preferred pattern to be transferred to the oxide layer 16. In particular, the first layer 18 of photoresist is formed on the layer 16 of oxide. The first layer 18 of photoresist is exposed and developed to form a pattern therein. In particular, uv light is transmitted through a reticle mask, ie a clear field reticle, having a clear area and a dark area representing a pattern to be formed in the first layer 18 of the photoresist. The clear area is transparent while the cancer area is opaque. Thus, a portion of the first layer 18 of photoresist below the clear area is exposed, resulting in an exposed area, such as the area 20 shown in FIG. A portion of the first layer of photoresist below the dark area is not exposed, resulting in an unexposed area, such as area 22 shown in FIG. According to the present invention, the unexposed regions 22 have a size, shape and position substantially the same as the size, shape and position of the features formed in the oxide layer 16. The exposed area 20 of the photoresist layer 18 is developed. The unexposed areas, ie the area 22, remain intact.

Once patterned, the first layer 18 of photoresist (hereinafter referred to as a patterned segment of the photoresist) serves as a mask. As described above, the patterned segment of photoresist 18 protects the underlying layer of material, ie oxide layer 16, from subsequent processing corresponding to the etching of the oxide layer.

As described above, the patterned segment of photoresist 18 is represented by the dark area of the clear field reticle. To form a patterned segment of photoresist 18, uv light is transmitted through the clear area that surrounds the dark area of the clear field reticle. When the structure to be patterned in the oxide layer 16 is small, the dark area of the clear field reticle is small compared to the clear area. Thus, sufficient light is achieved to adequately expose the photoresist without resorting to overexposure techniques.

2 illustrates one patterned segment of the formed photoresist 18. While such a patterned segment of photoresist 18 is shown, it is readily apparent to those skilled in the art that in practice a number of such patterned segments of photoresist are formed. The patterned segment of photoresist 18, such as the patterned segment of photoresist shown in FIG. 2, serves as a mask for the next pattern of oxide layer 16. In general, patterned segments of photoresist 18 reside on the region of oxide layer 16 where interconnects or other small scale structures are formed. The size of the patterned segment of photoresist 18 may be less than about 0.5 μm without requiring overexposure of the photoresist.

Oxide layer 16 is etched to form multiple steps therein, such as step 24 shown in FIG. Although one such step shown is formed in oxide layer 16, it is readily apparent to one skilled in the art that many such steps are formed. This step is formed under the patterned segment of photoresist 18 which protects the bottom of oxide layer 16 from etching. As a result, it serves as a mask during the patterned etching of photoresist 18. In accordance with the present invention, step 24 has a size, shape, and location substantially the same as the size, shape, and location of the features formed within oxide layer 16.

The patterned segment of photoresist 18 is then removed. 4 shows step 24 of oxide layer 16 after removing the patterned first layer of photoresist 18.

A layer of planarizable material 26 is formed over oxide layer 16. In one embodiment of the present invention, the layer of planarizable material 26 includes a second layer of photoresist. The thickness of the second layer of photoresist 26 preferably covers step 24 sufficiently as shown in FIG. 5. Preferably, the second layer of photoresist 26 has a surface that is nearly flat or planar as can be achieved with spin-on photoresist. After deposition, the spin-on photoresist dries out and spreads out smoothly.

The preceding step, ie, removing the patterned segment of photoresist 18 subsequent to etching the oxide layer 16, helps to provide a second planarized layer of photoresist 26. By depositing a second layer of photoresist 26 over step 24 having a patterned segment of formed photoresist 18, the second layer of photoresist is prevented from being evenly flattened above the step.

As shown in FIG. 6, the second layer of photoresist 26 is planarized by etch back so that step 24 of oxide layer 16 is exposed.

The exposed oxide is etched to form openings 28 in oxide layer 16 as shown in FIG. While one such opening 28 is shown formed in the oxide layer 16, it is readily apparent to those skilled in the art that in fact many such openings are formed. The second layer of photoresist 26 serves as an etch mask during the etching of oxide layer 16. Thus, the etching process selectively etches oxide layer 16 and does not etch the second layer of photoresist 26. According to the present invention, the opening 28 has a size, shape, and position represented by a patterned segment of the photoresist 18 represented by the dark area of the clear field reticle.

In this processing step, the second layer of photoresist 26 is removed and the openings 28 are filled with a material such as metal to form the interconnects 30 as shown in FIG. Examples of metals suitably used in practicing the present invention include tungsten and aluminum. Titanium and titanium tungsten may also be used to form interconnects 30. However, metallization used in interconnect 300 is conventional and does not form any part of the present invention.

The method of the present invention is not limited to etching the openings 28 in the oxide layer 16. The method of the invention is used to pattern features of oxides and other materials so that oxide layer 16 is broadly referred to herein as a layer of material. Other dielectrics as well as other materials such as metals and semiconductors may also be patterned.

In an alternative embodiment, the second layer of photoresist 26 is not used to cover step 24. Rather, a layer of photoresist and other planarizable material 26 as described below is used.

This process flow is the same as described above throughout the etching of the step of the oxide layer 16 and the removal of the patterned segment of the photoresist 18. 4 shows step 24 of oxide layer 16 at this stage in processing. In this alternative embodiment, a layer of planarizable material 26 is formed on oxide layer 16. According to the second layer of photoresist 26, the thickness of the layer of planarizable material 26 preferably covers step 24 sufficiently as shown in FIG. 5.

The layer of planarizable material 26 is planarized by etch back or polishing so that step 24 of oxide layer 16 is exposed as shown in FIG.

Preferably, the layer of planarizable material 26 is planarized by polishing. Unpolished spin-on photoresists are flattened on the local area, for example when dried. In addition, the spin-on photoresist does not flatten when formed over too large holes and / or features. In contrast, polishing allows the layer of planarizable material 26 to be evenly flattened over larger areas as well as larger holes and / or features. Thus, polishing causes the layer of planarizable material 26 to be evenly flattened over step 24. Polishing can include chemical mechanical polishing.

As discussed above, the exposed oxide is etched to form openings 28 in oxide layer 16 as shown in FIG. The planarizable material layer 26 acts as a mask during etching of the oxide layer 16. As a result, the etching process selectively etches oxide layer 16 and does not etch planarizable material layer 26. Thus, any material that is both planarizable by etch back or polishing and that withstands the etchant used to etch the layer 16 of material may be used as the layer of planarizable material 26. In this case, oxide layer 16 is a layer of material. Thus, the layer of planarization material 26 must withstand the etchant used to etch the layer 16 (oxide layer) of material. As a result, the layer of material 16 (oxide layer) is selectively etched with respect to the layer of planarizable material 26.

Optionally, the layer of planarizable material 26 consists of an oxide that can be polished, and the layer 16 of material consists of a nitride, for example BN (boron nitride. The boron nitride can optionally be etched with respect to the oxide. Other planarizable materials suitably used may be used in the methods of the present invention One example of other planarizable materials suitably used in the methods of the present invention includes polysilicon Layer 16 of material is an oxide; When made, polysilicon may also be used as a layer 26 of planarizable material. Polysilicon is also planarized by polishing.

In addition, polyimide may be used as the layer of planarizable material 26 when layer 16 of material is made of oxide. The polyimide may be flat upon deposition and etched back to expose step 24. Conversely, the oxide is also used as a layer of planarizable material 26, and layer 16 of material consists of polyimide. As mentioned above, the oxide is planarized by polishing.

In this processing step, the layer of planarizable material 24 is removed and the opening 28 is filled with a material, such as a metal, to form the interconnect 30 as shown in FIG. 8. As mentioned above, examples of metals suitably used in practicing the present invention include tungsten and aluminum. Titanium and titanium tungsten may also be used to form interconnects 30. Metallization used in interconnects 30 is conventional and does not form any part of the present invention.

As mentioned above, the method of the present invention is not limited to the etching of openings 28 in dielectric layer 16, in particular oxide layer 16. Other dielectrics as well as other materials such as metals and semiconductors may also be patterned. In either case, however, the layer 26 of planarizable material, which may be the second layer 26 of the photoresist, must withstand the etchant used to etch the layer 16 of material.

The present invention is readily applicable to defining small scale structures such as contact / via openings and metal lines. The method of the present invention can be applied to future 0.25 μm technology.

The method of the present invention to form small scale structures of 0.5 micrometers or less in size, such as contacts, bias and metal lines, can be used to fabricate all ultrafine IC technologies.

The foregoing description of the preferred embodiment of the present invention has been provided for the purposes of illustration and illustration. The invention is not limited to the form described above. Those skilled in the art can make various changes. Various modifications of the membranes and materials are possible. The invention may be practiced in other fabrication techniques in MOS or bipolar processes.

Likewise, certain process steps described may be exchanged with other steps to achieve the same result. The embodiments are selected and described in order to best explain the principles of the invention and its practical application, so that those skilled in the art can understand the invention for various modifications and various embodiments as appropriate to a particular use. The scope of the invention is defined by the claims appended hereto.

Claims (10)

A photo formed from the first layer of photoresist 18 using a clear field reticle to pattern each opening 28 having the size, shape and position of the layer 16 of material formed on the semiconductor substrate 12. A method of forming a mask comprising patterned segments of resist 18, (1) forming a first layer of photoresist 18 on layer 16 of material formed on semiconductor substrate 12, (2) a clear area for directing light onto a portion of the first layer of photoresist 18 that will be the exposed region 20 and the photoresist 18 that will be the unexposed region 22. Exposing the first layer of photoresist 18 by transmitting light through a clear field reticle having a dark area that does not expose a portion of the first layer, wherein the unexposed region 22 is a layer of material. Exposing a first layer of photoresist having a size, shape, and location substantially the same as the size, shape, and location of the openings 28 formed in (16), (3) removing the exposed area 20 of the first layer of the photoresist 18 by developing the first layer of the photoresist 18, wherein the unexposed area 22 remains intact and the photo Forming a patterned segment of resist 18, each patterned segment of photoresist 18 being substantially the same size, shape, and size as the size, shape, and location of openings 28 formed in layer 16 of material; Having a position, (4) etching a layer of material 16 to form one step 24 directly below each patterned segment of the photoresist 18 which acts as a mask during etching, wherein each step 24 is Having a size, shape and location substantially the same as the size, shape and location of the opening 28 formed in the layer 16 of material, (5) removing the first layer of photoresist 18, (6) depositing a layer 26 of planarizable material on the layer 16 of material, (7) exposing each of said steps 24 in layer 16 of material by removing a portion of layer 26 of planarizable material, (8) forming an opening 28 therein by etching the layer of material 16, wherein the layer 26 of planarizable material consists of acting as a mask during etching. Way. The method of claim 1, Removing a portion of the layer (26) of planarizable material is accomplished by etch back or polishing. The method of claim 2, Removing a portion of the layer of flattenable material (26) causes the layer of flattenable material (26) to be flattened. The method of claim 1, And a layer (26) of said planarizable material is removed after etching said layer (16) of said material to form said openings (28) therein. The method of claim 1, The layer of material (16) is selected from the group of materials consisting of oxides, boron nitrides and polyimides. The method of claim 1, And the layer (26) of planarizable material is selected from the group of materials consisting of photoresist, polysilicon, polyimide and oxide. The method of claim 6, And the layer (26) of planarizable material comprises a second layer of photoresist (26). The method of claim 7, wherein Removing a portion of the second layer of photoresist (26) is accomplished with an etch back. The method of claim 1, At least one of said openings (28) is filled with a metal. The method of claim 1, The layer 26 of planarizable material is formed on the layer 16 of the material in step 6 such that the layer 26 of the planarizable material covers each said step 24 of the layer 16 of the material. Mask deposition method, characterized in that deposited on.