KR100414153B1 - Clock timing recovery circuit and Method for DMT system - Google Patents

Abstract

According to the present invention, a decision-directed method is used to obtain an initial timing clock error by repeatedly transmitting a prefix (pre-committed symbol) in an individual multi-tone system, and then correcting the error using the determined data value for the residual error. The present invention relates to a clock timing recovery circuit for tracking and restoring using a method and a clock timing recovery method.

Description

Clock timing recovery circuit and method for DMT system

The present invention relates to a clock timing recovery circuit that repeatedly sends a prefix (pre-committed symbol) in an individual multi-tone system to find an initial timing error at the beginning of data reception, and then tracks and recovers residual errors using a decision-oriented method. will be.

As the importance and utilization of high speed data communication gradually increase, interest in multi-carrier systems has increased greatly, which has been recently used in various types of digital subscriber networks and high speed local area networks. In general, individual multi-tone communication systems have the advantage of being robust to inter-symbol interference due to multipath delay attenuation, while being very sensitive to timing errors. To compensate for this problem, various methods for correcting timing errors have been proposed.

These methods can be divided into two types, synchronous and asynchronous. The synchronous method is a method of directly adjusting the sampling clock of an analog signal using a phase-locked loop (PLL) by obtaining a timing error. The asynchronous method samples a signal in a digital domain using a fixed sampling clock. A method of estimating timing error and interpolating correct timing to correct the timing error.

However, the synchronous method is not used in a high speed communication system because of the complexity of hardware and the difficulty in controlling the phase of sampling quickly for high speed data transmission. As a result, high-speed systems typically use an asynchronous method that uses a fixed sampling clock to correct timing in the digital domain.

Monnier proposed a method for finding sampling error using the same repeated pilot signal. In this case, since the subcarriers for the pilot symbol in the entire band must be allocated separately, the overall data transmission efficiency is lowered and the convergence speed is slow.

1 shows a conventional circuit for recovering timing error using a pilot signal as a circuit using a PLL. The A / D converter 10 converts an analog signal into a digital signal and a signal sample used for FFT processing. An FFT window unit 11 for selecting an image, an FFT unit 12 for converting an input time domain signal into a signal in a frequency domain, and a pilot signal for extracting a pilot signal coming into a predetermined position to obtain information about timing errors. A pilot signal extractor 13, a timing error calculator 14 for calculating error information from the extracted pilot signal, a rounder 15 for dividing the calculated error into an integer part and a fractional part, and the FFT window An FFT window controller 16 for adjusting the position of 11 and a PLL 17 for adjusting the sample frequency of the AD converter.

The phase rotation amount due to the timing synchronization error can be largely divided into a phase error caused by a position error of the FFT window 11 and a phase error caused by a sampling clock error.

The conventional monaural scheme calculates phase error and sampling clock errors using the same pilot signal that is repeated. By adding a constant pilot signal to the same subcarrier position and extracting a phase difference between two symbols, a clock error can be obtained and a phase error can be found by a relationship between two pilot signals in one symbol. In this case, the pilot is signaled at a certain position on the symbol. The amount of phase rotation occurring in the k-th subcarrier of the j-th symbol may be expressed as in Equation (1).

In Equation 1, T _d represents an FFT error and Δt _j represents a sampling timing error. T _u represents the entire _duration of the symbol. By using this , an approximate sampling error can be obtained by calculating the amount of phase rotation between two samples k ₁ and k ₂ on one symbol. This is expressed as an equation (2).

When the timing synchronization error normalized through Equation 2 is obtained, Equation 3 is obtained. Equation 3 is obtained by a predetermined number of subcarriers of Equation 3 and then averaged.

At this time, the timing error taken as the average value is divided into the integer part and the fractional part, and the integer part is adjusted to add or subtract a sample by the adjustment of the FFT window, and the other fractional part is corrected by using a PLL or a phase rotor. At this time, a circuit such as a rounder is necessary to limit the range of the fractional part to within ± 0.5.

The conventional correction circuit has compensated by extracting pilot signals and using the information obtained therefrom to adjust the position of the sampling clock directly through window movement or through a PLL or phase rotator. However, in this method, the convergence time to correct the timing error and to the steady state is considerably longer, and compared with the use of the same frequency band, the number of subcarriers that can transmit data decreases as the pilot signal is allocated, thereby reducing the overall efficiency. There was a problem. In addition, it requires periodic sample subtraction, which requires frequent FFT window position adjustment, and in order to reduce the frequency of these adjustments, an accurate device is needed, resulting in a hardware price increase.

Therefore, in order to solve the problems, the present invention does not use a pilot signal to correct the timing error, and transmits a predetermined prefix before data transmission to obtain a timing error, and then tracks the residual error using a decision-oriented method. The value is corrected by using a phase rotator, and thus, unlike the conventional method, it is possible to minimize the size of the hardware, induce quick convergence of errors, and increase frequency efficiency, by not using the subtraction of the sample. There is this.

In order to achieve the above object, the present invention comprises an A / D converter, an FFT unit, an initial timing detector, a hard decision maker, a timing error tracker, an adder, and a phase rotator, and the A / D converter converts an analog signal into a digital signal. ; The FFT unit converts an inputted time domain signal into a frequency domain signal; The initial timing detector calculates and outputs an initial timing error from a slope from a precode of a frequency domain received through an FFT unit; The hard determiner detects the transmitted information based on the output value of the phase rotator; The timing error tracker obtains a residual error from the signals after hard decision of the hard judge; The adder obtains an error by adding a value output from the initial phase detector and a residual error obtained from the timing error tracker; The phase rotator is characterized in that the clock timing recovery circuit for the individual multi-tone system, characterized in that for correcting the phase using the obtained error.

1 is a block diagram showing a timing recovery circuit using a conventional PLL and a pilot signal.

2 is a block diagram showing a timing error recovery circuit according to the present invention;

3 is a graph showing the amount of timing error as an increase in phase according to subcarriers.

4 is a block diagram illustrating an initial timing error detector circuit in accordance with the present invention.

5 is a block diagram showing a phase rotator and a residual timing error tracking circuit according to the present invention.

<Description of Symbols for Main Parts of Drawings>

10,20: A / D Converter 11: FFT Window

12,21: FFT unit 13: pilot signal extractor

14: timing error calculation unit 15: rounding machine

16: FFT window controller 17: PLL

22: phase rotation machine 23,41: hard decision machine

24: Initial Timing Detector 25: Timing Error Tracker

31: one symbol delay stage 32: complex conjugate

33,42: Phase Detector 34,43: Average Calculator

35: tilt detector 44: tilt update unit

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 shows a circuit for calculating a timing error according to the present invention, which includes an A / D converter 20 for converting an analog signal into a digital signal, and an FFT for converting an input time domain signal into a frequency domain signal. And an initial timing detector 24 for calculating an initial timing error from the phase error slope between symbols from a pre-signal in the frequency domain received through the FFT section, and based on an output value of the phase rotator. Using the hard decision device 23 for detecting information, the timing error tracker 25 for obtaining residual errors from the signals after the hard decision, and the slopes obtained from the initial timing detector 24 and the error obtained through the timing error tracker 25. And a phase rotator 22 for correcting phase.

The initial timing detector 24 includes a symbol delay stage 31 for delaying the precode input as shown in FIG. 4, and a complex conjugate portion 32 for obtaining a complex conjugate component of the signal delayed at the delay stage. ), A multiplier for calculating the phase difference between the precode and the delayed precode, a phase detector 33 for detecting a phase from the result of the multiplication, an average calculator 34 for calculating an average value from the detected phase, and a calculation. A tilt detector 35 for extracting the slope from the averaged value. The illustrated initial timing detector 24 interprets the input prefix and outputs the initial timing error as the phase slope of each subcarrier.

Since the precode has the property of repeating the same symbol, the subcarrier in the current symbol is repeated after one symbol is delayed. Using this property, the phase difference between two prefixes can be obtained. In addition, the product of the signals passed through the complex delay unit 32 through the symbol delay end 31 and the input precode includes a phase error value of the subcarrier signal, and the phase error value is generated as a product of two values. Included in the phase of the complex signal. This is shown in equation (5). k is the subcarrier number and m is the symbol index and is increased by the number of prefixes. The phase of the transposition code is detected through the output of the phase detector 33 which detects this phase.

After obtaining the phase difference for each subcarrier component of the two prefixes as described above, if there are two or more prefixes, the phase difference between each prefix is averaged. The output is the average phase error value of each subcarrier.

Next, the slope detector 35 calculates a slope through the input data value. The effect in the frequency domain according to the initial phase error is shown as a result of increasing linearly with frequency as shown in Figure 3, in this case, the slope is proportional to the initial phase error τ as shown in equation (6).

In Equation 6, 1 / T represents an interval between carriers, τ represents delay information due to a phase error, and k represents a subcarrier number.

The phase value is corrected using the obtained slope as described above, and the clock timing error of the incoming data symbol is compensated inversely by using the phase rotator 22 as the product of the subcarrier number and the slope as a phase and described later. By interlocking with the residual error tracking circuit described in Fig. 5, the error is corrected.

Referring to the operation of the circuit once again, the one symbol delay stage 31 delays the signal to multiply the pre-signal before one symbol period, and provides a complex conjugate signal of the delayed signal passed through the complex conjugate 32. Extract and multiply the transpose code input through the multiplier, and obtain the phase using the phase detector 33 from the multiplied result. The average is calculated using the average calculator 34 from the obtained phase, and the slope of the final straight line obtained by using the slope detector 35 is fixed at the end of the precoding, and the clock timing error of the incoming data symbol is phased. The rotor 22 is used to compensate for the reverse by taking the product of the subcarrier number and the slope as a phase and simultaneously correct the error by interworking with the residual error tracking circuit, which will be described later with reference to FIG. 5.

Instead of using the pilot symbol repeated for each symbol, it is possible to estimate a relatively accurate magnitude of the clock timing synchronization error by sending a predetermined symbol repeatedly several times before sending actual information data. To make it possible. This method has the advantage that the convergence speed of the error is faster than the conventional method of finding the timing error using the pilot. The initial phase error is determined by obtaining a phase error between signals at the same subcarrier position between repeated symbols as shown in Equation (5).

The error of each subcarrier is calculated during repeated transposition, and the average of each subcarrier is calculated during the transposition. From the average values obtained, a slope detector (curve fitter) is used to calculate the slope to be expressed by a general formula. At this time, the phase rotation amount due to the timing error on the symbol can be represented by a simple linear function proportional to the subcarrier number as shown in Equation 6, and thus can be expressed in the form shown in the graph shown in FIG.

5 is a circuit diagram illustrating a residual error tracker and a phase rotator according to the present invention. Small residuals caused by inaccuracies in the initial phase detected by the initial timing detector do not affect the first few symbol reconstructions, but if they accumulate continuously, they are likely to be impossible to recover. Needs to be. How much error remains is determined through the same process as in Equation 6 and at the same time, the phase error is obtained by using a complex complex product of the determination signal and the signal before determination. Equation 7 shows an expression for the residual error obtained through the residual error tracking circuit. Y denotes a signal before determination and D denotes a signal after determination.

Then, the average of the errors occurring during one symbol is calculated according to Equation (7). The initial value of the slope compensated for the first data is based on the initial slope from the slope detector, after which the average of the residual errors obtained by the tracking circuit is multiplied by a constant convergence constant to update the currently used slope. The slope to be applied during the symbol is obtained. The updated slope is applied from the next symbol. Equation 8 shows this updating process and α represents the convergence constant. This value may have a different value depending on the specification of the communication system to be applied.

The timing error is corrected by performing a process of compensating the final slope obtained in this way inversely to the signal using Equation (9).

FIG. 5 is a schematic diagram of a tracking circuit, and the tracking circuit detects a phase from a conjugate product of a signal before and after the determination of a symbol that has already been corrected through a phase rotor at a current slope. It consists of a phase detector and an average calculator of an integrated dump (ID) method that calculates an average of one symbol of the calculated phase. Also, an updated slope to be applied to the next symbol is calculated through a slope update unit that updates the slope with a constant convergence constant.

The present invention reduces the hardware implementation cost by using a fixed clock and eliminates the subtraction of the sample, and increases the convergence speed compared to the system using the pilot. In addition, when using the same number of subcarriers, compared to the case of using a pilot signal, there is an advantage that the frequency carrier can be increased because the subcarriers allocated to the pilot can be used for data transmission.

Claims (4)

It consists of A / D converter, FFT unit, initial timing detector, hard decision maker, timing error tracker, adder and phase rotator. The A / D converter converts an analog signal into a digital signal; The FFT unit 12 converts the input time domain signal into a frequency domain signal; The initial timing detector calculates and outputs an initial timing error as a slope from a precode of a frequency domain received through the FFT unit; The hard determiner detects the transmitted information based on the output value of the phase rotator; The timing error tracker obtains a residual error from the signals after hard decision of the hard judge; The adder calculates an error by adding a value output from the initial timing detector and a residual error obtained from the timing error tracker; And And the phase rotator corrects the phase using the obtained error. The method of claim 1, The initial timing detector includes a symbol delay stage for delaying an input precode; A complex conjugate portion for obtaining a complex conjugate component of the signal delayed in the delay stage; A multiplier for multiplying the transpose signal with a complex conjugated signal; A phase detector for detecting a phase from the result of the multiplication; An average calculator for calculating an average value from the detected phases; And And a slope detector for extracting a slope from the calculated average value. Clock timing for an individual multi-tone system that corrects an initial timing error using a transposition code input to an initial timing detector of the circuit of claim 1 and then recovers the timing residual error using a decision directed method. Restore method. After obtaining the phase error between two adjacent prefixes input to the initial timing detector of the circuit of claim 1, the individual multiple tone system recovers the clock timing by estimating the timing error using the slope of the obtained phase error according to the subcarrier. Clock timing recovery method.