KR100330094B1 - Bias circuit using band gap reference - Google Patents

Abstract

PURPOSE: A bias circuit using a band gap reference is provided to supply a constant voltage and current regardless of temperature and processing conditions by using the band gap reference. CONSTITUTION: A start circuit(1) is used for performing an initial driving operation. The first current mirror portion(3) includes two transistor(Q1,Q2) and a resistance(Rb) connected with the transistor(Q2) in order to generate current(I1) from an external voltage(VCC) and supply a voltage(Vband) to the outside. A current source portion(2) is connected with the first current mirror portion(3) in order to offset a current variation of the first current mirror portion(3) according to a variation of the external voltage(VCC). The second current mirror portion(4) converts the intensity of the current(I1) of the first current mirror portion(3) and transmits the converted current(I2). The third current mirror portion(5) transmits the current(I2) of the second current mirror portion(4) to a vertical line(b6). The fourth current mirror portion(6) transmits the current of the third current mirror portion(5) to a vertical line(b7).

Description

Bias Circuit Using Bandgap Reference

The present invention relates to a bias circuit, and more particularly, to a bias circuit for supplying a constant current and voltage regardless of temperature and process conditions using a bandgap reference (BGR).

In particular, the present invention relates to a bias circuit which is integrated by a CMOS (Complementary Metal Oxide Semiconductor) process and manufactured into one chip.

Typically, a bandgap reference technique is applied to a bias circuit fabricated with CMOS VLSI (CMOS Very Large-Scale Integrated circuit) due to temperature stability.

In addition, the bias circuit using the bandgap reference technique has an independency with respect to the external power supply as compared to the bias circuit with the resistor, and is easy to manufacture by CMOS process. This is because it is very difficult to fabricate the resistor in a CMOS process to have a certain error value.

For reference, a bandgap reference technique has been disclosed in "A Precision Curvature-compensated CMOS Bandgap Reference" (IEEE J. Solid-State Circuits, vol.sc-18, no.6, pp634-643, DEC.1988). .

According to the "A Precision Curvature-compensated CMOS Bandgap Reference", temperature drift is guaranteed at about 13.1 to 25.6 ppm / ° C under normal temperature conditions. This is close to the 10 ppm / ℃ that can be theoretically obtained it can be seen that the excellent temperature characteristics.

Hereinafter, a bias circuit using a general bandgap reference will be described with reference to the accompanying drawings.

1 is a detailed circuit diagram of a bias circuit using a general bandgap reference.

Referring to FIG. 1, an external voltage VCC is applied to the upper ends of five vertical lines a1 to a5.

The capacitor C and the field effect transistors FET1 and FET2 are sequentially connected to the first vertical line a1. The gate terminal of the field effect transistor FET1 is connected to the first vertical line a1 and the drain terminal is connected to the current source of the third vertical line a3. The gate terminal of the field effect transistor FET2 is connected to the current source of the second vertical line a2.

Two transistors Q1 and Q0 are connected to the second vertical line a2 and the third vertical line a3 in which the base end and the collector end of each device are commonly connected to the external power supply VCC. A resistor Ra and a plurality of current sources are connected in series to the emitter terminal of the transistor Q1, and a plurality of current sources are connected in series to the emitter terminal of the transistor Q0.

The fourth vertical line a4 is connected to a transistor Q2 having a base terminal and a collector terminal connected to an external power supply VCC in common, and an emitter terminal of the transistor Q2 has a resistor Rb and a plurality of current sources in sequence. Connected.

The voltage Vband is provided to the outside through the rear end of the resistor Rb, and the non-inverting input terminal of the operational amplifier OP is connected to the rear end of the resistor Rb.

The two transistors Q1 and Q2 of the second vertical line a2 and the fourth vertical line a4 are the same.

A resistor Rc and a field effect transistor FET3 are sequentially connected to the fifth vertical line a5, and an inverting input terminal of the operational amplifier OP is connected to a rear end of the resistor Rc. The current Isource is provided to the outside through the field effect and the drain terminal of the transistor FET3. The output terminal of the operational amplifier OP is connected to the gate terminal of the field effect transistor FET3.

The capacitor C of the first vertical line a1 and the two field effect transistors FET1 and FET2 constitute a start circuit 1 and are a current source connected to the lower ends of the second to fourth vertical lines a2 to a4. These constitute the current source section 2.

Next, the operation of the bias circuit configured as described above will be described.

The start circuit 1 prevents the external voltage VCC from being excessively applied by the capacitor C, and the second vertical line a2 and the third vertical line a3 by the field effect transistors FET1 and FET2. Allow the current source to be driven.

The two transistors Q1 and Q2 of the second vertical line a2 and the fourth vertical line a4 operate as current mirrors, and the current I0 flowing through the collector terminals of the transistors Q1 and Q2. , I1) are the same.

In addition, since the ratio of the resistance values of the two resistors Ra and Rb is designed as a constant, the voltage Vband provided to the outside of the resistor Rb is constant as long as the ratio of the resistance values is constant. That is, since the resistance values of the two resistors Ra and Rb change with a constant ratio with respect to the temperature change, the voltage Vband always has a constant value.

Therefore, in order to obtain the value of the intended voltage Vband, the ratio of the resistors Ra and Rb may be appropriately selected when designing the circuit.

The two transistors Q1 and Q0 of the second vertical line a2 and the third vertical line a3 operate as Widlar current sources. Accordingly, the collector current of the transistor Q0 is determined by the resistance value of the resistor Ra and the amplification degree of the two transistors Q1 and Q2.

The current source unit 2 connected to the lower end of the second vertical line a2 to the fourth vertical line a4 includes a plurality of current sources, and cancels the current change of each line according to the change of the external voltage VCC. It is for.

The voltage Vband is provided externally, and is applied to the non-inverting input terminal of the operational amplifier OP. The operational amplifier OP and the field effect transistor FET3 perform a voltage-current conversion operation.

The field effect transistor FET3 amplifies the output voltage of the operational amplifier OP, and the magnitude of the current I2 flowing through the resistor Rc and the field effect transistor FET3 is determined according to the amplification degree.

The current I2 may have an intended size by appropriately selecting a resistance value of the resistor Rc when designing a circuit. The current 12 is provided externally.

However, in the bias circuit using the general bandgap reference described above, when the resistance value of the resistor Ra or the resistor Rb is changed according to the temperature change, the currents I0 and I1 flowing to each resistor are changed and provided to the outside. The current I2 to be varied.

In addition, since the offset voltage of the operational amplifier OP is not completely temperature independent, a change in the magnitude of the current I2 according to the temperature change is caused.

When the designed bias circuit is fabricated by the CMOS process, the resistors Ra and Rb are made of ordinary well resistors, and the process of forming the well resistors yields an intended 100% accurate resistance value. impossible. As a result, since the resistance values of the two resistors Ra and Rb cannot be made as designed, a change in the magnitude of the current I2 may be caused.

Therefore, an object of the present invention is to provide a bias circuit using a bandgap reference capable of stably supplying current against a process error and a temperature change in order to solve the above-described technical problem.

It is still another object of the present invention to provide a bias circuit using a bandgap reference that does not need to consider a change in offset voltage according to a temperature change by supplying a current without using an operational amplifier.

The present invention for achieving the above object,

A start circuit for performing an initial driving operation;

A first current mirror unit configured to generate current from an external voltage by two transistors each of which the base end and the collector end are commonly connected to an external voltage, and to provide an external voltage generated by a voltage drop due to a resistor connected to the transistor; Wow;

A current source unit connected to a lower end of the first current mirror unit to cancel a current change of the first current mirror unit according to an external voltage change;

Two field effect transistors are connected to each of the two vertical lines, and only the respective gates are connected to each other, thereby converting the magnitude of the current of the first current mirror portion input through one field effect transistor to convert the current to the other field effect and the transistor. A second current mirror unit for transmitting to the camera;

Between the vertical line through which the converted current of the second current mirror portion flows and the other vertical line through which the current is transmitted, a third current for transferring the current transmitted by the second current mirror unit to another vertical line without current conversion. A mirror portion;

Between the vertical line through which the current transmitted through the third current mirror portion flows and the vertical line through which the output current flows, the third current mirror portion transfers the transferred current to the vertical line through which the output current flows without current conversion and provides it to the outside. It consists of four current mirror parts.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.

2 is a detailed circuit diagram of a bias circuit using a bandgap reference according to an embodiment of the present invention.

First, the configuration of the bias circuit according to the embodiment of the present invention will be described with reference to FIG.

Referring to FIG. 2, since the start circuit 1 and the current source unit 2 are the same as those of FIG. 1, description thereof will be omitted.

Transistors Q1, Q0, and Q2 having their respective base and collector terminals commonly connected to the external voltage VCC are connected to the second vertical line b2 to the fourth vertical line b4. The transistors Q1 and Q2 are identical to each other. The resistors Ra and Rb are connected to emitter terminals of the transistors Q1 and Q2, respectively. The transistors Q1, Q0 and Q2 and the resistors Ra and Rb constitute the first current mirror unit 3.

The voltage Vband after the resistor Rb of the fourth vertical line b4 is provided to the outside.

A transistor Q3 having a base terminal and a collector terminal commonly connected to an external voltage VCC is connected to the fifth vertical line b5, and the transistor Q3 is the same as the transistor Q2, and thus the fourth vertical line b4. This is to maintain the symmetry with.

The two field effect transistors MP1 and MP2 are connected in the order of the source terminal and the drain terminal to the rear end of the resistor Rb of the fourth vertical line b4 and the emitter terminal of the transistor Q3 of the fifth vertical line b5. The gate terminal of each of the field effect transistors MP1 and MP2 is connected to each other, and the gate terminal and the drain terminal of the field effect transistor MP1 are connected to each other. The two field effect transistors MP1 and MP2 constitute a second current mirror unit 4.

Two field effect transistors FET8 and FET9 are connected to the drain terminal of the field effect transistor MP2 of the fifth vertical line b5 in the order of the drain terminal and the source terminal, respectively, and the gates of the respective field effect transistors FET8 and FET9. The stage and the drain stage are connected to each other. The field effect transistors FET10 and FET11, in which the gate ends of the field effect transistors FET8 and FET9 are connected to each other, are connected to the sixth vertical line b6 in the order of drain and source. The field effect transistors FET8, FET10 and the field effect transistors FET9, FET11, whose gate ends are connected to each other, are the same. This is the basic property of the current mirror. The four field effect transistors FET8 to FET11 constitute a third current mirror portion 5.

On the other hand, two field effect transistors FET4 and FET5 are connected to the external voltage VCC of the sixth vertical line b6 in the order of the source terminal and the drain terminal, and gate and drain terminals of the respective field effect transistors FET8 and FET9. Are connected to each other. In addition, the field effect transistors FET6 and FET7 having the gate ends of the field effect transistors FET4 and FET5 connected to each other are connected to the seventh vertical line b7 in the order of drain and source. The field effect transistors FET4 and FET6 and the field effect transistors FET5 and FET7 having their gate ends connected to each other are the same. As explained above, this is the basic property of the current mirror. The four field effect transistors FET4 to FET7 constitute a fourth current mirror portion 6.

Next, the operation of the bias circuit using the bandgap reference according to the embodiment of the present invention configured as described above will be described.

The transistor Q1 of the first current mirror unit 3 converts the external voltage VCC into the current I0, and the current 10 is transistor Q2 by the current mirror operation of the two transistors Q1 and Q2. It is represented by the current I1 flowing in the emitter stage of That is, the magnitudes of the two currents I0 and I1 are the same.

When the current I0 flowing through the transistor Q1 is expressed by a formula,

I0 = (1 / Ra) x Vt x 1n (n).

In the above formula, Vt is the value of the threshold voltage of the transistor Q1.

After the resistor Rb of the fourth vertical line b4, a voltage Vband provided to the outside is generated, and the voltage Vband is a voltage obtained by subtracting the voltage drop by the resistor Rb from the external voltage VCC. to be.

The current I1 of the fourth vertical line b4 flows through the field effect transistor MP1, and the current I1 is current-converted by the field effect transistor MP2 to form a fifth vertical line (I2). b5).

At this time, the gate-source voltage Vgs1 of the field effect transistor MP1 is

It is expressed as

In the above formula, Vth1 is the threshold voltage of the preconditioning transistor MP1, S1 is the magnitude of the field effect transistor MP1, and K1 is a constant.

The gate-source voltage Vgs2 of the field effect transistor MP2 is

It is expressed as Vgs2 = Vgs1 + (VCC-Vband).

The gate-source voltage Vgs2 determines the magnitude of the current I2 flowing through the field effect transistor MP2, and the current I2 has the same magnitude as the current Isource provided at the output terminal. Thus, the current Isource provided to the outside from the bias circuit by the two field effect transistors MP1 and MP2 is substantially determined.

Transistor Q3 of fifth vertical line b5 is for maintaining symmetry with fourth vertical line b4, and transistor Q3 and transistor Q2 are identical.

On the other hand, the current change ratio ΔI2 / ΔI1 determined by the field effect transistors MP1 and MP2 of the second current mirror unit 4 has the magnitudes S1 and S2 of the respective field effect transistors MP1 and MP2. It depends on the ratio and the current I1 flowing in the fourth vertical line b4.

Therefore, the current change ratio can be selected by determining the sizes S1 and S2 of the field effect transistors MP1 and MP2. This is chosen in consideration of the magnitude of the output current Isource required in the design of the circuit.

The current I2 flowing in the fifth vertical line b5 is

S2 (Vgs2-Vth2) ² and Vgs = Vgs1 + I1 Substituting Rb,

It is represented by [(Vgs1 + I1Rb) -Vth2] ² .

The change in current I2 with respect to the change in current I1 is

Where α and β are constants,

S1 and S2 are the magnitudes of the field effect transistors MP1 and MP2.

In the design of the circuit, The sizes S1 and S2 of the field effect transistors MP1 and MP2 are determined so as to be satisfied.

The current I2 of the fifth vertical line b5 whose magnitude is converted by the two field effect transistors MP1 and MP2 is formed by the field effect transistors FET8 and FET9 of the third current mirror unit 5 and the field effect transistors ( The current mirror operation between the FETs 10 and FET 11 is transmitted to the sixth vertical line b6 without changing the size.

In addition, the current of the sixth vertical line b6 is set without changing the size by the current mirror operation between the field effect transistors FET4 and FET5 of the fourth current mirror unit 6 and the field effect transistors FET6 and FET7. The seventh vertical line b7 is transmitted, and the current Isource delivered to the seventh vertical line b7 is provided to the outside.

As described above, in the embodiment of the present invention, since the bias circuit according to the embodiment of the present invention can omit the operational amplifier, it is necessary to improve the integration of the circuit and to consider the variation of the offset voltage of the operational amplifier according to the temperature change. There is no.

In addition, since the bias circuit according to the embodiment of the present invention determines the size of the output current I2 according to the size ratio of the two field effect transistors MP1 and MP2, the error of the well resistance forming process is reduced and the temperature change is made. The output current I2 may be provided regardless of the change in the magnitude of the current I1.

1 is a detailed circuit diagram of a bias circuit using a general bandgap reference.

2 is a detailed circuit diagram of a bias circuit using a bandgap reference according to an embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

DESCRIPTION OF SYMBOLS 1 Start circuit 2 Current source part 3 First current mirror part

4: second current mirror portion 5: third current mirror portion 6: fourth current mirror portion

Claims (6)

A start circuit 1 for performing an initial driving operation; Each base and collector terminal generates a current I1 from an external voltage VCC by two transistors Q1 and Q2 commonly connected to an external voltage VCC, and a resistor Rb connected to the transistor Q2. A first current mirror unit 3 which provides a voltage Vband generated by the voltage drop due to the outside to the outside; A current source unit 2 connected to a lower end of the first current mirror unit 3 to cancel a current change of the first current mirror unit 3 according to a change in an external voltage VCC; Two first field effect transistors MP1 and MP2 are connected to two vertical lines b4 and b5, respectively, and gates thereof are connected to each other, so that the first current mirror unit is input through one field effect transistor MP1. A second current mirror unit 4 for converting the magnitude of the current I1 of (3) and transferring the current to the other field effect transistor MP2 as the current I2; Between the vertical line b5 through which the converted current I2 of the second current mirror portion 4 flows and the other vertical line b6 through which the current I2 is transmitted, the second current mirror portion 4 A third current mirror unit 5 for transferring the current I2 delivered by the second vertical line b6 without a current conversion; Between the vertical line b6 through which the transmitted current of the third current mirror unit 5 flows and the vertical line b7 through which the output current Isource flows, the current transmitted from the third current mirror unit 5 is transferred to the current. A bias circuit using a bandgap reference, characterized in that it comprises a fourth current mirror portion (6) for delivering to the vertical line (b7) through which the output current (Isource) flows without conversion. The method of claim 1, The first current mirror unit 3 is The base terminal and the collector terminal are composed of two transistors Q1 and Q2 connected in common to the external voltage VCC and resistors Ra and Rb connected to each emitter terminal, and the two transistors Q1 and Q2 are the same. The bias circuit using a bandgap reference, characterized in that the magnitude of the current (I0, I1) flowing through each emitter stage is the same. The method according to claim 1 or 2, The second current mirror unit 4 is It is composed of two field effect transistors (MP1, MP2) connected to the vertical line (b4) and the vertical line (b5) where the first current mirror portion (3) is located, and the gate ends are connected to each other. A bias using a bandgap reference, which transfers the current I1 of the first current mirror unit 3 to the current I2 of the vertical line b5 corresponding to the size ratio of the effect transistors MP1 and MP2. Circuit. The method of claim 3, In the vertical line b5 to which the second current mirror unit 4 is connected, In order to maintain the symmetry with the vertical line b4, the base end and the collector end are commonly connected to the external voltage VCC, and the same transistor Q3 as the transistors Q1 and Q2 of the first mirror part 3 is added. A bias circuit using a bandgap reference, characterized in that for connecting. The method of claim 1, The third current mirror unit 5 is The drain and source terminals of the two field effect transistors FET8 and FET9 are sequentially connected to the vertical line b5, and the drain and source terminals of the two field effect transistors FET10 and FET11 are connected to the vertical line b6 in order. The gate ends of the field effect transistors FET8 and FET10 are connected to each other, the gate ends of the field effect transistors FET9 and FET11 are connected to each other, and the field effect transistors connected to each other to operate as a current mirror are A bias circuit using a bandgap reference, wherein the same field effect transistor is used. The method according to claim 1 or 5, The fourth current mirror unit 6 is The drain and source terminals of the two field effect transistors FET4 and FET5 are connected in turn to the vertical line b6, and the drain and source terminals of the two field effect transistors FET6 and FET7 are connected in order to the vertical line b7. The gate ends of the field effect transistors FET4 and FET6 are connected to each other, the gate ends of the field effect transistors FET5 and FET7 are connected to each other, and the field effect transistors connected to each other to operate as a current mirror are A bias circuit using a bandgap reference, wherein the same field effect transistor is used.