KR100309641B1 - Bismos memory cell manufacturing method - Google Patents
Bismos memory cell manufacturing method Download PDFInfo
- Publication number
- KR100309641B1 KR100309641B1 KR1019930000643A KR930000643A KR100309641B1 KR 100309641 B1 KR100309641 B1 KR 100309641B1 KR 1019930000643 A KR1019930000643 A KR 1019930000643A KR 930000643 A KR930000643 A KR 930000643A KR 100309641 B1 KR100309641 B1 KR 100309641B1
- Authority
- KR
- South Korea
- Prior art keywords
- region
- cell
- memory cell
- isolation
- npn transistor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 23
- 238000009792 diffusion process Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims description 13
- -1 boron ions Chemical class 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 abstract description 5
- 239000002245 particle Substances 0.000 abstract description 5
- 239000007858 starting material Substances 0.000 abstract description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
제1a, b도는 종래 바이 시모스 메모리셀 제조 공정도.1A and 1B are a process diagram of a conventional bi-MOSMOS memory cell manufacturing process.
제2a, b도는 본 발명에 따른 바이 시모스 제조 공정도.2a, b is a bismos manufacturing process according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1 : P+반도체기판 2, 3 : 매입층1: P + semiconductor substrate 2, 3 buried layer
4 : 에피층 5 : 확산영역4: epi layer 5: diffusion region
6, 6' : 소스 7, 7' : 드레인6, 6 ': source 7, 7': drain
8, 8' : 게이트 9 : 플레이프8, 8 ': gate 9: play
10 : 에미터 11 : 콜렉터10 emitter 11 collector
12 : 베이스 20 : 셀영역12: base 20: cell area
30 : NPN 트랜지스터 영역 40 : 격리영역30: NPN transistor region 40: isolation region
50 : 보론이온 60 : 격리접합부50: boron ion 60: isolation junction
본 발명은 바이 시모스 메모리셀에 관한 것으로서 특히 P+반도체기판을 스타트 물질 (STARTING MATERIAL)로 사용하여 알파 파티클(α-PARTICLE)에 의한 속성 저하를 간단하게 개선시켜 주도록한 바이 시모스 메모리셀 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bismos memory cell, and more particularly, to a method of manufacturing a bismos memory cell, in which a P + semiconductor substrate is used as a starting material to easily improve the property deterioration caused by alpha particles. It is about.
제 1 도의 (a)(b)는 종래 바이 시모스 메모리셀 제조 공정도이다.(A) and (b) of FIG. 1 are manufacturing process diagrams of a conventional bi-sMOS memory cell.
일반적으로 사용되는 바이 시모스(BI C0MS) 제조 공정은, 제 1 도의 (a)(b)에 도시된 바와 같이, 메모리셀 형성영역의 확산영역은 NPN 바이폴라 트랜지스터 영역의 베이스, 그리고 격리영역에는 따로 P+접합부를 각각 별도로 형성시켜 주도록 되어 있다.In a commonly used bi CMOS (BI C0MS) fabrication process, as shown in FIG. 1 (a) (b), the diffusion region of the memory cell formation region is the base of the NPN bipolar transistor region and the P is separated from the isolation region. The joints are formed separately.
즉, 제 1도의 (a)와와 같이, P 타입의 반도체기판(1)의 메모리 셀영역 아래와 바이폴라 격리영역 아래에 P+매입층(2)을 형성하고, 바이폴라 NPN 트랜지스터 영역과 PMOS 영역에 N+매입층(3)을 형성한다.That is, as shown in FIG. 1A, a P + buried layer 2 is formed below the memory cell region and below the bipolar isolation region of the P-type semiconductor substrate 1, and N + is formed in the bipolar NPN transistor region and the PMOS region. The buried layer 3 is formed.
그다음 제 1도의 (b)에서와 같이, 상기 P 타입의 반도체기판(1)과 매입층(2)(3) 위에 에피층(4)을 성장시킨 후, 메모리 셀영역(20)에는 확산영역(5)을, NPN 바이폴라 트랜지스터 영역(30)에는 베이스(12), 그리고 격리영역(40)에 따로 P+접합부를 형성시킨다.Then, as shown in (b) of FIG. 1, the epitaxial layer 4 is grown on the P-type semiconductor substrate 1 and the buried layer 2, 3, and then the diffusion region (3) is formed in the memory cell region 20. 5), a P + junction is formed in the NPN bipolar transistor region 30 separately from the base 12 and the isolation region 40.
이후, 일반적인 DRAM 제조공정을 진행하여 셀영역(20)에 소스(6),드레인(7),게이트(8),플레이트(9)를 형성하여 메모리셀을 완성하고, 바이폴라 NPN 트렌지스터영역(30)에는 에미터(10),베이스(12),콜렉터(11)를 형성하게 된다.After that, a general DRAM fabrication process is performed to form a source 6, a drain 7, a gate 8, and a plate 9 in the cell region 20 to complete the memory cell, and to form a bipolar NPN transistor region 30. The emitter 10, the base 12, and the collector 11 are formed therein.
상기와 같은 종래 바이 시모스 메모리셀 구조에서는 메모리셀 영역의 확산영역, NPN 바이폴라 트랜지스터 영역의 베이스, 그리고 격리영역에는 따로 P+접합부를 형성시켜 주어야 함으로서 이러한 복잡한 바이 시모스 디램 제작공정은 제품의 단가를 높게하고, 또한 고속, 고신뢰에서 문제되는 알파 파티클에 의한 소프트 에러(S0FT ERRER) 문제가 발생하게 되는 것이다.In the conventional bi-sMOS memory cell structure as described above, a P + junction must be formed separately in the diffusion region of the memory cell region, the base of the NPN bipolar transistor region, and the isolation region. In addition, a soft error (S0FT ERRER) problem caused by alpha particles, which is a problem at high speed and high reliability, occurs.
본 발명은 상기와 같은 문제점을 해결하기 위하여, 먼저, P+반도체 기판위에 에피층을 성장시킨 후, 셀영역, 격리영역 및 바이폴라 트랜지스터영역을 같은 형의 확산영역으로 동시에 형성시킨 것이다. 이 때, 확산공정에 의한 열에 의해 P+반도체 기판에서 보론(BORON)이온이 에피층으로 확산되어 확산영역과 닿게되는 접합격리부가 형성된다.In order to solve the above problems, first, an epitaxial layer is grown on a P + semiconductor substrate, and then a cell region, an isolation region, and a bipolar transistor region are simultaneously formed as diffusion regions of the same type. At this time, by the heat of the diffusion process, a boron (BORON) ion is diffused into the epitaxial layer from the P + semiconductor substrate to form a junction isolation portion in contact with the diffusion region.
즉, 본 발명은 바이 시모스(BI CMOS)메모리 셀 제조방법에 있어서, P+반도체 기판(1)에 에피층(4)을 형성하는 단계와. 셀 영역(20)과 격리영역(40) 및 바이폴라 트랜지스터영역(40)을 같은 형의 확산영역(5)으로 동시에 형성하는 단계와, 셀영역(20)과 바이폴라 트랜지스터영역(40)에 셀 및 바이폴라 트랜지스터를 형성하는 단계를 포함하여 이루어진 것이 특징이다.That is, the present invention provides a method of manufacturing a bi CMOS memory cell, comprising: forming an epitaxial layer (4) on a P + semiconductor substrate (1). Simultaneously forming the cell region 20, the isolation region 40, and the bipolar transistor region 40 into the diffusion region 5 of the same type, and the cell and bipolar regions in the cell region 20 and the bipolar transistor region 40. And forming a transistor.
이하, 첨부된 도면에 의해 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제 2 도의 (a)(b)는 본 발명에 따른 바이 시모스 제조 공정도이다.(A), (b) of FIG. 2 is a manufacturing process chart of the bismos according to the present invention.
제 2도의 (a)와 같이, P+반도체기판(1)에 에피층(4)을 성장시킨 후, 1차 이온주입에 의해 셀영역(20)과 격리영역(40)을 디파인한다.As shown in FIG. 2A, after the epi layer 4 is grown on the P + semiconductor substrate 1, the cell region 20 and the isolation region 40 are defined by primary ion implantation.
이 후, 2차 이온주입에 의해 바이폴라 NPN 트랜지스터 영역(30)을 디파인한다.Thereafter, the bipolar NPN transistor region 30 is defined by secondary ion implantation.
이 때, 셀영역(20)및 격리영역(40)은 도면과 같이, 바이폴라 NPN 트랜지스터 영역(30)과는 이온 농도 프로파일이 다르도록 이온주입된다.At this time, the cell region 20 and the isolation region 40 are ion implanted so that the ion concentration profile is different from that of the bipolar NPN transistor region 30 as shown in the figure.
즉, 셀영역(20) 및 격리영역(40)과, 바이폴라 NPN 트랜지스터 영역(30)은 이온주입시 에너지 세기 등의 차이에 의해 각기 다른 농도 프로파일을 갖는다.That is, the cell region 20, the isolation region 40, and the bipolar NPN transistor region 30 have different concentration profiles due to differences in energy intensities during ion implantation.
이 후, 기판에 열확산 공정을 진행시킴으로써, 셀영역(20) 및 격리영역(40)과, 바이폴라 NPN 트랜지스터영역(30)에 주입된 이온이 고르게 분포되도록 한다.Thereafter, a thermal diffusion process is performed on the substrate so that the ions implanted into the cell region 20 and the isolation region 40 and the bipolar NPN transistor region 30 are evenly distributed.
그러므로, 본 발명에서는 상기 2회에 걸친 이온주입 및 열확산 공정에 의해, 셀영역(20)과 격리영역(40), 그리고 바이폴라 NPN 트랜지스터 영역(30)이 같은 형의 확산영역으로 동시에 형성된다.Therefore, in the present invention, the cell region 20, the isolation region 40, and the bipolar NPN transistor region 30 are simultaneously formed into diffusion regions of the same type by the two ion implantation and thermal diffusion processes.
이 때, 동시에 형성된 셀영역(20)의 확산영역(5)과 NPN 트랜지스터영역(30)의 베이스(12)는 소자 특성을 만족시키도록 함과 동시에 최적화된다.At this time, the diffusion region 5 of the cell region 20 and the base 12 of the NPN transistor region 30 formed at the same time are optimized while satisfying device characteristics.
상기 열확산 공정 시, 이온 농도차에 의한 확산원리에 의해 P+반도체기판(1)의 보론이온이 에피층(4)으로 도핑되어 접합격리부(JUNTION ISOLATION)(60)가 형성된다.In the thermal diffusion process, boron ions of the P + semiconductor substrate 1 are doped into the epi layer 4 by the diffusion principle due to the difference in ion concentration to form a junction isolation unit 60.
이 후, 일반적인 DRAM 제조공정을 진행하여 (b)도와 같이 셀 영역(20)에 소스(6), 드레인(7),게이트(8),플레이트(9)를 형성하여 메모리 셀을 완성하고, 바이폴라 NPN 트랜지스터영역(30)에는 에미터(10),베이스(12),콜렉터(11)를 형성한다.Thereafter, a general DRAM manufacturing process is performed to form a source 6, a drain 7, a gate 8, and a plate 9 in the cell region 20 as shown in FIG. An emitter 10, a base 12, and a collector 11 are formed in the NPN transistor region 30.
이러한 구조는 기존의 바이 시모스 디램 공정에서 사용되어지는 마스크 공정을 3단계 줄여 주게 되며, 또한 메모리 셀 영역이 매입층과 맞닿게 함으로써 알파 파티클에 의한 디램셀의 정보가 손실되지 않게 되는 것이다.Such a structure reduces the mask process used in the conventional bi-sMOS DRAM process by three steps. Also, the memory cell region contacts the buried layer so that the information of the DRAM cell by the alpha particles is not lost.
통상적인 디램 구조에서는 바이폴라 격리를 위한 매입층이 필요하며, 에피층 성장후에는 메모리 셀 영역의 확산영역, 바이폴라 NPN 트랜지스터의 베이스, 그리고 격리영역 형성을 위한 접합이 각각 따로 최적화 되어야 하나, 본 발명에서는 P+반도체기판을 스타트 물질로 사용 함으로서 공정을 줄일뿐만 아니라 메모리 셀 영역의 확산영역, 바이폴라 NPN 트랜지스터의 베이스, 그리고 격리영역 형성을 위한 접합부를 P+반도체 기판층의 보론이온 확산에 의해 최적화 함으로써 마스크 공정과 열처리 공정을 줄여 제조원가를 감소 시키고, 메모리 셀 영역이 매입층과 맞닿게하여 알파 파티클에 의한 정보 손실을 개선하는 효과가 있다.In the conventional DRAM structure, a buried layer for bipolar isolation is required, and after epitaxial growth, the diffusion region of the memory cell region, the base of the bipolar NPN transistor, and the junction for forming the isolation region should be optimized separately. By using the P + semiconductor substrate as a starting material, not only the process is reduced but also the mask by optimizing the diffusion region of the memory cell region, the base of the bipolar NPN transistor, and the junction for forming the isolation region by the boron ion diffusion of the P + semiconductor substrate layer. The manufacturing cost is reduced by reducing the process and heat treatment process, and the memory cell region is brought into contact with the buried layer, thereby improving information loss caused by alpha particles.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930000643A KR100309641B1 (en) | 1993-01-20 | 1993-01-20 | Bismos memory cell manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930000643A KR100309641B1 (en) | 1993-01-20 | 1993-01-20 | Bismos memory cell manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR940018998A KR940018998A (en) | 1994-08-19 |
| KR100309641B1 true KR100309641B1 (en) | 2001-12-15 |
Family
ID=37530824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930000643A KR100309641B1 (en) | 1993-01-20 | 1993-01-20 | Bismos memory cell manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100309641B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100731087B1 (en) | 2005-10-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | Bi-SMOS device and its manufacturing method |
-
1993
- 1993-01-20 KR KR1019930000643A patent/KR100309641B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100731087B1 (en) | 2005-10-28 | 2007-06-22 | 동부일렉트로닉스 주식회사 | Bi-SMOS device and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| KR940018998A (en) | 1994-08-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5424572A (en) | Spacer formation in a semiconductor structure | |
| US3955269A (en) | Fabricating high performance integrated bipolar and complementary field effect transistors | |
| US5082796A (en) | Use of polysilicon layer for local interconnect in a CMOS or BiCMOS technology incorporating sidewall spacers | |
| KR100189739B1 (en) | Method of forming well for semiconductor wafer | |
| US5907168A (en) | Low noise Ge-JFETs | |
| KR19980071514A (en) | Semiconductor device and manufacturing method thereof | |
| US5837590A (en) | Isolated vertical PNP transistor without required buried layer | |
| JPH0348458A (en) | Bi-CMOS integrated circuit and its manufacturing method | |
| KR100309641B1 (en) | Bismos memory cell manufacturing method | |
| US5929506A (en) | Isolated vertical PNP transistor and methods for making same in a digital BiCMOS process | |
| JP2001093985A (en) | Silicon carbide semiconductor device and its manufacturing method | |
| US6316324B1 (en) | Method of manufacturing semiconductor device without forming selective region by lithography | |
| KR0138310B1 (en) | Bipolat transistor fabrication method | |
| JPH03116774A (en) | Manufacture of semiconductor device | |
| KR940001257B1 (en) | Method of making semiconductor device | |
| KR100196509B1 (en) | Most transistor manufacturing method | |
| KR100264210B1 (en) | Method for separating active region of semiconductor device | |
| JPS60105265A (en) | Method for manufacturing complementary semiconductor device | |
| KR100194654B1 (en) | Semiconductor device and manufacturing method thereof | |
| JPS63144567A (en) | Manufacture of semiconductor device | |
| KR940010913B1 (en) | High breakdown voltage bipolar transistor and method of manufacturing the same | |
| KR0147644B1 (en) | Bicmos device and its manufacture method | |
| JPS63164356A (en) | Manufacture of semiconductor integrated circuit | |
| JPH01134962A (en) | Manufacture of semiconductor device | |
| JPH04346263A (en) | Manufacture of bi-cmos semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19930120 |
|
| PG1501 | Laying open of application | ||
| A201 | Request for examination | ||
| PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19971229 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19930120 Comment text: Patent Application |
|
| E902 | Notification of reason for refusal | ||
| PE0902 | Notice of grounds for rejection |
Comment text: Notification of reason for refusal Patent event date: 20000731 Patent event code: PE09021S01D |
|
| E701 | Decision to grant or registration of patent right | ||
| PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 20010621 |
|
| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20010910 Patent event code: PR07011E01D |
|
| PR1002 | Payment of registration fee |
Payment date: 20010911 End annual number: 3 Start annual number: 1 |
|
| PG1601 | Publication of registration | ||
| PR1001 | Payment of annual fee |
Payment date: 20040820 Start annual number: 4 End annual number: 4 |
|
| PR1001 | Payment of annual fee |
Payment date: 20050822 Start annual number: 5 End annual number: 5 |
|
| PR1001 | Payment of annual fee |
Payment date: 20060818 Start annual number: 6 End annual number: 6 |
|
| PR1001 | Payment of annual fee |
Payment date: 20070827 Start annual number: 7 End annual number: 7 |
|
| PR1001 | Payment of annual fee |
Payment date: 20080820 Start annual number: 8 End annual number: 8 |
|
| PR1001 | Payment of annual fee |
Payment date: 20090828 Start annual number: 9 End annual number: 9 |
|
| FPAY | Annual fee payment |
Payment date: 20100825 Year of fee payment: 10 |
|
| PR1001 | Payment of annual fee |
Payment date: 20100825 Start annual number: 10 End annual number: 10 |
|
| LAPS | Lapse due to unpaid annual fee | ||
| PC1903 | Unpaid annual fee |
Termination category: Default of registration fee Termination date: 20120809 |