Nothing Special   »   [go: up one dir, main page]

JPS63144567A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63144567A
JPS63144567A JP29277286A JP29277286A JPS63144567A JP S63144567 A JPS63144567 A JP S63144567A JP 29277286 A JP29277286 A JP 29277286A JP 29277286 A JP29277286 A JP 29277286A JP S63144567 A JPS63144567 A JP S63144567A
Authority
JP
Japan
Prior art keywords
buried layer
semiconductor device
oxide film
ion implantation
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29277286A
Other languages
Japanese (ja)
Inventor
Kazuhiko Hashimoto
一彦 橋本
Mitsuchika Saitou
光親 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP29277286A priority Critical patent/JPS63144567A/en
Publication of JPS63144567A publication Critical patent/JPS63144567A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To form a semiconductor device having excellent characteristics through a simple manufacturing technique using no epitaxial technique by forming an insulating film for isolating elements to a first conductivity type semiconductor base body and selectively shaping a second conductivity type buried layer by employing an ion implantation method. CONSTITUTION:An oxide film 22 for isolating elements is formed to a substrate 21. An oxide film is 200Angstrom is shaped in an element region, and phosphorus ions are implanted selectively at acceleration voltage of 1.0-2MeV and in dosage of 1X10<15>-1X10<16>cm<-2> through a photoetching method, thus shaping a buried layer 23. Said oxide film is peeled selectively through the photoetching method, and phosphorus ions are implanted under conditions of 100KeV and 1X10<12>cm<-2>, thus forming a collector 24. Likewise, a base 25 by boron under conditions of 20KeV and 1X10<14>cm<-2> and an external collector 26 by phosphorus under conditions of 100KeV and 5X10<15>cm<-2> are formed through ion implantation by employing the photoetching method.

Description

【発明の詳細な説明】 [発明の目的] (産業上の利用分野) 本発明は半導体装置の製造方法に関するもので、特にバ
イポーラ型半導体装置の接続方法に使用されるものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and is particularly used for a method for connecting bipolar semiconductor devices.

(従来の技術)   ′ 従来のNPN型バイポーラ・トランジスタの製造方法を
第2図により説明する。まずP型(100)基板1に高
濃度N型埋め込み層3をアンチモンなどの拡散により形
成し、約2μmの厚さのP型エピタキシャル層2を形成
し10通常の方法でN型ウェル層4を形成する。(第2
図(a))次に選択酸化法等を用いて、非素子領域に酸
化膜12を5000人形成し、素子領域に酸化膜5を形
成し、イオン注入法で、選択的にP型ベース層6を形成
する。(第2図(b))更に前記酸化膜5の一部を開孔
し、多結晶シリコン層7を全面に形成し、砒素などのN
型不純物をイオン注入法等により導入し、熱処理を行な
いN型エミツタ層8を形成する。(第2図(C))写真
食刻法等により、前記多結晶シリコン層7をフォトレジ
スト9をマスクとし部分的にエツチングし、前記フォト
レジスト9、前記酸化膜12をマスクにして、イオン注
入法等で高濃度P型外部ベース層10を形成する。第2
図(d)更に拡散、イオン注入法等によりN型高濃度外
部コレクタ層11を形成する。(第2図(e)更に、通
常の方法により、配線層を形成するものである。
(Prior Art) A conventional method for manufacturing an NPN bipolar transistor will be explained with reference to FIG. First, a heavily doped N-type buried layer 3 is formed on a P-type (100) substrate 1 by diffusion of antimony, etc., a P-type epitaxial layer 2 with a thickness of approximately 2 μm is formed, and an N-type well layer 4 is formed using a normal method. Form. (Second
Figure (a)) Next, 5,000 oxide films 12 are formed in the non-device region using selective oxidation, etc., an oxide film 5 is formed in the device region, and a P-type base layer is selectively formed by ion implantation. form 6. (FIG. 2(b)) Further, a part of the oxide film 5 is opened, a polycrystalline silicon layer 7 is formed on the entire surface, and N such as arsenic is formed.
Type impurities are introduced by ion implantation or the like, and heat treatment is performed to form an N-type emitter layer 8. (FIG. 2(C)) The polycrystalline silicon layer 7 is partially etched by photolithography using the photoresist 9 as a mask, and ions are implanted using the photoresist 9 and the oxide film 12 as a mask. A highly doped P-type external base layer 10 is formed by a method or the like. Second
(d) Further, an N-type high concentration external collector layer 11 is formed by diffusion, ion implantation, or the like. (FIG. 2(e)) Furthermore, a wiring layer is formed by a normal method.

(発明が解決しようとする問題点) しかしながら、従来方法によると以下のような欠点を持
つ。
(Problems to be Solved by the Invention) However, the conventional method has the following drawbacks.

(1)  エピタキシャル成長技術を用いる為、埋め込
み層に用いるN型不純物として、通常オートドーピング
効果を抑制する為にアンチモンを使用する。しかしなが
らアンチモンはシリコンに対する固溶度が小さい為に、
低抵抗埋込み層を実現する為には、深いアンチモン層を
形成する必要がある。
(1) Since epitaxial growth technology is used, antimony is usually used as an N-type impurity for the buried layer in order to suppress the autodoping effect. However, since antimony has low solid solubility in silicon,
In order to realize a low resistance buried layer, it is necessary to form a deep antimony layer.

(シリコン表面から埋め込み層表面までの距離)を制御
性良く形成出来ないという欠点を持つ。
(distance from the silicon surface to the surface of the buried layer) cannot be formed with good controllability.

(2)  エピタキシャル層形成に高温(通常1100
℃以上)が必要な為にアンチモン層がエピタキシャル層
に拡散し、実効的なエピタキシャル脱灰が薄くなるので
、薄エピタキシャル層を制御性良く形成することが難し
い為、バイポーラトランジスタ特性の制御性が悪い。
(2) High temperature (usually 1100℃) for epitaxial layer formation
℃ or higher), the antimony layer diffuses into the epitaxial layer, and the effective epitaxial deashing becomes thinner, making it difficult to form a thin epitaxial layer with good controllability, resulting in poor controllability of bipolar transistor characteristics. .

(3)  エピタキシャル層は通常のシリコン基板に比
較して、欠陥密度が大きいので、エピタキシャル技術を
用いて製造した半導体は不良品が多く、高価である。
(3) Since the epitaxial layer has a higher defect density than a normal silicon substrate, semiconductors manufactured using epitaxial technology have many defective products and are expensive.

本発明は、これらの事情に鑑みなされたもので、エピタ
キシャル技術を用いない簡易な製造技術が実現出来かつ
、優れた特性を持つ半導体装置の製造方法を提供するも
のである。゛ [発明の構成] (問題点を解決するための手段) 本発明はバイポーラ形トランジスタを含む半導体装置を
製造するに当り、第1導電型半導体基体に素子分離用絶
縁膜を形成した後に、イオン注入法を用いて選択的に第
2導電型埋め込み層を形成する工程を具備したことを特
徴とする半導体装置の製造方法である。即ち高濃度埋め
込み層を形成するに際して、従来の拡散による埋め込み
層形成とその後のエピタキシャル技術によるシリコン基
板形成と異なり、通常の単結晶シリコン基板に高加速イ
オン注入を行うことにより埋め込み層を形成し、従来の
埋め込み層/エピタキシャル成長と同等以上の作用をも
たせることをその特徴とする。
The present invention has been made in view of these circumstances, and provides a method for manufacturing a semiconductor device that can realize a simple manufacturing technique that does not use epitaxial technology and has excellent characteristics.゛ [Structure of the Invention] (Means for Solving the Problems) In manufacturing a semiconductor device including a bipolar transistor, the present invention provides that after forming an element isolation insulating film on a first conductivity type semiconductor substrate, ions are removed. This is a method of manufacturing a semiconductor device, comprising a step of selectively forming a second conductivity type buried layer using an injection method. That is, when forming a high concentration buried layer, unlike the conventional formation of a buried layer by diffusion and subsequent formation of a silicon substrate by epitaxial technology, the buried layer is formed by performing high acceleration ion implantation into a normal single crystal silicon substrate, Its feature is that it has an effect equivalent to or better than that of conventional buried layer/epitaxial growth.

(実施例) 以下図面を参照して本発明の一実施例を説明する。第1
図は同実施例の工程を示す断面図である。まず、P型(
100)シリコン基板21に、通常用いられる方法で素
子分離用酸化膜22を500OA形成する。(第1図(
a))次に200人の酸化膜を素子領域に形成し、1.
0−2MeVの加速電圧、ドーズEtlxlO” 〜1
xlO” cm−2でリンを写真食刻法を用い選択的に
イオン注入し、埋め込み層23を形成する。(第1図(
b))他の製造条件での埋め込み層23形成のイオン注
入条件は異なるが本実施例での最適条件は1.5 MV
、lXl0α−2の条件でイオン注入しコレクタ24を
形成する。更に、同様に写真食刻法を用い、ボロンを2
0KeV、  I X 10” ax−2の条件でベー
ス25、リンを100KeV、5X10” cry°2
の条件で外部コレクタ26をイオン注入で形成する。(
第1図(C))次に従来の実施例と同様の方法でエミッ
タ、外部ベースを形成し、その後配線を行うものである
(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure is a sectional view showing the process of the same embodiment. First, P type (
100) Form an oxide film 22 with a thickness of 500 OA on a silicon substrate 21 using a commonly used method. (Figure 1 (
a)) Next, a 200-layer oxide film is formed on the device region, and 1.
Accelerating voltage of 0-2 MeV, dose EtlxlO” ~1
A buried layer 23 is formed by selectively ion-implanting phosphorus at xlO" cm-2 using a photolithography method (see Fig. 1).
b)) Although the ion implantation conditions for forming the buried layer 23 are different under other manufacturing conditions, the optimum conditions in this example are 1.5 MV.
, lXl0α-2 to form the collector 24. Furthermore, using the same photo-etching method, 2 boron
Base 25, phosphorus at 100KeV, 5X10” cry°2 under the conditions of 0KeV, I x 10”ax-2
The external collector 26 is formed by ion implantation under the following conditions. (
(FIG. 1C) Next, an emitter and an external base are formed in the same manner as in the conventional embodiment, and then wiring is performed.

本実施例では埋め込み層をリンで形成したが、ヒ素を用
いても、イオン注入加速電圧がリンと同じ投影飛程とな
る様調整すれば作用効果は変わらない。
In this embodiment, the buried layer is made of phosphorus, but even if arsenic is used, the effect remains the same if the ion implantation accelerating voltage is adjusted to have the same projected range as phosphorus.

又本実施例ではバイポーラ素子のみの製造方法をのべた
が、バイポーラCMO3IU合素子いわゆるB 1−C
MOS素子の製造等にも同様の方法で応用出来る。
Furthermore, although this embodiment describes the method of manufacturing only a bipolar element, a bipolar CMO3IU composite element, so-called B1-C
A similar method can also be applied to the manufacture of MOS devices.

上記実施例によれば、 (1)  エピタキシャル技術を用いないので、安価で
不良品の少ない半導体装置を提供出来る。
According to the above embodiments: (1) Since epitaxial technology is not used, a semiconductor device can be provided at low cost and with fewer defective products.

(2)埋め込み層形成時、形成後の熱工程を、従来の如
くエピタキシャル層及びアンチモンを使わない為に、最
小に出来、制御性が上がるので高性能特性が得られる。
(2) During the formation of the buried layer, the thermal process after formation can be minimized because an epitaxial layer and antimony are not used as in the conventional method, and controllability is improved, resulting in high performance characteristics.

(3)  (2)と同じ理由で、埋め込み層の横方向拡
散が少なく、高集積化が可能である。
(3) For the same reason as (2), there is little lateral diffusion of the buried layer, and high integration is possible.

埋め込み層23里は他と比べ浅くなり、外部コレクタを
深く形成する必要がないので熱工程を少なく出来、ひい
ては高性能特性が得られる。
The buried layer 23 is shallower than the others, and there is no need to form a deep external collector, so the thermal process can be reduced and high performance characteristics can be obtained.

[発明の効果] 以上説明した如く本発明によれば、従来の如きエピタキ
シャル技術を用いない簡易な製造技術が実現でき、かつ
優れた特性をもつ半導体装置が提供できるものである。
[Effects of the Invention] As described above, according to the present invention, a simple manufacturing technique that does not use conventional epitaxial technology can be realized, and a semiconductor device with excellent characteristics can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の工程説明図、第2図は従来
装置の工程説明図である。 21・・・P型シリコン基板、22・・・酸化膜、23
・・・N型埋め込み層、24・・・コレクタ、25・・
・ベース、26・・・外部コレクタ。
FIG. 1 is a process explanatory diagram of an embodiment of the present invention, and FIG. 2 is a process explanatory diagram of a conventional apparatus. 21... P-type silicon substrate, 22... Oxide film, 23
...N-type buried layer, 24...Collector, 25...
- Base, 26...external collector.

Claims (3)

【特許請求の範囲】[Claims] (1)バイポーラ型トランジスタを含む半導体装置を製
造するに当り、第1導電型半導体基体に素子分離用絶縁
膜を形成した後に、イオン注入法を用いて選択的に第2
導電型埋め込み層を形成する工程を具備したことを特徴
とする半導体装置の製造方法。
(1) When manufacturing a semiconductor device including a bipolar transistor, after forming an element isolation insulating film on a first conductivity type semiconductor substrate, a second conductivity type semiconductor substrate is selectively formed using an ion implantation method.
1. A method of manufacturing a semiconductor device, comprising a step of forming a conductive buried layer.
(2)前記埋め込み層がリンまたはヒ素で形成されるこ
とを特徴とする特許請求の範囲第1項に記載の半導体装
置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the buried layer is made of phosphorus or arsenic.
(3)前記リンが加速電圧1〜2MeV、ドーズ量1×
10^1^5〜1×10^1^6cm^−^2の条件で
イオン注入されることを特徴とする特許請求の範囲第2
項に記載の半導体装置の製造方法。
(3) The phosphorus has an acceleration voltage of 1 to 2 MeV and a dose of 1×
Claim 2, characterized in that the ions are implanted under the conditions of 10^1^5 to 1 x 10^1^6 cm^-^2.
A method for manufacturing a semiconductor device according to section 1.
JP29277286A 1986-12-09 1986-12-09 Manufacture of semiconductor device Pending JPS63144567A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29277286A JPS63144567A (en) 1986-12-09 1986-12-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29277286A JPS63144567A (en) 1986-12-09 1986-12-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63144567A true JPS63144567A (en) 1988-06-16

Family

ID=17786140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29277286A Pending JPS63144567A (en) 1986-12-09 1986-12-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63144567A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04174523A (en) * 1990-03-09 1992-06-22 Mitsubishi Electric Corp Bipolar transistor
JP2012243784A (en) * 2011-05-16 2012-12-10 Lapis Semiconductor Co Ltd Semiconductor device and manufacturing method of the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04174523A (en) * 1990-03-09 1992-06-22 Mitsubishi Electric Corp Bipolar transistor
JP2012243784A (en) * 2011-05-16 2012-12-10 Lapis Semiconductor Co Ltd Semiconductor device and manufacturing method of the same

Similar Documents

Publication Publication Date Title
US4408387A (en) Method for producing a bipolar transistor utilizing an oxidized semiconductor masking layer in conjunction with an anti-oxidation mask
JPH0817841A (en) Manufacture of semiconductor substrate and semiconductor device
JPS63144567A (en) Manufacture of semiconductor device
JPS62200723A (en) Manufacture of semiconductor device
JPS624339A (en) Semiconductor device and manufacture thereof
JP3097095B2 (en) Method for manufacturing semiconductor device
JPH0387059A (en) Semiconductor integrated circuit
JP2828264B2 (en) Method for manufacturing semiconductor device
JP2571449B2 (en) Manufacturing method of bipolar IC
JP2722829B2 (en) Method for manufacturing semiconductor device
JP2988067B2 (en) Manufacturing method of insulated field effect transistor
JP2892436B2 (en) Method for manufacturing semiconductor device
JPS63273317A (en) Manufacture of semiconductor device
JPS617664A (en) Semiconductor device and manufacture thereof
JPS6129537B2 (en)
JPS63278347A (en) Semiconductor device and manufacture thereof
JPS63306659A (en) Semiconductor device and manufacture thereof
JPH02181931A (en) Manufacture of semiconductor device
JPH01307216A (en) Manufacture of semiconductor device
JPH0281438A (en) Bipolar integrated circuit
JPH04245674A (en) Manufacture of semiconductor device
JPH0897226A (en) Pnp transistor, semiconductor integrated circuit, manufacture of semiconductor device, and manufacture of semiconductor integrated circuit
JPH0244733A (en) Manufacture of semiconductor device
JPH04237168A (en) Manufacture of mis type semiconductor device
JPS605561A (en) Manufacture of semiconductor device