KR100294643B1 - Triple Well Forming Method of Semiconductor Device_ - Google Patents
Triple Well Forming Method of Semiconductor Device_ Download PDFInfo
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- KR100294643B1 KR100294643B1 KR1019980061144A KR19980061144A KR100294643B1 KR 100294643 B1 KR100294643 B1 KR 100294643B1 KR 1019980061144 A KR1019980061144 A KR 1019980061144A KR 19980061144 A KR19980061144 A KR 19980061144A KR 100294643 B1 KR100294643 B1 KR 100294643B1
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- 239000007943 implant Substances 0.000 abstract description 2
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
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Abstract
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자의 삼중웰(triple-well) 형성방법에 관한 것이며, 누설전류의 감소와 더불어 래치-업 특성을 개선할 수 있는 반도체 소자의 삼중웰 형성방법을 제공하는데 그 목적이 있다. 종래기술의 문제점은 누설전류 특성 개선을 위하여 깊은 웰 이온주입시 이온주입 에너지 및 도즈를 낮추는데 따른 래치-업 특성의 열화에 있다. 이에 본 발명은 예컨대, 고에너지 이온주입 방식의 깊은 n웰 이온주입/중간 n웰 이온주입/p웰 이온주입을 통해 n웰/n웰로 둘러싸인 제1 p웰/제2 p웰 구조의 삼중웰을 고에너지 이온주입을 이용하여 형성함에 있어서, 누설전류 특성에 가장 큰 영향을 주는 깊은 n웰 이온주입시의 도즈만을 낮추어 우수한 접합 누설전류 특성을 확보하고, 중간 n웰 이온주입시 이온주입 에너지를 높여 중간 n웰 이온주입 영역의 위치를 깊은 n웰 이온주입 영역 쪽으로 이동시켜 궁극적으로 n웰의 저항을 감소시킴으로써 취약해 질 수 있는 래치-업 특성을 보완하는 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor technology, and more particularly, to a method of forming a triple-well of a semiconductor device, and to providing a method of forming a triple well of a semiconductor device capable of reducing a leakage current and improving latch-up characteristics. Its purpose is to. The problem of the prior art lies in the deterioration of the latch-up characteristic due to lowering the ion implantation energy and dose during deep well ion implantation to improve leakage current characteristics. Accordingly, the present invention provides a triple well of a first p well / second p well structure surrounded by n wells / n wells through, for example, deep n well ion implantation / middle n well ion implantation / p well ion implantation using high energy ion implantation. Formation using high energy ion implantation ensures excellent junction leakage current characteristics by lowering the dose at the time of deep n well ion implantation, which has the greatest effect on leakage current characteristics, and increases ion implantation energy during intermediate n well ion implantation. By shifting the position of the middle n well implantation region toward the deep n well implant region, it ultimately reduces the resistance of the n well to compensate for the latch-up characteristics that can be vulnerable.
Description
본 발명은 반도체 기술에 관한 것으로, 특히 반도체 소자의 삼중웰(triple-well) 형성방법에 관한 것이다.TECHNICAL FIELD The present invention relates to semiconductor technology, and more particularly, to a method of forming triple-wells of semiconductor devices.
반도체 소자의 고집적화가 급속히 진행됨에 따라 불순물이나 격자 결함이 극미량이라 할지라도 이들이 소자 구동 영역에 존재할 경우 소자의 전기적 특성을 크게 저하시키기 때문에 반도체 제조 공정 중 불순물이나 격자 결함의 생성은 최대한 억제시키거나 또는 공정 중에 이를 제거해야만 한다.As the high integration of semiconductor devices proceeds rapidly, even if the amount of impurities or lattice defects is extremely small, if they are present in the device driving region, the electrical characteristics of the devices are greatly deteriorated. It must be removed during the process.
첨부된 도면 도 1a 내지 1f는 종래기술에 따른 삼중웰 기술을 이용한 트랜지스터 제조 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.1A to 1F illustrate a transistor manufacturing process using a triple well technique according to the prior art, which will be described with reference to the following.
종래기술에 따른 공정은 먼저 도 1a를 참조하면, 실리콘 웨이퍼(1)에 STI(shallow trench isolation)공정을 진행하여 소자분리막(2)을 형성한다.Referring to FIG. 1A, a process according to the prior art first performs a shallow trench isolation (STI) process on a silicon wafer 1 to form an isolation layer 2.
이어서, 도 1b에 나타낸 바와 같이 깊은 n웰 형성을 위한 마스크 공정을 수행하여 포토레지스트 패턴(3)을 형성하고 이를 이온주입 마스크로 고에너지 이온주입기를 사용한31P 이온주입을 수행하여 깊은 n웰 이온주입 영역(4)을 형성한다.Subsequently, as shown in FIG. 1B, a mask process for deep n well formation is performed to form a photoresist pattern 3, and 31 P ion implantation using a high energy ion implanter as an ion implantation mask is performed to deep n well ions. The injection region 4 is formed.
다음으로, 도 1c에 나타낸 바와 같이 포토레지스트 패턴(3)을 제거한 다음, n웰 형성을 위한 마스크 공정을 실시하여 포토레지스트 패턴(5)을 형성하고 이를 이온주입 마스크로 고에너지 이온주입기를 사용한 중간 n웰 이온주입 및 p채널 필드스탑(p-channel field stop) 이온주입 공정을 수행하여 프로파일드(profiled) n웰을 형성한다. 이때, 도면 부호 '6'은 중간 n웰 이온주입 영역, '7'은 p채널 필드스탑 이온주입 영역, '8'은 프로파일드 n웰의 프로파일을 각각 나타낸 것이다.Next, as shown in FIG. 1C, the photoresist pattern 3 is removed, followed by a mask process for forming an n-well to form a photoresist pattern 5, and using the high energy ion implanter as an ion implantation mask. An n well ion implantation and a p-channel field stop ion implantation process is performed to form a profiled n well. In this case, reference numeral '6' denotes an intermediate n well ion implantation region, '7' denotes a p-channel field stop ion implantation region, and '8' denotes a profile of a profiled n well.
이어서, 도 1d에 나타낸 바와 같이 포토레지스트 패턴(5)을 제거한 다음, p웰 형성을 위한 마스크 공정을 실시하여 포토레지스트 패턴(9)을 형성하고, 역시 고에너지 이온주입기를 사용하여 p웰 이온주입 및 n채널 필드스탑 이온주입을 수행하여 프로파일드 p웰을 형성한다. 도면 부호 '10'은 p웰 이온주입 영역, '11'은 n채널 필드스탑 이온주입 영역, '12'는 프로파일드 p웰의 프로파일을 각각 나타낸 것이다.Subsequently, as shown in FIG. 1D, the photoresist pattern 5 is removed, followed by a mask process for forming a p-well to form a photoresist pattern 9, which is also implanted with a p-well ion implanter using a high energy ion implanter. And n-channel field stop ion implantation to form a profiled p well. Reference numeral '10' denotes a p well ion implantation region, '11' denotes an n-channel field stop ion implantation region, and '12' denotes a profile of a profiled p well.
다음으로 도 1e를 참조하면, 포토레지스트 패턴(9)을 제거한 다음, 퍼니스(furnace) 열처리 과정을 통해 이온주입된 불순물을 활성화시켜 n웰(14)과, 제1 p웰(13), n웰(14)로 둘러싸인 제2p 웰(15) 등 2개의 p웰과 1개의 n웰을 형성한다Next, referring to FIG. 1E, after removing the photoresist pattern 9, an ion implanted impurity is activated through a furnace heat treatment process to n n 14, the first p well 13, and n well. Two p wells and one n well such as a second p well 15 surrounded by 14 are formed.
도 1f는 각 웰(13, 14, 15) 상에 형성된 트랜지스터를 모식적으로 도시한 것으로, 도시된 바와 같이 제2 p웰(15) 상에 형성되는 트랜지스터(18)는 제1 p웰(13) 상에 형성되는 트랜지스터(16)와 다른 독립적인 트랜지스터를 형성할 수도 있으며, n웰로 둘러싸여 있기 때문에 갑자기 유입되는 외부 전압이나 노이즈(noise)로부터 보호될 수 있다.FIG. 1F schematically illustrates a transistor formed on each well 13, 14, and 15. As illustrated, the transistor 18 formed on the second p well 15 may include a first p well 13. The transistor 16 may be formed to be independent of the transistor 16 formed on the N-th transistor, and may be surrounded by n wells, thereby being protected from an unexpected external voltage or noise.
그러나, 전술한 종래기술은 각 이온주입 조건이 적절하지 않으면 큰 접합누설전류를 유발하기도 하는데, 특히 고에너지 이온주입기를 사용하여 깊은 n웰 이온주입을 수행할 때 사용하는31P 이온에 의한 손상은 도즈(dose)가 비교적 낮아 소자 특성에는 별 영향을 주지 않을 것으로 알려져 있었으나, Rp(projected range)뿐만 아니라 표면에 이르기까지 많은 마이크로 결함을 생성시킴으로써 취약한 누설전류 특성을 나타내는 문제점이 발견되고 있다.However, the above-described prior art may cause a large junction leakage current if each ion implantation condition is not appropriate. In particular, the damage caused by 31 P ions used when performing deep n well ion implantation using a high energy ion implanter is prevented. Although the dose is relatively low, it is not known to affect the device characteristics. However, a problem of exhibiting a weak leakage current characteristic by generating a large number of micro defects not only in the projected range but also on the surface has been found.
첨부된 도면 도 2는 상기 도 1f에 도시된 구조 형성시 이온주입 에너지와 도즈 조건에 따른 누설전류(n+접합/제2 p웰(15))를 도시한 것으로, 이온주입 에너지와 도즈 조건이 소자에 미치는 영향이 매우 큼을 알 수 있다.FIG. 2 is a diagram illustrating ion injection energy and leakage current (n + junction / second p well 15) according to ion implantation energy and dose conditions in forming the structure illustrated in FIG. 1F. It can be seen that the effect on the device is very large.
이러한 문제점을 고려하여 깊은 n웰 이온주입시 이온주입 에너지와31P 이온의 도즈를 낮추어 이온주입을 수행하는 기술이 제시되었다. 이 경우, 우수한 접합 누설전류 특성을 확보할 수 있었으나, 래치-업(latch-up) 특성은 깊은 n웰 이온주입시 이온주입 에너지와31P 이온의 도즈를 낮춤으로써 상당히 취약해지는 문제점이 있었다.In consideration of these problems, a technique of performing ion implantation by lowering ion implantation energy and dose of 31 P ions during deep n well ion implantation has been proposed. In this case, excellent junction leakage current characteristics could be secured, but the latch-up characteristic had a problem of being significantly weakened by lowering the ion implantation energy and the dose of 31 P ions during deep n well ion implantation.
첨부된 도면 도 3a 및 도 3b는 각각 상기 도 1f에 도시된 구조 형성시 접합-웰 거리에 따른 홀딩 전압 특성을 각각 제2 p웰(15)/n웰(14) 및 제1 p웰(13)/n웰(14)에 대해 측정한 특성도로서, 깊은 n웰 이온주입시 도즈 및 이온주입 에너지를 낮출 경우, 래치-업 특성이 크게 저하됨을 알 수 있다.3A and 3B show the holding voltage characteristics according to the junction-well distances when forming the structure shown in FIG. 1F, respectively, for the second p well 15 / n well 14 and the first p well 13, respectively. As a characteristic diagram measured for) / n well 14, it can be seen that the latch-up characteristic is greatly reduced when the dose and ion implantation energy are lowered during deep n well ion implantation.
본 발명은 누설전류의 감소와 더불어 래치-업 특성을 개선할 수 있는 반도체 소자의 삼중웰 형성방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a triple well forming method of a semiconductor device capable of reducing a leakage current and improving a latch-up characteristic.
도 1a 내지 1f는 종래의 삼중웰 기술을 이용한 트랜지스터 제조 공정도.1A to 1F are transistor manufacturing process diagrams using conventional triple well techniques.
도 2는 상기 도 1f에 도시된 구조 형성시 이온주입 에너지와 도즈 조건에 따른 누설전류(n+접합/제2 p웰(15)) 특성도.2 is a characteristic diagram of leakage current (n + junction / second p well 15) according to ion implantation energy and dose conditions in forming the structure shown in FIG. 1F;
도 3a 및 도 3b는 각각 상기 도 1f에 도시된 구조 형성시 접합-웰 거리에 따른 홀딩 전압 특성을 각각 제2 p웰(15)/n웰(14) 및 제1 p웰(13)/n웰(14)에 대해 측정한 특성도.3A and 3B show the holding voltage characteristics according to the junction-well distance when forming the structure shown in FIG. 1F, respectively, for the second p well 15 / n well 14 and the first p well 13 / n, respectively. Characteristic chart measured for the well 14.
도 4a 내지 4e는 본 발명의 일 실시예에 따른 삼중웰 형성 공정도.Figures 4a to 4e is a triple well forming process in accordance with an embodiment of the present invention.
도 5a는 깊은 n웰 이온주입 공정 조건(도즈 및 이온주입 에너지)에 따른 p+접합/n웰 누설전류 특성도.FIG. 5A is a plot of p + junction / n well leakage current with deep n well ion implantation process conditions (dose and ion implantation energy). FIG.
도 5b는 중간 n웰 이온주입 공정 조건(도즈 및 이온주입 에너지)에 따른 p+접합/n웰 누설전류 특성도.5b is a plot of p + junction / n well leakage current according to intermediate n well ion implantation process conditions (dose and ion implantation energy).
도 5c는 p웰 이온주입 공정 조건(도즈 및 이온주입 에너지)에 따른 n+접합/p웰 누설전류 특성도.5C is a diagram of n + junction / pwell leakage current characteristics according to pwell ion implantation process conditions (dose and ion implantation energy).
도 6a 및 도 6b는 삼중웰 형성시 접합-웰 거리에 따른 홀딩 전압 특성을 각각 제2 p웰/n웰 및 제1 p웰/n웰에 대해 측정한 특성도.6A and 6B are characteristic diagrams of holding voltage characteristics of the second p well / n well and the first p well / n well, respectively, according to the junction-well distance during triple well formation.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
41 : 실리콘 웨이퍼41: silicon wafer
42 : 필드 산화막42: field oxide film
43, 45, 49 : 포토레지스트 패턴43, 45, 49: photoresist pattern
53 : 제1 p웰53: first p well
54 : n웰54: n well
55 : 제2 p웰55: second p well
종래기술의 문제점은 누설전류 특성 개선을 위하여 깊은 웰 이온주입시 이온주입 에너지 및 도즈를 낮추는데 따른 래치-업 특성의 열화에 있다. 이에 본 발명은 예컨대, 고에너지 이온주입 방식의 깊은 n웰 이온주입/중간 n웰 이온주입/p웰 이온주입을 통해 n웰/n웰로 둘러싸인 제1 p웰/제2 p웰 구조의 삼중웰을 고에너지 이온주입을 이용하여 형성함에 있어서, 누설전류 특성에 가장 큰 영향을 주는 깊은 n웰 이온주입시의 도즈만을 낮추어 우수한 접합 누설전류 특성을 확보하고, 중간 n웰 이온주입시 이온주입 에너지를 높여 중간 n웰 이온주입 영역의 위치를 깊은 n웰 이온주입 영역 쪽으로 이동시켜 궁극적으로 n웰의 저항을 감소시킴으로써 취약해 질 수 있는 래치-업 특성을 보완하는 것이다.The problem of the prior art lies in the deterioration of the latch-up characteristic due to lowering the ion implantation energy and dose during deep well ion implantation to improve leakage current characteristics. Accordingly, the present invention provides a triple well of a first p well / second p well structure surrounded by n wells / n wells through, for example, deep n well ion implantation / middle n well ion implantation / p well ion implantation using high energy ion implantation. Formation using high energy ion implantation ensures excellent junction leakage current characteristics by lowering the dose at the time of deep n well ion implantation, which has the greatest effect on leakage current characteristics, and increases ion implantation energy during intermediate n well ion implantation. By shifting the position of the middle n well implantation region toward the deep n well implant region, it ultimately reduces the resistance of the n well to compensate for the latch-up characteristics that can be vulnerable.
상기의 기술적 과제를 달성하기 위하여 본 발명으로부터 제공되는 특징적인 반도체 소자의 삼중웰 형성방법은, 반도체 기판에 0.8∼1.6MeV의 이온주입 에너지와 5X1012∼2X1013ions/㎠의 도즈 조건으로 깊은 제1 도전형 웰 이온주입 영역을 형성하는 제1 단계; 500∼600keV의 이온주입 에너지와 5X1012∼2X1013ions/㎠의 도즈 조건으로 중간 제1 도전형 불순물 이온주입 영역을 형성하는 제2 단계; 제2 도전형 불순물 이온주입 영역을 형성하는 제3 단계; 및 열처리를 실시하여 상기 반도체 기판 내에 주입된 불순물을 활성화하는 제4 단계를 포함하여 이루어진다.In order to achieve the above technical problem, a method of forming a triple well of a semiconductor device, which is provided from the present invention, is characterized in that the ion implantation energy of 0.8 to 1.6 MeV and the dose condition of 5X10 12 to 2X10 13 ions / cm 2 are applied to a semiconductor substrate. Forming a first conductivity type well ion implantation region; A second step of forming an intermediate first conductivity type impurity ion implantation region under an ion implantation energy of 500 to 600 keV and a dose condition of 5X10 12 to 2X10 13 ions / cm 2; A third step of forming a second conductivity type impurity ion implantation region; And a fourth step of activating impurities implanted in the semiconductor substrate by performing a heat treatment.
이하, 본 발명이 속한 기술분야에서 통상의 지식을 가진 자가 본 발명을 보다 용이하게 실시할 수 있도록 하기 위하여 본 발명의 바람직한 실시예를 소개하기로 한다.Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.
첨부된 도면 도 4a 내지 도 4e는 본 발명의 일 실시예에 따른 삼중웰 형성 공정을 도시한 것으로, 이하 이를 참조하여 설명한다.4A to 4E illustrate a triple well forming process according to an embodiment of the present invention, which will be described below with reference to the drawings.
본 실시예에 따른 공정은 우선 도 4a를 참조하면, 실리콘 웨이퍼(51)에 STI 공정을 진행하여 필드 산화막(42)을 형성한다.Referring to FIG. 4A, a process according to the present embodiment first performs an STI process on a silicon wafer 51 to form a field oxide film 42.
이어서, 도 4b에 나타낸 바와 같이 깊은 n웰 형성을 위한 마스크 공정을 수행하여 포토레지스트 패턴(43)(고에너지 전용 포토레지스트를 사용하며, 1∼10g/㎤의 밀도와 2.5㎛ 이상의 두께를 요구)을 형성하고 이를 이온주입 마스크로 고에너지 이온주입기를 사용한31P 이온주입을 수행하여 깊은 n웰 이온주입 영역(44)을 형성한다. 이때, 접합 누설전류 특성을 고려하여 이온주입 에너지는 종전과 비슷한 0.8∼1.6MeV로 하고,31P 이온의 도즈를 5X1012ions/㎠∼2X1013ions/㎠로 낮추어 설정하여 이온주입을 수행한다.Subsequently, as shown in FIG. 4B, a mask process for forming a deep n well is performed to form a photoresist pattern 43 (using a high energy dedicated photoresist, requiring a density of 1 to 10 g / cm 3 and a thickness of 2.5 μm or more). Is formed and 31 P ion implantation is performed using a high energy ion implanter as an ion implantation mask to form a deep n well ion implantation region 44. At this time, the ion implantation energy is set to 0.8 to 1.6 MeV, similar to the conventional one, in consideration of the junction leakage current characteristics, and ion implantation is performed by setting the dose of 31 P ions to 5 × 10 12 ions / cm 2 to 2 × 10 13 ions / cm 2.
다음으로, 도 4c에 나타낸 바와 같이 n웰 형성을 위한 마스크 공정을 실시하여 포토레지스트 패턴(45)을 형성하고 이를 이온주입 마스크로 고에너지 이온주입기를 사용한 중간 n웰 이온주입 및 p채널 필드스탑 이온주입 공정을 수행하여 프로파일드 n웰을 형성한다. 이때, 중간 n웰 이온주입은31P 이온을 사용하고, 도즈는 5X1012ions/㎠∼2X1013ions/㎠, 이온주입 에너지는 500keV∼600keV로 조절하는 것이 바람직하며, p채널 필드스탑 이온주입은31P 이온을 사용하고, 도즈는 5X1011ions/㎠∼1X1013ions/㎠, 이온주입 에너지는 150keV∼300keV로 조절하는 것이 바람직하다. 이때, 도면 부호 '46'은 중간 n웰 이온주입 영역, '47'은 p채널 필드스탑 이온주입 영역, '48'은 프로파일드 n웰의 프로파일을 각각 나타낸 것이다.Next, as illustrated in FIG. 4C, a mask process for forming an n well is performed to form a photoresist pattern 45, and the intermediate n well ion implantation and p-channel field stop ions using a high energy ion implanter as an ion implantation mask are formed. An implantation process is performed to form a profiled n well. In this case, the intermediate n well ion implantation is 31 P ions, the dose is 5X10 12 ions / ㎠ ~ 2X10 13 ions / ㎠, ion implantation energy is preferably adjusted to 500keV ~ 600keV, p-channel field stop ion implantation 31 P ions are used, the dose is preferably 5X10 11 ions / cm 2 to 1X10 13 ions / cm 2, and the ion implantation energy is adjusted to 150 keV to 300 keV. In this case, reference numeral '46' denotes an intermediate n well ion implantation region, '47' denotes a p-channel field stop ion implantation region, and '48' denotes a profile of a profiled n well.
이어서, 도 4d에 나타낸 바와 같이 포토레지스트 패턴(45)을 제거한 다음, p웰 형성을 위한 마스크 공정을 실시하여 포토레지스트 패턴(49)을 형성하고, 역시 고에너지 이온주입기를 사용하여 p웰 이온주입 및 n채널 필드스탑 이온주입을 수행하여 프로파일드 p웰을 형성한다. 이때, p웰 이온주입은 1X1013ions/㎠∼5X1013ions/㎠의 B 이온 도즈, 180keV∼300keV의 이온주입 에너지 조건을 사용하는 것이 바람직하며, n 채널 필드스탑 이온주입은 5X1011ions/㎠∼1X1013ions/㎠의 B 이온 도즈, 80keV∼100keV의 이온주입 에너지 조건을 사용하는 것이 바람직하다. 도면 부호 '50'은 p웰 이온주입 영역, '51'은 n채널 필드스탑 이온주입 영역, '52'는 프로파일드 p웰의 프로파일을 각각 나타낸 것이다.Subsequently, as shown in FIG. 4D, the photoresist pattern 45 is removed, followed by a mask process for forming a p-well to form a photoresist pattern 49, and also a p-well ion implantation using a high energy ion implanter. And n-channel field stop ion implantation to form a profiled p well. In this case, p-well ion implantation is 1X10 13 ions / ㎠~5X10 13 ions / ㎠ of B ion dose, it is preferred to use the ion implantation energy condition of 180keV~300keV, n-channel field-stop ion implantation is 5X10 11 ions / ㎠ It is preferable to use a B ion dose of ˜1 × 10 13 ions / cm 2 and an ion implantation energy condition of 80 keV to 100 keV. Reference numeral '50' denotes a p well ion implantation region, '51' denotes an n-channel field stop ion implantation region, and '52' denotes a profile of a profiled p well.
다음으로 도 4e를 참조하면, 포토레지스트 패턴(49)을 제거한 다음, 퍼니스(furnace) 어닐 공정을 통해 이온주입된 불순물을 활성화시켜 n웰(64)과, 제1 p웰(63), n웰(64)로 둘러싸인 제2p 웰(65) 등 2개의 p웰과 1개의 n웰을 형성한다. 이때, 퍼니스 열처리는 900℃∼1000℃의 N2분위기에서 30분∼90분 동안 수행된다. 이때, 추가적으로, 급속열처리(RTP)를 실시할 수 있으며, 그 조건은 다음과 같이 수행한다.Next, referring to FIG. 4E, after removing the photoresist pattern 49, the impurities implanted through the furnace annealing process are activated to activate the n well 64, the first p well 63, and the n well. Two p wells and one n well are formed, such as a second p well 65 surrounded by 64. At this time, the furnace heat treatment is performed for 30 minutes to 90 minutes in an N 2 atmosphere of 900 ℃ to 1000 ℃. At this time, in addition, rapid thermal treatment (RTP) can be carried out, the conditions are carried out as follows.
가) RTP 온도 : 900℃∼1100℃.A) RTP temperature: 900 ° C to 1100 ° C.
나) RTP 시간 : 30초∼5분.B) RTP time: 30 seconds to 5 minutes.
다) 승온 속도(ramp-up rate) : 30℃/초∼250℃/초.C) ramp-up rate: 30 ° C./sec. To 250 ° C./sec.
라) 분위기 가스 및 유량비 : N2, 1∼20slpm.D) Atmospheric gas and flow rate ratio: N 2 , 1-20slpm.
마) 냉각 속도(ramp-down rate) : 20℃/초∼100℃/초.E) ramp-down rate: 20 ° C / sec to 100 ° C / sec.
이후, 각 웰(63, 64, 65) 상에 트랜지스터를 형성한다.Thereafter, a transistor is formed on each well 63, 64, 65.
첨부된 도면 도 5a는 깊은 n웰 이온주입 공정 조건(도즈 및 이온주입 에너지)에 따른 p+접합/n웰 누설전류 특성을 도시한 것이고, 도 5b는 중간 n웰 이온주입 공정 조건(도즈 및 이온주입 에너지)에 따른 p+접합/n웰 누설전류 특성을 도시한 것이며, 도 5c는 p웰 이온주입 공정 조건(도즈 및 이온주입 에너지)에 따른 n+접합/p웰 누설전류 특성을 도시한 것으로, 전술한 본 발명의 일 실시예에 따를 경우, 누설전류 특성이 우수함을 확인할 수 있다.5a shows p + junction / n well leakage current characteristics according to deep n well ion implantation process conditions (dose and ion implantation energy), and FIG. 5b shows intermediate n well ion implantation process conditions (dose and ion) P + junction / n well leakage current characteristics according to the implantation energy), Figure 5c shows the n + junction / p well leakage current characteristics according to the p well ion implantation process conditions (dose and ion implantation energy) According to one embodiment of the present invention described above, it can be confirmed that the leakage current characteristics are excellent.
첨부된 도면 도 6a 및 도 6b는 삼중웰 형성시 접합-웰 거리에 따른 홀딩 전압 특성을 각각 제2 p웰/n웰 및 제1 p웰/n웰에 대해 측정한 특성도로서, 중간 n웰 이온주입시 도즈 및 이온주입 에너지 조건에 따라 그 특성에 큰 차이를 보이고 있으며, 전술한 본 발명의 일 실시예에 따라 중간 n웰 이온주입 영역을 깊은 n웰 이온주입 영역 쪽으로 이동시킬 경우, n웰의 저항이 감소되고 궁극적으로 래치-업 특성이 개선됨을 확인할 수 있다.6A and 6B are characteristic diagrams of holding voltage characteristics of the second p well / n well and the first p well / n well, respectively, according to a junction-well distance when forming triple wells. The ion implantation shows a large difference in the characteristics according to the dose and ion implantation energy conditions, when moving the intermediate n well ion implantation region toward the deep n well ion implantation region according to an embodiment of the present invention described above, n well It can be seen that the resistance of the circuit is reduced and ultimately the latch-up characteristic is improved.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
예를 들어, 전술한 실시예에서는 n웰과, 제1 p웰, n웰로 둘러싸인 제2p 웰 등 2개의 p웰과 1개의 n웰을 형성하는 경우를 일례로 들어 설명하였으나, 본 발명은 이와 도전형을 반대로 하여 1개의 p웰과 2개의 n웰을 형성하는 경우에도 적용할 수 있다.For example, in the above-described embodiment, an example of forming two p wells and one n well, such as an n well, a first p well, and a second p well surrounded by n wells, has been described. The same applies to the case of forming one p well and two n wells by reversing the molds.
전술한 본 발명은 삼중웰 구조를 채용하는 반도체 소자의 누설전류의 감소와 더불어 래치-업 특성을 개선할 수 있는 효과가 있으며, 이로 인하여 신뢰성 높은 고품질의 반도체 소자의 제조를 가능하게 한다.The present invention described above has the effect of improving the latch-up characteristics together with the reduction of the leakage current of the semiconductor device employing the triple well structure, thereby enabling the manufacture of high quality semiconductor devices with high reliability.
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