KR100252879B1 - Sub wordline driver of semiconductor device - Google Patents

Abstract

PURPOSE: A sub word line driver of a semiconductor device is provided to be suitable to prevent the sub word line from being floated and to minimize the layout of the semiconductor device by using a PMOS transistor(PM) having lower threshold voltage, thereby enhancing the integrity of the semiconductor device. CONSTITUTION: The sub word line(SWL) acts as preventing a word line from being floated. A PMOS transistor(PM) has threshold voltage lower than that of a cell transistor for storing data, and is operated by a global word bar line signal applied to a gate. A drain and a source of an NMOS transistor(NM) are respectively connected to a drain of the PMOS transistor(PM) and a ground. The sub word line(SWL) is connected to a common drain of the PMOS transistor(PM) and NMOS transistor(NM).

Description

Sub word line driver of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a sub word line driver for semiconductor devices suitable for reducing chip size and improving low voltage characteristics.

In general, as the integration of devices increases and the cell size decreases, the number of cells connected to a word line increases.

One of the problems caused by this is that as the number of cells connected to the word line increases, the capacitance of the word line increases and the word line needs to be long, resulting in an increase in the resistance, thereby degrading the speed characteristic.

In addition, as the cell size becomes smaller, the pitch of the word line is also reduced, resulting in process difficulties.

In order to solve the above problems, concepts of a word shunt scheme and a hierarchical wordline scheme have been proposed.

However, although the word shunt scheme can improve the speed, it is difficult to process because the pitch of the metal line is the same as the pitch of the sub word line.

In addition, although the layout of the hierarchical word line scheme is larger than that of the word shunt scheme, the layout is larger than that of the sub word line driver, it has been widely used due to the ease of processing because it can improve the speed and make the pitch of the metal line larger. .

Hereinafter, a sub word line driver of a conventional semiconductor memory device will be described with reference to the accompanying drawings.

1 is a configuration diagram of a self-boosting driver consisting of NMOS only.

As shown in FIG. 1, the self-boost driver according to the first embodiment of the present invention is composed of three NMOS transistors.

That is, the first NMOS transistor NM1 and the second NMOS transistor NM2 are configured in series, and the drain of the third NMOS transistor NM3 is connected to the gate of the first NMOS transistor NM1. .

Since the self-boost driver shown in FIG. 1 is composed of NMOS transistors, the area of the layout is small.

In the self-boost driver, when the gate control signal Vboot is applied, the third NMOS transistor NM3 is turned on.

Accordingly, the high level global word line signal GWL turns on the first NMOS transistor NM1 through the third NMOS transistor NM3.

Therefore, DXi is transferred to the sub word line SWL through the first NMOS transistor NM1.

2 is a configuration diagram of a CMOS sub word line driver according to the related art.

As shown in FIG. 2, the conventional CMOS sub word line driver is connected in parallel with the CMOS transistor 21 including the PMOS transistor PM, the first NMOS transistor NM1, and the PMOS transistor PM. And a second NMOS transistor NM2.

Here, the output terminal of the CMOS transistor 21 and the drain of the NMOS transistor NM2 are connected in common and are connected to the sub word line SWL.

This CMOS sub wordline driver has the advantages of high speed and easy timing control.

As shown in FIG. 2, the PMOS transistor PM is turned on by the signal GWLb of the low level global word bar line, and the first NMOS transistor NM1 remains off.

The second NMOS transistor NM2 is turned on by the global word line GWL signal to transfer the high level DXi signal to the subword line.

If the DXi is low level and the global word bar line GWLb is low level, the first and second NMOS transistors NM1 and NM2 are turned off.

In this case, the second NMOS transistor NM2 is turned on as the global word line signal in order to prevent the subword line from floating.

3 is another embodiment of a conventional CMOS sub word line driver, and twists the global word line GWL to eliminate coupling noise of a floating word line during word line active.

As shown in FIG. 3, a CMOS sub word line driver according to another exemplary embodiment is a CMOS transistor including two transistors, a PMOS transistor PM and an NMOS transistor NM in series.

Compared with FIG. 1 or FIG. 2, two transistors are used to reduce the layout area.

As shown in FIG. 3, the PMOS transistor PM is turned on and the NMOS transistor NM is turned off by the global word bar line GWLb having a low level.

Accordingly, the high level DXi signal is transmitted to the subword line through the PMOS transistor PM.

When the word line is active, the global word line is twisted to remove coupling noise of the floating word line.

That is, by replacing the floating word line with a word line that is reliably kept low, the coupling noise of the word line is reduced.

However, the sub word line driver of the conventional semiconductor device as described above has the following problems.

First, the NMOS self-boost driver needs to boot the global word line with the Vboot signal, which requires a timing METCH of the global word line and Vboot and a high gate voltage is applied to the gate insulating film, which degrades device reliability. .

Second, the CMOS sub word line driver using three transistors increases the area of the layout because N wells are needed to make the PMOS transistor, and the pitch of the metal lines is needed because two complement global word lines are required. ) Will decrease by that amount.

Third, in the case of another CMOS sub word line driver using two transistors, the word line of the DXi that is not selected becomes a floating state.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is a subword of a semiconductor device suitable for preventing a subword line from being floated using a PMOS transistor having a low threshold voltage and minimizing a layout to improve integration. The purpose is to provide a line driver.

1 is a circuit diagram of a conventional self-boost driver

2 is a circuit diagram illustrating a conventional CMOS sub word line driver.

3 is a circuit diagram illustrating a CMOS sub word line driver according to another exemplary embodiment of the present invention.

4 is a circuit diagram illustrating a CMOS sub wordline driver of the present invention.

Explanation of symbols for main parts of the drawings

PM: PMOS transistor NM: NMOS transistor

A sub word line driver of a semiconductor device according to the present invention for achieving the above object has a threshold voltage lower than a threshold voltage of a cell transistor for storing data in a sub word line for preventing a word line from floating. A PMOS transistor operated by a global word bar line signal applied to a gate, and a drain is connected to the drain of the PMOS transistor, the source is characterized in that it comprises a NMOS transistor connected to the ground terminal.

Hereinafter, a sub word line driver of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

4 is a circuit diagram illustrating a sub word line driver of a semiconductor device according to the present invention.

As shown in FIG. 4, the sub word line driver according to the present invention includes two transistors, that is, a PMOS transistor PM having a low threshold voltage and an NMOS transistor NM.

As shown in FIG. 4, when the global word bar line GWLb is active, ie, falls from a high level to a low level, the PMOS transistor PM is turned on and the NMOS transistor is not turned off. As the global word bar line GWLb falls from a high level to a low level, the PMOS transistor has a low threshold voltage and is immediately turned on.

Thereafter, the NMOS transistor NM is turned off.

Even when the NMOS transistor is turned off, the amount of active current flowing through the PMOS transistor PM is very small because the time that the global word line is transitioned is short.

Therefore, no problem occurs with the active current.

In standby mode, there is no leakage current, which keeps the Vpp level safe.

The operation description of the sub word line driver of the semiconductor device of the present invention will be described in detail as follows.

As shown in FIG. 4, when the voltage of the floating word line rises by the threshold voltage of the PMOS transistor having the low threshold voltage using the PMOS transistor PM having the low threshold voltage V _T , the PMOS transistor is used. (PM) is turned on to prevent the word line from rising at least by the threshold voltage of the PMOS transistor.

At this time, when low data is stored in the cell and the bit line is at a low level, there is no possibility that the data of the cell is inverted even if the voltage of the floating word line rises and the cell transistor is turned on. .

If the bit line is at a high level, there is a possibility that the data of the cell is gradually increased to a high level, but there is no possibility of completely inverting from a low to a high level.

In addition, as time passes, it drops back to the low level data by the liquid current.

A case where high-level data is stored in a cell will now be described.

That is, if the data stored in the cell is high level and the bit line is high level, the cell data is safely maintained because the word line does not rise to the Vpp level.

The PMOS transistor having a low threshold voltage is used to lower the threshold voltage of the PMOS transistor than the threshold voltage of the cell transistor so that the PMOS transistor is turned on before the cell transistor is turned on. The voltage can be controlled below the threshold voltage of the PMOS transistor.

As described above, the sub word line driver of the semiconductor device of the present invention has the following effects.

By using a PMOS transistor having a low threshold voltage, it is not necessary to configure an NMOS transistor separately so as not to float the word line, thereby minimizing the area of the layout.

In addition, the pitch of the metal line can be increased, so that the process can be easily implemented. As the PMOS transistor having a low threshold voltage can be used, the Wisth of the PMOS transistor can be reduced at the same speed, so that is normal. The area of the layout can be reduced in comparison with a PMOS transistor having a normal threshold voltage.

Claims (3)

A sub word line for preventing a word line from floating, A PMOS transistor having a threshold voltage lower than a threshold voltage of a cell transistor for storing data and operating by a global word bar line signal applied to a gate; And a source connected to the drain of the PMOS transistor and a source connected to the ground terminal of the PMOS transistor. The method of claim 1, And a sub word line connected to a common word drain of the PMOS transistor and the NMOS transistor. The method of claim 2, And the PMOS transistor prevents the sub word line from being floated by lowering the voltage of the sub word line below its threshold voltage.

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