KR100217253B1 - The encoding apparatus using general memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TV encoder device using a general memory. In the related art, a PC scanning method is a non-interlacing method and is composed of a plurality of lines in one frame. Since the scanning method of the PC is about twice as fast as the scanning method of the TV, the capacity of the line memory for image data processing varies depending on the resolution of the PC. In view of this, in the case of a constant resolution (640 × 480), at least a constant byte (640 bytes) is required for one line.

That is, in order to store the image data output from the PC and transmit the image data to the TV, two line memory for image data processing having a predetermined byte (640 byte) must be configured, thereby providing a cause for the rise of the product at a price. Therefore, when applied to the ASIC (ASIC), there was a problem that the size of the product increases.

Therefore, in order to solve such a problem, the present invention configures a memory for storing video information of a PC in a TV encoder as a single memory, and outputs the composite video signal of a non-interlaced VGA output TV from a PC. It is a TV encoder device using general memory that enables cost reduction in the production of TV encoder board and TV encoder ASIC.

Description

TV encoder device using general memory

1 is a block diagram showing the structure of a conventional TV encoder device.

(A)-(n) of FIG. 2 are the output waveform diagrams of each part produced by the conventional TV encoder apparatus.

3 is a block diagram showing the structure of a TV encoder device using the general memory of the present invention.

4A to 4Q are diagrams of output waveforms of each part generated by a TV encoder device using the general memory of the present invention.

* Explanation of symbols for main parts of the drawings

11: VGA control unit 12: storage means

13: memory controller 14: controller

15: conversion means 16: mixing unit

17: NTSC encoder section 18: first master line memory section

19: second master line memory unit 20: first slave line memory unit

21: second drive line memory unit 22: the first RAM D / A conversion unit

23: 2nd RAM D / A Converter

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TV encoder device using a general memory. In particular, the memory for storing image information of a PC in an encoder of a TV is configured as a single port memory (for example, SRAM, DRAM), The present invention relates to a TV encoder device using a general memory to output a non-interlaced VGA output as a composite video signal of a TV.

As shown in FIG. 1, the configuration and operation of a conventional TV encoder device are described. First, the PC image data PC-DATA of a plurality of lines 525 lines and the corresponding clock signal PCLK (PCLK) accordingly. / 2) and a VGA (Video Graphics Array) controller 1 for outputting a vertical / horizontal sync signal (PC-HS) (PC-VS) and a blank signal (PC-BLANK), and the VGA controller 1 Control unit 2 for controlling each part of the system according to the vertical / horizontal synchronization signal (PC-HS) / (PC-VS) and the blank signal (PC-BLANK) output from the; and according to the control of the control unit (2) Image data processing storage means (3) for storing PC image data (PC-DATA) of multiple lines (525 lines) output from the VGA controller (1), and multiple lines (525) output from the storage means (3). Conversion means (4) for converting image data (PC-DATA) of a line) into a predetermined RGB signal according to a non-interlace method, and then converting the same to an analog and outputting the analog data; And a mixing unit 5 for mixing and outputting a predetermined RGB signal converted into analog by the converting unit 4 and outputting the mixed RGB signal encoded by the mixing unit 5. NTSC encoder unit 6 for outputting the signal to a TV, and the storage means 3 has a VGA under the control of a predetermined clock signal PCLK (PCLK / 2) and the controller 2. Among the image data (525 lines) output from the control unit 1, certain lines (n, n + 2, ; n Under the control of the master line memory 7 for storing the image data PC-DATA of 1), and the input of the constant clock signal PCLK (PCLK / 2) and the controller 2, The predetermined lines (n, n + 2, stored in the master line memory unit 7, ; n Lines (n + 1, n + 3, adjacent) to prevent flicker from occurring in the image data (PC-DATA) of 1) : n Slave Line Memory (Slave Line Memory) 8 for storing the image data (PC-DATA) of 1).

Then, the converting means 4 is a predetermined line (n, n + 2, output from the master line memory unit 7 of the storage means 3, ; n The first RAM converts the image data PC-DATA of 1) into a predetermined RGB signal according to a non-interlace method, and then converts it to an analog and outputs it to the mixing unit 5. RAM D / A converting section 9 and adjacent lines (n + 1, n + 3, and the like) output from the slave line memory section 8 of the storage means 3; ; n A second RAM for converting the image data PC-DATA of 1) into a predetermined RGB signal according to a non-interlace method, and then converting the image data PC-DATA into an analog and outputting the analog data to the mixing unit 5; It consists of the D / A conversion unit 10.

Referring to the operation of the conventional TV encoder device configured as described above is as follows.

First, as shown in (e) of FIG. 2, one frame of constant image data (PC-DATA) of a PC having a constant horizontal synchronization line (PC-HS Line) is scanned in multiple lines (525 lines) in one frame. In order to output to the horizontal synchronous scanning line (NTSC-HS LINE) of the TV as shown in FIG. 2 (i), which is scanned as a predetermined line (262.5 lines), the VGA control unit 1 of the PC As shown in Figs. (A), (b) and (k), the predetermined clock signal PCLK (PCLK / 2) and the PC image data PC-DATA of the plurality of lines (525 lines) are stored in the image data processing storage means 3. When outputted to the configured master line and slave line memory units 7 and 8, the control unit 2 inputs the vertical / horizontal vertical synchronizing signal (PC-VS) of the PC input as shown in FIG. (L) of FIG. 2 in the master line and slave line memory sections 7 and 8 according to the blank signal PC-BLANK of the PC as shown in FIG. m) master-memite and slab like (n) The master line and slave line memory units 7 and 8 are controlled by outputting a live-memory write signal (MMW; Master Men Write).

For example, according to the master-memory signal MMW and the blank signal PC-BLANK outputted from the control unit 2, the master line memory unit 7 uses the TV NTSC system as shown in FIG. Schedule lines (e.g. NTSC) 15 lines) of a plurality of lines (525 lines) of PC image data (PC-DATA) of a certain line (eg PC) The image data (PC-DATA) (line 29) is initially written and stored.

In this case, the slave line memory unit 8 writes and stores a predetermined line (eg, PC) in the master line memory unit 7. In order to prevent the flicker phenomenon in the image data PC-DATA of 29 lines, the predetermined line (eg PC) 29 (e.g., PC) adjacent to the image data PC-DATA of FIG. The image data PC-DATA of 28 lines is written and stored according to the slave-memory signal SMW output from the controller 2.

Thereafter, the controller 2 outputs a master-membrane and a slave-membrane signal (MMR; Master Men Read) (SMR; Slave Mem Read) to the master line and the slave line memory units 7 and 8. In this case, certain lines (eg, PCs) stored in the master line and the slave line memory units 7 and 8 are stored. A line (eg, PC) adjacent to the image data PC-DATA of 29 lines) The first and second RAM D / A converters 9 and 10 of the conversion means 4 are read out while reading the image data PC-DATA of 28 lines).

In the first RAM D / A conversion unit 9 configured in the conversion means 4, a predetermined line (eg, PC) stored and read in the master line memory unit 7 is output. Video data (PC-DATA) of 29 lines) is converted into a predetermined RGB signal according to a non-interlace method, and then converted into an analog and outputted to the mixing unit 5, In the second RAM D / A conversion unit 10 configured in the conversion means 4, a certain line (eg PC) 29 lines) As ancillary data for controlling the flicker phenomenon of the image data PC-DATA, a proximity line (eg, PC) stored and read in the slave line memory unit 8 and outputted. After converting the image data (PC-DATA) of the 28 lines) into a predetermined RGB signal according to the non-interlace method, the image data PC-DATA is converted to analog and output to the mixing unit 5.

Therefore, the mixing section 5 mixes a predetermined RGB signal which is converted into analog and output by the first and second RAM D / A converters 9 and 10, and as shown in FIG. As you can see schedule line (e.g. PC 28 lines, PC PC image data (PC-DATA) of 29 lines is a certain line (e.g. NTSC) of TV NTSC system. 15 lines) to output one video RGB signal to the NTSC encoder unit 6. FIG.

In other words, by repeating the above-described operation, the constant image data on the PC is transmitted to the TV, and the NTSC encoder section 5 shows the constant image data on the PC to be transferred (f) (g) of FIG. As shown in (h), a composite image that can be displayed on a TV screen according to the NTSC-type vertical and horizontal synchronous signals (NTSC-VS) (NTSC-HS) and color signals (NTSC-CS) output by the control unit 2 It is encoded as a signal and a luminance (Y) / color (C) signal.

However, the conventional TV encoder device is a non-interlaced method of PC scanning and is composed of a plurality of lines (525 lines) in one frame, and the scanning method of an NTSC TV is composed of a predetermined line (262.5) in one frame. Since the scanning method of the PC is about twice as fast as that of the TV, the capacity of the line memory 9 and 10 for image data processing varies according to the resolution of the PC. In view of this, at a constant resolution (640 x 480), at least a constant byte (640 bytes) is required for one line.

That is, in order to store the image data output from the PC and to transmit the image data to the TV, two line memory for image data processing having a predetermined byte (640 bytes) must be configured, thereby providing a cause for the rise of the product at a price. Accordingly, when applied to the ASIC (Application Specific Inergrated Circuit), there was a problem that the size of the product increases.

Therefore, in order to solve such a problem, the present invention configures a memory for storing image information of a PC in a TV encoder into a single port memory (for example, SRAM and DRAM), thereby reducing the need for a PC. It aims to achieve cost reduction in the production of TV encoder boards and TV encoder ASICs by outputting non-interlaced VGA outputs as composite video signals of TVs.

The configuration and operation of a TV encoder device using the general memory of the present invention for achieving the above object will be described with reference to FIG. 3.

First, PC image data PC-DATA of a plurality of lines 525 lines, and a constant clock signal PCLK (PCLK / 2) and vertical / horizontal synchronization signal PC-HS (PC-VS) accordingly. And a video graphics array (VGA) controller 11 for outputting a blank signal (PC-BLANK), and PC image data (PC-DATA) of a plurality of lines (525 lines) output from the VGA controller 1. A storage means 12 for storing the data; a memory controller 13 for controlling write / read operations of the storage means 12; and a vertical / horizontal sync signal (PC-HS) / outputted from the VGA controller 11; The controller 14 which controls the system according to the PC-VS, the blank signal PC-BLANK, and the write / read operation of the memory controller 13, and the write / read-controlled by the memory controller 13 After converting the image data (PC-DATA) of the multiple lines (525 lines) of the storage means 12 to a predetermined RGB signal according to the non-interlace method, it is converted into an analog signal. A conversion unit 15 for outputting, a mixing unit 16 for mixing and outputting a predetermined RGB signal which is converted into analog by the conversion unit 15 and outputted, and a fixed RGB mixed by the mixing unit 16. NTSC encoder unit 17 for encoding a signal and outputting a composite video signal to a TV. The storage unit 12 includes a predetermined clock signal PCLK (PCLK / 2) and a memory controller. Lines n, n + 4, n + 8, and the like output from the VGA controller 11 according to the write / read control of (13). : n A first master line memory unit 18 storing the image data PC-DATA of 1) and the first master line memory unit under the write / read control of the memory controller 13; 18, a certain line (n + 2, n + 6, n + 10, by the following procedure) : n According to the second master line memory unit 19 for storing the image data PC-DATA of 1) and the write / read control of the input constant clock signal PCLK (PCLK / 2) and the memory controller 13 The predetermined lines n, n + 4, n + 8, stored in the first and second master line memory units 18, 19, ; n 1) (n + 2, n + 6, n + 10, : n Lines n + 1, n + 5, n + 9, which are adjacent to prevent flicker occurring in the image data PC-DATA of 1) : n 1) (n + 3, n + 7, n + 11, : n And first and second slave line memory units 20 and 21 for storing the image data PC-DATA of 1).

In addition, the conversion means 15 is a predetermined line (n, n + 4, n + 8, output from the memory control unit 13, : n 1) (n + 2, n + 6, n + 10, : n The first RAM converts the image data PC-DATA of 1) into a predetermined RGB signal according to a non-interlace method, and then converts it to an analog and outputs it to the mixing unit 16. RAM D / A converter 22 and adjacent lines (n + 1, n + 5, n + 9) outputted from the memory controller 13; : n 1) (n + 3, n + 7, n + 11, ; n A second RAM for converting the image data PC-DATA of 1) into a predetermined RGB signal according to a non-interlace method, and then converting the image data PC-DATA into an analog and outputting the analog data to the mixing unit 16. It consists of the D / A conversion unit 23.

Referring to the operation of the TV encoder (TV Encoder) using the general memory of the present invention configured as described above is as follows.

First, as shown in (e) of FIG. 4, one frame of constant image data (PC-DATA) of a PC having a constant horizontal synchronization line (PC-HS Line) is scanned in a plurality of lines (525 lines) in one frame. In order to output to the horizontal synchronous scanning line (NTSC-HS LINE) of the TV as shown in FIG. 4 (i), which is scanned as a predetermined line (262.5 lines), the VGA controller 11 of the PC As shown in Figs. (A), (b) and (k), the constant clock signal PCLK (PCLK / 2) and the PC image data PC-DATA of the predetermined line 525 are stored in a single port memory (for example; Output to the first and second master lines and the first and second slave line memory sections 18, 19, 20, 21 configured in the storage means 12 having the characteristics of SRAM or DRAM, The memory controller 13 controlling the write / read operation of the storage means 12 includes: a first master-memlite and a first slave-membra signal MMW1 as shown in FIG. 4 (l) (m); Master Men Write) (SMW1; Slav e Men Write) to control the first master line and the first slave line memory units 18 and 20.

For example, when the memory controller 13 outputs the first master-memory signal MMW1 to the first master line memory unit 18, the first master line memory unit 18 is shown in FIG. 4. Certain lines in the TV NTSC system (262.5 lines) as in (i) (e.g. NTSC Of the PC image data PC-DATA of the predetermined line 525 to display the vertical / horizontal sync signal (PC-VS) of the control unit 14 as shown in FIG. 4 (c) (d) (j). A certain line (e.g. PC) blanked by (PC-HS) and blank signal (PC-BLANK) The image data PC-DATA of 27 lines is initially written and stored, and a predetermined line (eg, written in the first slave line memory unit 18) is written and stored in the first master line memory unit 18. PC In order to prevent the flicker phenomenon generated from the image data PC-DATA of 27 lines, the predetermined line (eg PC) A line (eg, PC) adjacent to the image data PC-DATA of 27 lines The image data PC-DATA of 28 lines is written and stored according to the first slide-memory signal SMW1 output from the memory controller 13, and as shown in FIG. In NTSC, a certain line (eg, 15 lines) is formed.

Thereafter, the memory controller 13 may include a first master member and a first slave member in the first master line and the first slave line memory units 18 and 20, as shown in FIG. 4 (n). A predetermined line (eg, PC) stored in the first master line and the first slave line memory units 18 and 20 while outputting a read signal MMR1 (Master Men Read) (SMR1; Slave Men Read). Lines (eg, PC) adjacent to the image data PC-DATA of 27 lines The first and second RAM D / A converters 22 and 23 configured in the conversion means 15 are outputted through the memory controller 13 while reading the image data PC-DATA of 28 lines).

Meanwhile, certain lines (eg, PCs) stored in the first master line memory unit 18 and the first slave line memory unit 20 according to read control by the memory controller 13 may be used. Lines (eg, PC) adjacent to image data PC-DATA of 27 lines During the read operation of the image data PC-DATA of 28 lines, the second master line memory unit 19 and the second slave line memory unit 21 configured in the storage unit 12 are controlled.

That is, in the second master line memory unit 19, a predetermined line (eg, PC) written and stored in the first master line memory unit 18 is stored. While the image data (PC-DATA) of 27 lines are read, a certain line (e.g., NTSC) in the TV NTSC system (262.5 lines) as shown in FIG. 4 (i). The predetermined line (e.g., PC) among the plurality of lines (525 lines) of the PC image data (PC-DATA) blanked by the blank signal (PC-BLANK) of the controller 14 to display the 16 lines). A schedule line (eg, PC) that can follow the image data (PC-DATA) of line 27 The image data PC-DATA of the line 29) is outputted from the memory controller 13 and stored in accordance with the second master-memory signal MMW2 as shown in FIG. 4 (o). In the slave line memory unit 21, a predetermined line (eg, PC) is written and stored in the second master line memory unit 19. In order to prevent the flicker phenomenon generated from the image data PC-DATA of 29 lines, the predetermined line (eg PC) A line (eg, PC) adjacent to the image data PC-DATA of 29 lines The image data PC-DATA of 30 lines) is written and stored according to the second slave-memory signal SMW2 outputted from the memory controller 13 as shown in FIG. As shown in (i) of FIG. 4, a certain line (eg, 16 lines) is configured in the NTSC system of the TV.

When the read operation is completed in the first master line memory unit 18 and the first slave line memory unit 20, the second master line memory unit 19 and the second slave line memory unit ( In FIG. 21, as shown in FIG. 4A, a predetermined line (eg, stored in accordance with the second master-memory read signal and the second slave-memory read signal MMR2 and SMR2) outputted from the memory controller 13 (eg; PC A line (eg, PC) adjacent to the image data PC-DATA of 29 lines The image data PC-DATA (line 29) is outputted to the first and second RAM D / A converters 22 and 23 configured in the converter 15 through the memory controller 13.

Accordingly, the first RAM D / A converter 22 configured in the conversion means 15 stores a predetermined line (eg, PC) which is stored and read in the first and second master line memory units 18 and 29. 27 lines) (e.g. PC 29-line video data (PC-DATA) are arranged in a non-interlace method and converted into a master RGB signal, and then converted into analog and output to the mixing unit 16. In the second RAM D / A conversion unit 23 configured in the conversion means 15, a predetermined line (for example, PC) 27 lines) (e.g. PC As an auxiliary data for controlling the flicker phenomenon generated in the image data PC-DATA of the 29th line, it is stored in the first and second slave line memory units 20 and 21 and read and output. Line (e.g. PC 28 lines) (e.g. PC The video data (PC-DATA) of 30 lines) is converted into a Slave RGB signal by arranging according to the non-interlace method, and then converted into analog and outputted to the mixing unit 16.

At this time, the mixing unit 16 mixes the master and slave RGB signals, which are converted into analog by the first and second RAM D / A converters 22 and 23, and are mixed with each other. as shown in i) 27 lines, PC 28 lines) (e.g. PC 29 lines, PC PC image data (PC-DATA) of 30 lines) is a certain line (Dp; NTSC) of TV NTSC system. 15 lines) (e.g. NTSC 16 lines) to output one video RGB signal to the NTSC encoder unit 6.

In other words, by repeating the above-described operation, the constant image data on the PC is transmitted to the TV, and the NTSC encoder unit 17 shows the constant image data on the PC to be transmitted. As shown in (h), a composite image that can be displayed on a TV screen according to the NTSC-type vertical and horizontal synchronization signals (NTSC-VS) (NTSC-HS) and color signals (NTSC-CS) output by the control unit 14. It is encoded as a signal and a luminance (Y / color (C) signal.

As described above, the present invention configures a memory for storing video information of a PC in an encoder of a TV into a single port memory (for example, SRAM and DRAM), thereby providing a non-interlace (PC) in a PC. It is possible to achieve cost reduction in the production of TV encoder board and TV encoder ASIC by enabling the output of non-interace type VGA output as a composite video signal of TV.

Claims (4)

VGA control unit 11 for outputting a plurality of lines of PC image data, a constant clock signal, vertical / horizontal synchronization signal, and a blank signal, and storing for storing a plurality of lines of PC image data output from the VGA controller 11. Means 12, a memory controller 3 for controlling the write / read operation of the storage means 12, a vertical / horizontal sync signal and a blank signal output from the VGA controller 11, and the memory controller 13 Image data of a plurality of lines of the control unit 14 for controlling the system according to the write / read operation in the storage unit and the storage unit 12 that is write / read controlled by the memory control unit 13 according to the non-interlace method. A conversion unit 15 for converting a predetermined RGB signal and converting the same into an analog and outputting the analog signal; and a mixing unit 16 for mixing and outputting a predetermined RGB signal that is converted into analog by the conversion means 15 and outputted. , The mixing unit A TV encoder device comprising an NTSC encoder section 17 for encoding a predetermined RGB signal mixed by 16 to output a composite video signal to a TV, wherein the storage means 12 is input. A predetermined line (n, n + 4, n + 8) outputted by the VGA controller 11 according to the predetermined clock signal and the write / read control of the memory controller 13 : n The first master line memory unit 18 storing the image data of 1) and a predetermined line according to the next procedure of the first master line memory unit 18 according to the write / read control of the memory controller 13. n + 2, n + 6, n + 10, : n And a second master line memory unit (19) for storing the image data of 1). 2. The storage device of claim 1, wherein the storage means 12 stores a predetermined clock signal stored in the first and second master line memory units 18 and 19 according to a predetermined clock signal and a write / lead control of the memory controller 13. Line (n, n + 4, n + 8, ; n 1) (n + 2, n + 6, n + 10, ; n Lines (n + 1, n + 5, n + 9, adjacent) to prevent flicker occurring in the image data of 1) : n 1) (n + 3, n + 7, n + 11, ; n A TV encoder apparatus using a general memory, characterized in that it further comprises a first and second slave line memory unit (20, 21) for storing the image data of 1). The method of claim 1, wherein the conversion means 15 is a predetermined line (n, n + 4, n + 8, output from the memory control unit 13) : n 1) (n + 2, n + 6, n + 10, : n A first RAM D / A converter 22 for converting the image data of 1) into a predetermined RGB signal according to a non-interlace method, and then converting the image data into an analog signal and outputting the analog data to the mixing unit 16; The adjacent lines output from (13) (n + 1, n + 5, n + 9, : n 1) (n + 3, n + 7, n + 11, ; n And a second RAM D / A converter 23 for converting the image data of 1) into a predetermined RGB signal according to a non-interlace method, converting the image data into an analog signal, and outputting the analog data to the mixing unit 16. TV encoder device using a conventional memory. The characteristics of the SRAM or DRAM according to claim 1 or 2, wherein the write / read and storage operation states of each of the memory units 18, 19, 20, and 21 configured in the storage means 12 are single port memories. TV encoder device using a general memory, characterized in that using.