KR0167169B1 - Data receive/transmit apparatus - Google Patents

Abstract

The present invention relates to a data transmission / reception apparatus, which is configured to share one memory area through different address buses and data buses in order to transmit and receive data between two processors, thereby improving processing speed, reducing component count, and minimizing power consumption. will be.

As described above, the present invention includes first and second decoding means for decoding an address provided from each of the first and second CPUs and outputting the chip selection signal; The memory area is selected by the chip selection signals obtained by the first and second decoding means, and the corresponding addresses are provided according to the addresses, read / write signals, address selection signals, and clocks provided from the first and second CPUs, respectively. This is achieved by synchronizing and storing data in the dual port RAM which selects the stored data and provides them to the first and second CPUs.

Description

Data transceiver

1 is a block diagram of a conventional data transmission and reception apparatus.

2 is a configuration diagram of a data transmitting and receiving device of the present invention.

* Explanation of symbols for main parts of the drawings

200: first central processing unit 201: second central processing unit

202: first decoding unit 203: second decoding unit

204: dual pod RAM 205: first address bus

206: Second address bus 207: First data bus

208: second data bus

The present invention relates to data transmission and reception between two processors sharing an address and a data bus. More particularly, the present invention relates to an independent address and data between a common central processing unit in an elevator group management system and a central processing unit board for boarding call processing. The present invention relates to a data transceiver for transmitting and receiving data by sharing one dual port RAM area through a bus.

In general, in the elevator group management system, transmitting and receiving data by sharing data and address buses between two processors that require high-speed processing not only decreases processing speed, but also causes a lot of hardware design burden.

Therefore, if data is transmitted and received between two processors under an independent bus system, the burden on processing speed and hardware is reduced.

1 is a block diagram of a data transmission / reception apparatus of a conventional elevator group management system. The address transmitted from the first central processing unit 100 for group management of an elevator is received through the address bus 105, decoded, and read / A first address decoding unit 101 for outputting a recording signal; A first buffer unit 102 which receives the data transmitted from the first central processing unit 100 through the data bus 104 and bidirectionally buffers the data to be transmitted through the data bus 104; The first and third registers 103a and 103c receive data buffered from the first buffer unit 102 through the data bus 104 according to the read / write signal output from the first address decoding unit 101. A register group 103 for writing to the first central processing unit 100 through the data bus 104 and the first buffer unit 102 or the data recorded in the second register 103b; A second central processing unit (106) for transmitting and receiving information to and from the first central processing unit (100) and in charge of boarding process; Decodes an address generated by the second central processing unit 106 to generate a read signal in the first and third registers 103a and 103c of the register group 103 and to write it in the second register 103b. A second address decoding unit 107 for generating a signal; A ROM 108 for chip selection according to the read / write signal generated by the second address decoding unit 107 to generate an address corresponding to data generated by the second central processing unit 106; A data RAM 110 chip-selected according to a read / write signal generated by the first address decoder 107 to generate data corresponding to an address generated by the rob 108 and to store input data; According to the read / write signal generated by the second address decoding unit 107, the data generated by the data RAM 110 is buffered and stored in the second register 103b of the register group 103. The second buffer unit 109 which reads the data stored in the third registers 103a and 103c, stores the data stored in the data RAM 110 and provides the stored data to the second CPU 106 via the ROM 108. )Wow; Input / output provided by the second buffer unit 109 to the first and second central processing unit (100, 106) to transfer the data buffered to the external device, and the data input therefrom as information necessary for military management It consists of the port 111.

The conventional data transmitting / receiving apparatus configured as described above, first, the address bus 105 and the data bus 104 between the first central processing unit 100 for military management and the second central processing unit 106 for processing boarding hall calling are performed. The data is written to or read from the register group 103 using the address bus and the data bus independently of each other.

Specifically, when the first central processing unit 100 for military management wants to record data in the register group 103 provided in the board of the second central processing unit 106, 1 When the central processing unit 100 provides the addresses and data necessary for recording to the first address decoding unit 101 and the first buffer unit 102 via the address bus 105 and the data bus 104, respectively. The first address decoding unit 101 combines the input addresses to write signals. And the buffering direction signal are provided to the first, third registers 103a and 103c and the first buffer unit 102 of the register group 103 to enable them.

In addition, the first buffer unit 102 buffers data input by the buffering direction signal provided from the first address decoding unit 101 and write-enabled by the first address decoding unit 101. The data is written to the third registers 103a and 103c to complete the write operation.

On the other hand, in order for the second central processing unit 106 for boarding hall calling processing to read data recorded in the first and third registers 103a and 103c of the register group 103, an address for reading is provided. 2 to the address decoding unit 107.

In the above description, the first and second address decoding units 101 and 107 are programmable ROMs for selectively selecting data stored in the register group 103.

The second address decoding unit 107 combines the address input from the second CPU 106 and reads the signal. Is provided to the first and third registers 103a and 103c of the register group 103, and the chip selection signal Is provided to the second buffer unit 109, the ROM 108, and the data RAM 110.

The first and third registers 103a and 103c of the register group 103 are read signals provided from the second address decoding unit 107. The pre-stored data is provided to the second buffer unit 109 via the data bus 104.

The first to third registers 103a to 103c are registers capable of storing four bits, respectively.

Subsequently, the second buffer unit 109 buffers the data input from the first and third registers 103a and 103c by the second address decoding unit 107 and stores the data in the data RAM 110. The ROM 108 may be provided to the second CPU 106 or the input / output port 111 may transmit military management data to external devices.

On the other hand, when the second CPU 106 wishes to record data in the register group 103, the second CPU 106 generates data and addresses to be recorded and provides them to the rob 108 and the second address decoder 107, respectively. Done.

As described above, the second address decoding unit 107 combines the input addresses into a write signal to the second register 103b of the register group 103. In addition, the ROM 108, the data RAM 110, and the second buffer unit 109 are enabled.

The ROM 108 is chip-selected by the second address decoding unit 107 to generate an address corresponding to data input from the second CPU 106 to designate a corresponding address of the data RAM 110. .

Accordingly, the data RAM 110 generates data in the corresponding address by the address input from the ROM 108 and provides the data to the second buffer unit 109.

The second buffer unit 109 buffers the input data by the second address decoding unit 107 and stores the data in the second register 103b of the register group 103 that is write enabled.

Meanwhile, the first CPU 100 for reading data stored in the register group 103 enables the first buffer unit 102 through the first address decoding unit 101 and register group. The second register 103b of 103 is read enabled.

Accordingly, the data recorded in the second register 103b is buffered through the data bus 104 and through the first buffer unit 102 and provided to the first CPU 100.

In this way, the register group 103 allows the first central processing unit 100 and the second central processing unit 106 to transmit and receive information without sharing the data bus 104 and the address bus 105.

However, such a conventional data transmitting and receiving apparatus is required for data creation because a program ROM (PROM), that is, data of an address decoding unit is essential to selectively select a file stored in a register group. There is considerable difficulty, and since one bit of registers can make 4-bit data, two registers must be connected in parallel in order to send and receive 1 byte data. In order to transmit and receive data in the area, the number of registers must be increased and the program ROM needs to be replaced, resulting in an increase in scalability and corresponding power consumption.

Accordingly, an object of the present invention is to solve the above-mentioned problems, by using different address buses and data buses in transmitting and receiving data between a central processing unit for group management of an elevator and a central processing unit in charge of boarding process. The present invention provides a data transmitting / receiving device which reduces the number of parts and minimizes power consumption by sharing one memory area.

It is still another object of the present invention to secure more data input / output areas using dual port RAM and to improve data processing speed by completely separating data bus and address bus during transmission and reception.

The data transmitting and receiving apparatus for achieving the object of the present invention comprises first and second decoding means for decoding the address provided from the first and second central processing unit, respectively, and outputting the chip selection signal; The memory area is selected by the chip selection signal obtained by the first and second decoding means, and data is stored in the corresponding address according to the address and read / write signal, the address selection signal and the clock provided from the first and second CPUs. It is achieved by the dual port RAM to store the data in synchronization with the selected first and second central processing unit, the storage device in synchronization with the present invention in detail as follows. .

2 is a block diagram of the data transmitting and receiving apparatus of the present invention. As shown in FIG. 2, an address, data, a first address selection signal ASa and a first read / write signal R / And a first central processing unit (200) for generating a first clock (Ea); The first chip selection signal is received by decoding the address transmitted from the first CPU 200 through an independent first address bus 205 and decoded. A first decoding unit 202 outputting the data; Address, data, and second read / write signal (R /) to transmit and receive information to and from the first central processing unit 200 to perform boarding process. A second central processing unit 201 for generating a second address selection signal ASb and a second clock Eb; The second chip selection signal is received by decoding the address generated by the second CPU 201 through an independent second address bus 206. A second decoding unit 203 for outputting the data; First chip select signal obtained by the first and second decoding units 202 and 203 Or second chip selection signal Selects a corresponding memory area by using the first CPU 200 and an address provided from the first CPU 200 or the second CPU 201 and the first and second read / write signals R /. ) (R / ), The first and second address selection signals ASa (ASb) and the first and second clocks Ea and Eb according to the data of the first and second CPUs 200 and 201. Dual stores the synchronously stored in the address and selects and stores the stored data to the corresponding first and second CPUs 200 and 201 through independent first and second data buses 207 and 208, respectively. It consists of the fortram 204.

If described in detail with reference to Figure 2 the effect of the present invention configured as described above.

First, the first central processing unit 200 for military management of an elevator and the second central processing unit 201 for calling a boarding process are the corresponding first and second memory areas A of the dual port RAM 204 ( In order to respectively record data in B), the addresses required for recording are respectively provided to the first and second decoding units 202 and 203 through independent first and second address buses 205 and 206, respectively. The corresponding addresses of the first memory area A and the second memory area B of the port RAM 204 are designated, and data is dual-ported through independent first and second data buses 207 and 208, respectively. The first memory area A and the second memory area B of the RAM 204, and ) ( ), First and second address selection signals ASa (ASb) and first and second clocks Ea and Eb are provided to the dual port RAM 204.

The first decoding unit 202 decodes an address input from the first central processing unit 200 through the first address bus 205 to perform a first chip selection signal. As described above, the dual port RAM 204 is provided, and the second decoding unit 203 decodes an address input from the second CPU 201 through the second address bus 206 to process the second chip selection signal. To the dual pod RAM 204.

The dual port RAM 204 may include first and second chip selection signals input from the first and second decoding units 202 and 203, respectively. Selects the corresponding first and second memory areas A and B and the first and second write signals ) ( ) And the first and second data buses 207 and 208 that are independent from the first and second CPUs 200 and 201 according to the first and second address selection signals ASa and ASb. The data inputted through the first and second clocks Ea and Eb are stored in the corresponding address of the first and second memory areas A and B in synchronization with each other.

In addition, the first and second address processing units 200 and 201 are dual port RAMs through independent first and second address buses 205 and 206, and first and second data buses 207 and 208, respectively. In order to read data from 204, as described above, the first and second decoding units 202 (the first and second decoding buses 205 and 206 respectively transmit the addresses required for reading, respectively). 203 and the corresponding addresses of the first memory area A and the second memory area B of the dual port RAM 204, and the first and second read signals R and R, respectively. And the first and second address selection signals ASa (ASb) and the first and second clocks Ea and Eb to the dual port RAM 204.

The first decoding unit 202 decodes an address input from the first central processing unit 200 through the first address bus 205 to perform a first chip selection signal. The dual port RAM 204 is provided, and the second decoding unit 203 decodes an address input from the second CPU 201 through the second address bus 206 to select the second chip. signal The dual port RAM 204 is provided.

The dual port RAM 204 may include first and second chip selection signals input from the first and second decoding units 202 and 203, respectively. By selecting the first and second memory areas A and B, the first and second read signals R and R and the first and second address selection signals ASa and ASb are selected. The first and second data buses 207 (independent of the data stored in the corresponding addresses of the first and second memory areas A and B) are synchronized with the first and second clocks Ea and Eb, respectively. 208 through the first and second central processing unit (200) (201).

In this case, the dual port RAM 204 collides by controlling a semaphore internally so that correct data transmission and reception may occur even when the first and second CPUs 200 and 201 simultaneously access the same memory. It can safely send and receive data between two processors by eliminating the risk.

As described in detail above, according to the present invention, unlike the conventional technology which requires several devices in order to avoid the sharing of the address and data buses, which are essentially encountered when transmitting and receiving between two processors, different address buses and data buses are used. By sharing one memory area, the number of parts can be significantly reduced, and more data I / O area can be secured by using dual port RAM.

In addition, unlike the conventional technology which required a large number of peripheral devices to avoid sharing the address bus and data bus, the use of one dual port RAM improves data processing speed due to complete bus separation, and reduces the cost and power of the product. It has the effect of reducing consumption.

Claims (3)

First and second decoding means for decoding an address provided from the first and second CPUs and outputting the chip selection signal; The memory area is selected by the chip selection signals obtained by the first and second decoding means, and the corresponding addresses are provided according to the addresses, read / write signals, address selection signals, and clocks provided from the first and second CPUs, respectively. And a dual port RAM for synchronizing and storing the data within the selected data and providing the stored data to the first and second CPUs. The data transmitting / receiving apparatus according to claim 1, wherein the first central processing unit and the second central processing unit have independent address buses and data buses, respectively, to simultaneously access the dual port RAM. The data transmitting / receiving device according to claim 1 or 2, wherein the dual port RAM comprises a semaphore to eliminate data collisions when accessing the same memory simultaneously.