JPS60229156A - Common memory device - Google Patents

Abstract

PURPOSE:To prevent a common memory device from the competition of memory requests and to reduce the load of a data processor by incorporating a clock generating circuit for generating clocks having different phases in the memory device and providing a memory control device circuit with plural registers and FFs. CONSTITUTION:The clock generating circuit 6 for generating plural clock signal strings having different phases is incorporated in the common memory device and the memory device control circuit 4 is provided with the registers 7, 7', 10, 10' and the FFs 8, 8' for storing receiving signals inputted synchronously with clocks with different phases. In said constitution, receiving signals and request signals from respective data processors are stored in the corresponding registers and FFs, and until the return of an accept signal from a memory device 5, timing start signals are sent to the device 5 respectively synchronously with the clocks with different phases. When the device 5 is inhibited from writing or reading data because of refresh operation or the like, data can be written or read on/from the device 5 on the basis of the contents stored in the registers at the timing of the succeeding clock, so that device 5 can be prevented from the competition of memory requests.

Description

TECHNICAL FIELD The present invention relates to a shared memory device commonly used by a plurality of data processing devices.

BACKGROUND ART Conventionally, as shown in FIG. 1, this type of shared memory device has a built-in memory device control circuit 4 and a memory device 5, and between the memory device control circuit 4 and a plurality of data processing devices 1.2,
Reception signals 11 and 2+, transmission signals 12 and 22, etc. are exchanged.

When the memory device control circuit 4 receives a reception signal 11 or 21 (including a request signal, an address signal, a read/write designation signal, write data, etc.) from the data processing device 1 or 2, the memory device control circuit 4 transmits 7 x bits by a transmission signal 12 or 22. The signal is sent back, and a memory request signal, address signal, write data, etc. are sent to the memory device 5.
The memory device 5 writes the write data to the address specified by the address signal, or reads data from the specified address. The read data 32 is sent to the memory device control circuit 4, and the memory device control circuit 4 sends the transmission signal 12 to the data processing device Ml or 2 that issued the request.
Or the read data is transmitted as 22. However, when the memory device M5 cannot perform a read/write operation because it is in the middle of a read/write operation or a refresh operation due to a request from another data processing device, the memory device control circuit 4 outputs the accept signal. Don't send it back.

Therefore, the data processing device Ml or 2 that issued the request must issue the same request again and transmit the same request signal, address signal, and read/write designation signal to the memory control circuit 4.

In the conventional device described above, the request signal, address signal, read/write designation signal, etc. from the data processing devices 1 and 2 are input asynchronously, so a device is devised to avoid interference of these signals in the shared memory device 3. Furthermore, when a request from the data processing device IT, etc. cannot be met, the data processing device 1, etc. generates the same request signal, address signal, and read/write designation signal request over and over again. Therefore, the control of the data processing device 1.2 becomes complicated, which increases the burden on the data processing device 1.2. Furthermore, there are many drawbacks, such as the fact that collisions of these signals may occur accidentally and cause accidental failures.

OBJECTS OF THE INVENTION It is an object of the present invention to solve the above-mentioned conventional drawbacks, prevent conflicting request signals from a plurality of data processing devices,
In addition, memory requests that could not be executed due to memory device refresh operations, etc. can be managed within the shared memory device and re-executed, thereby reducing the burden on the data processing device side. Our goal is to provide the following.

Composition of the Invention The shared memory device of the present invention includes a clock generation circuit that generates a plurality of clock signal trains with one phase difference, and a reception circuit that includes a memory address signal, write data, write/read designation signal, etc. input from a data processing device. a first register that stores and holds a signal in response to a request signal input from the data processing device; a flip-flop that is set by the request signal and reset by an accept signal from the memory device described later; and the first register. a memory device that reads data from or writes write data from an address specified by an address signal output from the flip-flop; and a memory device that is opened when the output of the flip-flop is at a high level and timings the clock signal output from the clock generation circuit. The present invention is characterized in that it includes an AND gate that outputs an activation signal to the memory device, and a second register that holds and outputs read data read from the memory device.

Embodiments of the Invention Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention.

That is, it is comprised of a clock generation circuit 6 that generates a plurality of clock signals having mutually different phases, a memory device 5, and a memory device control circuit 4. The memory device control circuit 4 operates based on a plurality of clock signal trains generated by the clock generation circuit 6. The memory device control circuit 4 includes:
A first register 7 receives the received signal 11 input from the data processing device l in synchronization with the clock signal 13, and is set by the request signal R. The flip-flop 8 is reset by an accept signal from the memory device 5.
, a second register 10 that stores read data 32 from the memory device 5 and sends the transmission signal 12 to the data processing device 1; signal 13
is passed through the memory device M as a timing activation signal 15.
5, a pass gate 17 which is periodically opened and closed by the clock signal 13 output from the clock generation circuit 6, a first register 7' similar to the above for the data processing device 2, and a flip-flop gate 8'. 2 register lO', AND gate 16', pass go)
17' etc.

Next, the operation of this embodiment will be explained with reference to FIGS. 3 and 4. FIG. 3 is a time chart showing signals of various parts during normal operation of this embodiment, and FIG. 4 explains the operation when the memory device 5 is in the refresh operation and cannot perform read/write operations. This is a time chart for

In normal times, the memory device control circuit 4 receives request signals, address signals, write data, and read/write designation signals from the data processing device 1, which are input in synchronization with one clock signal 13 generated by the clock generation circuit 6. etc., and a request signal from the data processing device 2 that is input in synchronization with the other clock signal 23,
Receives and holds address signals and read/write designation signals. FIG. 3(A) shows the clock generated by the clock generation circuit 6. One clock signal 13 is shown, and FIG. The phases are shifted by a period T. A received signal 11 (write data) from the data processing device 1 as shown in FIG.

(address signal, read/write designation signal, etc.) are input to the first register 7, and stored in the first register 7 in response to a request signal R (FIG. 4(C)) input from the data processing device 1. On the other hand, the flip-flop 8 is set by the request signal R, and the output 14 of the flip-flop 8 becomes high level. Flip-flop 8 is
It is reset when the accept signal A is returned from the memory device 5. That is, the output signal 1 of flip-flop 8
A high level of 4 indicates that a memory request is in progress.

The AND gate 16 is opened by the signal 14, and the clock signal 13 output from the clock generation circuit 6 is applied to the AND gate 1.
6 as a timing activation signal 15 ((E) in the figure), and sent to the memory device 5. When the memory device 5 receives the timing activation signal 15, the memory device 5 receives the signal (F) sent from the first register 7 via the pass gate 17.
A booter writes data to the address specified by a signal (write data, address, read/write designation signal) as shown in (1) or reads data from the specified address, and returns an accept signal A. This accept signal A
The flip-flop 8 is reset by this. Since the output I4 of the flip-flop 8 is sent to the data processing device 1 as the busy signal B, the busy signal B becomes low level by resetting the flip-flop 8, and the data processing device M1 sends out the signal 11 at the next timing. However, data is written to or read from the memory device 5 in the same manner as described above. In the case of reading, the read data 32 as shown in FIG.
The transmission signal 12 is sent to the data processing device l at the timing shown in H).

Received signals 21 such as address signals and read/write designation signals inputted from the data processing HM2 ((J) in the same figure are stored in the register 7' of Ml by the request signal H shown in (K) in the same figure. , as described above, the output signal 24 of the flip-flop 8' becomes high level as shown in FIG. It is supplied to the device 5. The memory device 5 includes a first register 7'
The write data is written to the address specified by the signal 31 supplied through the pass-through 17', or the data is read from the specified address.

The read data 32 is shown in (0) of the same figure, and (P) of the same figure shows the transmission signal 22 sent from the memory device control circuit 4 to the data processing device 2. Data writing timing and data processing device 2
Since the timing of writing data from M5 is always shifted by T, there is no conflict between the two write data on memory 1 and M5. The same applies to read data.

Next, a case where the memory device 5 cannot respond to a memory request because it is being refreshed will be described. Figure 4 (A)
As shown in FIG. 2, a reception signal 11 and a request signal R are inputted from the data processing device 1 in synchronization with the lock signal 13 ((B) in the same figure).

(C)). This causes the first register 7 to receive the received signal +1.
is stored, the flip-flop 8 is set, and the signal 14 becomes high level ((D) in the same figure).

The high level of the signal 14 opens the AND gate 1B, and the timing activation signal 15 is output from the AND gate 1B ((E) in the figure). However, since the memory device 5 is being refreshed, the accept signal A is not returned from the memory device M5, and the flip-flop 8 remains set. That is, the signal 14 remains at high level ((D) in the same figure). Therefore, since the busy signal B has been output to the data processing device 1, the data processing device 1 does not send out the next signal 11 and the request signal R. and,
When the next clock signal 13 passes through the anti-game) 1B and is output as the timing start signal 15, the memory device M
5, the address stator etc. held in the first register 7 writes write data to the address specified by the signal 31 outputted through the pass gate 17, or reads data from the specified address and outputs the accept signal A.
is returned to reset the flip-flop 8. (G) in the same figure shows the read data 32. When the flip-flop 8 is reset by the accept signal A, the signal 14 becomes low level, and the data processing device 1 transmits the next signal 11 at the next timing.
Writing or reading by is the same as described above.

Therefore, the data processing device 1 can store necessary data in the memory device 5 or read data each time without sending a request signal, an address signal, a read/write designation signal, etc. again. The same applies to memory requests from the data processing device 2. As described above, the memory requests from the data processing devices Ml and 2 do not compete on the memory device 5, and the data processing devices 1 and 2 read data from the memory device 5 without waiting for each IT. Or a write operation can be performed.

Effects of the Invention As described above, the present invention includes a built-in clock generation circuit that generates a plurality of clock signal trains of different phases,
The memory device control circuit is equipped with a plurality of registers and flip-flops that store and hold received signals that are input in synchronization with the clocks of different phases, respectively, and can handle each of the received signals and request signals from multiple data processing devices. The timing activation signal is held in the register and flip-flop, and is configured to send a timing activation signal to the memory device in synchronization with the clocks of different phases until an accept signal is returned from the memory device. Therefore, when data cannot be written to or read from the memory device due to a refresh operation or the like, writing to or reading from the memory device can be performed according to the contents held in the register at the timing of the next clock signal. can. Therefore, there is no conflict between memory requests from multiple data processing devices, and even if a memory request is not executed due to refresh, etc., the same request signal, 7 address signal, read/write designation signal, etc. from the data processing device side, etc. This eliminates the need to send out the data again, thereby reducing the burden on the data processing device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional shared memory device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing an example of signals of each part of the above embodiment.
FIG. 4 is a time chart showing signals of various parts in the above embodiment when a memory request occurs during refresh.

Claims (1)

[Claims] A clock generation circuit that generates a plurality of clock signal trains having different phases, and a reception signal that is input from the data processing device and includes a memory address signal, write data, a write/read designation signal, etc. that is input from the data processing device. a first register that stores and holds data in response to a request signal;
a flip-flop that is set by the request signal and reset by an accept signal from the memory device described later; and a memory device that reads data from or writes write data from an address specified by an address signal output from the first register. , an AND gate that is opened when the output of the flip-flop is at a high level and outputs the clock signal output from the clock generation circuit to the memory device as a timing activation signal, and holds read data read from the memory device. A shared memory device comprising: a second register for outputting.