JPWO2017077728A1 - パワーモジュールの製造方法 - Google Patents
パワーモジュールの製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 106
- 230000002093 peripheral effect Effects 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims description 80
- 229910052751 metal Inorganic materials 0.000 claims description 80
- 239000002923 metal particle Substances 0.000 claims description 45
- 238000005304 joining Methods 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 32
- 238000010438 heat treatment Methods 0.000 claims description 28
- 238000000576 coating method Methods 0.000 claims description 24
- 238000003825 pressing Methods 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 7
- 239000002245 particle Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010419 fine particle Substances 0.000 description 50
- 230000008569 process Effects 0.000 description 17
- 239000000463 material Substances 0.000 description 8
- 230000008646 thermal stress Effects 0.000 description 6
- 239000003566 sealing material Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000010304 firing Methods 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 238000002076 thermal analysis method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 238000007561 laser diffraction method Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000000638 solvent extraction Methods 0.000 description 1
- 238000009864 tensile test Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
Description
例えば、特許文献1(特開平9−129680号公報)には、接合部中央に十字状に溝を形成し、接合部を4分割することが開示されている。
以下、第1の実施形態について、図を参照して説明する。なお、各図中同一または相当部分には同一符号を付している。また、以下に記載する実施の形態の少なくとも一部を任意に組み合わせてもよい。
以下に、第1の実施形態に係るパワーモジュールの構造について説明する。図1は、第1の実施形態のパワーモジュールの断面図である。図1に示すとおり、第1の実施形態に係るパワーモジュールは、主として、パワー半導体素子1、絶縁基板2、第1の配線部材3、導電性接合部材4、第2の配線部材5、ベース板6、接合材料7、ケース8及び封止材料9を備える。
導電性接合部材4は、金属微粒子ペースト403(図2参照)を用いて形成された金属の焼結体である。導電性接合部材4を構成する金属としては、好ましくはAg及びCuである。
以下に、パワー半導体素子と絶縁基板の接合工程について説明する。
次に、第1の実施形態に係るパワーモジュールの効果について説明する。
以下、図を参照して第2の実施形態について説明する。ここでは、第1の実施形態と異なる点について主に説明する。
以下、図を参照して第3の実施形態について説明する。ここでは、第1の実施形態と異なる点について主に説明する。
以下、図を参照して第4の実施形態について説明する。ここでは、第1の実施形態と異なる点について主に説明する。
以下、図を参照して第5の実施形態について説明する。ここでは、第1の実施形態と異なる点について主に説明する。
以下、図を参照して第6の実施形態について説明する。ここでは、第1の実施形態と異なる点について主に説明する。
以下、図を参照して第7の実施形態について説明する。ここでは、第1の実施形態と異なる点について主に説明する。
本発明に係るパワーモジュールの一の製造方法では、絶縁基板上の導電性部材の接合領域に金属粒子ペーストを塗布する塗布工程がなされる。第1の主面及び第1の主面の反対側の第2の主面を有するパワー半導体素子を、第2の主面が塗布された金属粒子ペーストに接触するようにマウントするマウント工程がなされる。パワー半導体素子をその厚み方向に加圧しながら加熱することでパワー半導体素子と絶縁基板上の導電性部材を接合する加熱工程がなされる。加熱工程において、パワー半導体素子と絶縁基板上の導電性部材との接合領域の中央領域に形成される導電性接合部材は、接合領域の周辺領域に形成される導電性部材よりも密度が高い。塗布工程は、接合領域の中央領域における金属粒子ペーストの塗布量は、接合領域の周縁領域における金属粒子ペーストの塗布量よりも多い。
本発明に係るパワーモジュールの他の製造方法では、絶縁基板上の導電性部材の接合領域に金属粒子ペーストを塗布する塗布工程がなされる。第1の主面及び第1の主面の反対側の第2の主面を有するパワー半導体素子を、第2の主面が塗布された金属粒子ペーストに接触するようにマウントするマウント工程がなされる。パワー半導体素子をその厚み方向に加圧しながら加熱することでパワー半導体素子と絶縁基板上の導電性部材を接合する加熱工程がなされる。加熱工程において、パワー半導体素子と絶縁基板上の導電性部材との接合領域の中央領域に形成される導電性接合部材は、接合領域の周辺領域に形成される導電性部材よりも密度が高い。塗布工程は、接合領域の中央領域において塗布される金属粒子ペーストの厚みが、接合領域の周縁領域において塗布される金属粒子ペーストの厚みよりも大きい。
本発明に係るパワーモジュールのさらに他の製造方法では、絶縁基板上の導電性部材の接合領域に金属粒子ペーストを塗布する塗布工程がなされる。第1の主面及び第1の主面の反対側の第2の主面を有するパワー半導体素子を、第2の主面が塗布された金属粒子ペーストに接触するようにマウントするマウント工程がなされる。パワー半導体素子をその厚み方向に加圧しながら加熱することでパワー半導体素子と絶縁基板上の導電性部材を接合する加熱工程がなされる。加熱工程において、パワー半導体素子と絶縁基板上の導電性部材との接合領域の中央領域に形成される導電性接合部材は、接合領域の周辺領域に形成される導電性部材よりも密度が高い。塗布工程は、金属粒子ペーストを接合領域の中央領域において一様に塗布し、接合領域の周縁領域においてパターニングして塗布する。
Claims (12)
- 第1の主面と第1の主面の反対側の第2の主面を有するパワー半導体素子と、
前記第2の主面に面し、導電性部材を有する絶縁基板と、
前記第2の主面と前記導電性部材の間に形成された導電性接合部材を備え、
前記導電性接合部材は周縁領域及び中央領域を有しており、
前記導電性接合部材の前記周縁領域における強度は、前記導電性接合部材の前記中央領域における強度よりも低い、パワーモジュール。 - 第1の主面と第1の主面の反対側の第2の主面を有するパワー半導体素子と、
前記第2の主面に面し、導電性部材を有する絶縁基板と、
前記第2の主面と前記導電性部材の間に形成された導電性接合部材を備え、
前記導電性接合部材は周縁領域及び中央領域を有しており、
前記導電性接合部材は金属焼結体であり、
前記導電性接合部材の前記周縁領域における密度は、前記導電性接合部材の前記中央領域における密度よりも低い、パワーモジュール。 - 前記導電性部材の前記中央領域において凸部を含んでいる、請求項1又は2記載のパワーモジュール。
- 前記導電性接合部材は、前記中央領域において板状部材を含んでおり、前記板状部材は前記中央領域に埋没している、請求項1又は2記載のパワーモジュール。
- 前記導電性接合部材は矩形形状を有しており、前記矩形形状の対角の長さYと前記周縁領域の長さXはX≦Y/6を満たす、請求項1又は2記載のパワーモジュール。
- 絶縁基板上の導電性部材の接合領域に金属粒子ペーストを塗布する塗布工程と、
第1の主面及び第1の主面の反対側の第2の主面を有するパワー半導体素子を、前記第2の主面が前記塗布された金属粒子ペーストに接触するようにマウントするマウント工程と、
前記パワー半導体素子を前記パワー半導体素子の厚み方向に加圧しながら加熱することで前記パワー半導体素子と前記絶縁基板上の導電性部材を接合する加熱工程とを備え、
前記加熱工程において、前記パワー半導体素子と前記絶縁基板上の導電性部材との接合領域の中央領域に形成される導電性接合部材は、前記接合領域の周辺領域に形成される前記導電性部材よりも密度が高い、パワーモジュールの製造方法。 - 前記加熱工程において、前記パワー半導体素子の中央領域に付加される加圧力は、前記パワー半導体素子の周辺領域に付加される加圧力よりも大きい、請求項6記載のパワーモジュールの製造方法。
- 前記加熱工程において、前記パワー半導体素子の中央領域のみが加圧される、請求項7記載のパワーモジュールの製造方法。
- 前記塗布工程は、前記接合領域の中央領域における前記金属粒子ペーストの塗布量は、前記接合領域の周縁領域における前記金属粒子ペーストの塗布量よりも多い、請求項6又は7記載のパワーモジュールの製造方法。
- 前記塗布工程は、前記接合領域の中央領域において塗布される前記金属粒子ペーストの厚みが、前記接合領域の周縁領域において塗布される前記金属粒子ペーストの厚みよりも大きい、請求項6又は7記載のパワーモジュールの製造方法。
- 前記塗布工程は、前記金属粒子ペーストを前記接合領域の中央領域において一様に塗布し、前記接合領域の周縁領域においてパターニングして塗布する、請求項6又は7記載のパワーモジュールの製造方法。
- 前記塗布工程は、第1の金属粒子ペーストを前記接合領域の中央領域に塗布し、第2の金属粒子ペーストを前記接合領域の周縁領域に塗布し、
前記第2の金属粒子ペースト中の金属粒子の平均粒径は、前記第1の金属粒子ペースト中の金属粒子の粒径の10倍以上である、請求項6又は7記載のパワーモジュールの製造方法。
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