JPWO2009147804A1 - Probe device manufacturing method - Google Patents

Abstract

In manufacturing a probe apparatus that forms an electrical connection to a device under test, adjustment according to the specifications of the device under test is made possible in a short time. The probe device manufacturing method includes a via hole forming step for forming a via hole (330) penetrating the test substrate (301) on the front and back sides, and a surface side connection pad (320) connected to the surface side end of the via hole. A surface-side connection pad forming step formed on the surface of the test substrate, and a droplet-shaped conductive material is ejected and adhered to the back surface of the test substrate, thereby forming the back-side connection pad (350) and the via hole. A back side conductor pattern forming step of forming a back side wiring (340) for electrically connecting the back side end and the back side connection pad.

Description

The present invention relates to a probe device manufacturing method. More particularly, the present invention relates to a probe apparatus manufacturing method for manufacturing a probe apparatus that is used by being exchanged when forming an electrical connection to a device under test having different specifications in a test apparatus. In addition, this application is related to the following international application and claims priority from the following international application. For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.
PCT / JP2008 / 060170 Filing date June 2, 2008

  In a wafer test in which a device under test is tested in a die or wafer state, a part called a probe card or the like is used for the purpose of forming an electrical connection to a fine connection pad on the wafer. Probe cards are individually manufactured according to the arrangement of connection pads of devices under test having different specifications. Thereby, a probe card can be replaced | exchanged and the utilization efficiency of an expensive test apparatus can be improved.

  Patent Document 1 below describes a probe wafer used as a probe card. The probe wafer is manufactured by processing a wafer which is itself a semiconductor substrate, and electrical connections can be made to a large number of semiconductor devices formed on a single wafer.

JP-A-11-274252

  However, the probe wafer is individually manufactured for each specification of the device under test. Further, in the case of a wafer test, the number of connection pads that form electrical connections reaches a large number, and the arrangement of the connection pads becomes fine. For this reason, it takes time to manufacture the probe wafer, and the probe wafer itself becomes an expensive part.

  In order to solve the above-mentioned problem, as a first aspect of the present invention, there is provided a probe apparatus manufacturing method for manufacturing a probe apparatus that forms an electrical connection to a device under test. And a via hole forming step for forming a via hole penetrating between the back surfaces, and a surface side connection pad forming step for forming a surface side connection pad connected to an end portion on the surface side of the via hole on the surface of the test substrate; By discharging and adhering a droplet-shaped conductive material toward the back surface of the test substrate, the back surface side connection pad and the back surface side wiring for electrically connecting the back surface side end portion of the via hole and the back surface side connection pad And a backside conductor pattern forming step of forming a probe device.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

1 is a diagram schematically showing components of a test apparatus 100. FIG. 1 is a diagram schematically showing the structure of a test apparatus 100. FIG. 2 is a perspective view showing the shape of a device under test 200. FIG. 2 is a perspective view showing a shape of a probe wafer 300. FIG. 5 is a cross-sectional view showing a manufacturing process of the probe wafer 300. It is a figure which shows typically the structure of the drawing apparatus 400 which forms the wiring 340. FIG. It is a cross-sectional head which shows the structure and manufacturing method of the probe wafer 300 which concern on another form. It is a section head showing the structure and manufacturing method of probe wafer 300 concerning still another form.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a diagram schematically showing the components of the test apparatus 100 separated. The test apparatus 100 is formed by sequentially stacking a test head 110, a performance board 120, and a prober 130. Further, the test apparatus 100 may be further used by connecting to a main frame (not shown).

  The test head 110 includes a chuck 111, pin electronics 114, and a motherboard 119 housed in a housing 112. The chuck 111 slightly protrudes from the upper surface of the housing 112 and holds a wafer or the like that is the device under test 200 when a test is executed.

  The pin electronics 114 is disposed on the upper portion of the housing 112 and supports a connector 118 having one end exposed on the upper surface of the housing 112. In addition, the pin electronics 114 electrically connects the connector 118 to the motherboard 119 via the cable 113 and the connector 116. A circuit for comprehensively controlling the operation of the test apparatus 100 is mounted on the motherboard 119, and a storage unit for accumulating evaluation results is also mounted.

  The performance board 120 includes a pin electronics 124 and a chuck 121 housed in a housing 122. The pin electronics 124 has a plurality of connectors 126 on the top surface. The pin electronics 124 is connected to a connector 128 exposed on the lower surface of the housing 122 via the cable 123. Further, an internal circuit 129 is mounted on the pin electronics 124.

  The chuck 121 is fixed with a slight offset upward from the lower surface of the housing 122. When a test is executed in the test apparatus 100, the probe wafer 300 is held on the chuck 121 of the performance board 120.

  The prober 130 has a housing 132 that houses a plurality of pin electronics 134. The pin electronics 134 includes a connector 136 at each lower end.

  As described above, the prober 130, the performance board 120, the test head 110, and the probe wafer 300 are provided as parts that can be separated from each other. With such a structure, a wide range of tests can be executed by arbitrarily combining the probe wafer 300, the performance board 120 and the pin electronics 134 according to the type of the device under test 200, the content of the test to be performed, and the like.

  Further, the test of the device under test 200 having different specifications such as the arrangement of the connection pads can be handled by exchanging some parts such as the probe wafer 300. Therefore, the operating rate of the test apparatus 100 can be improved and the cost related to the test can be reduced.

  FIG. 2 is a diagram schematically showing the structure of the test apparatus 100 assembled when the test is executed. Components that are the same as those in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted.

  In the assembled test apparatus 100, a prober 130 is attached to the performance board 120. At this time, since the connectors 136 and 126 are coupled to each other, the connector 128 of the performance board 120 is coupled to the chuck 121 via the prober 130.

  A probe wafer 300 is held on the lower surface of the chuck 121. As a result, the probe wafer 300 is electrically connected to the chuck 121.

  The assembly in which the prober 130, the performance board 120, and the probe wafer 300 are integrated is mounted on the casing 112 of the test head 110 from above. At this time, a wafer or the like which is the device under test 200 is mounted on the chuck 111. As a result, the device under test 200 is coupled to the probe wafer 300 and the connector 118 is coupled to the connector 128. Therefore, a signal path is formed from the mother board 119 of the test head 110 to the device under test 200 via the performance board 120, the prober 130 and the probe wafer 300.

  When the test of the device under test 200 in the test apparatus 100 is executed, when the test for one device under test 200 is completed, the assembly in which the performance board 120 and the probe wafer 300 are integrated is lifted, and the next device under test is tested. Device 200 is inserted. By repeating this, tests for a plurality of devices under test 200 can be sequentially executed.

  Further, when the specification of the device under test is changed, if the changed specification is, for example, the arrangement of the connection pads of the device under test 200, the test is performed by changing the probe wafer 300 to a corresponding one. Can continue. In addition, when the test contents are changed, any of the pin electronics 134 can be changed and dealt with.

  FIG. 3 is a perspective view schematically illustrating the shape of the device under test 200. A device under test 200, which is a semiconductor wafer, has a plurality of dies 210, each of which forms a circuit, an element, etc., formed in a matrix on the surface. Each die 210 has a plurality of connection pads 220 that are used when making electrical connections to the outside. In practice, however, the number and density of dies 210 are very high and the number and density of connection pads 220 are even higher.

  FIG. 4 is a perspective view showing the shape of the probe wafer 300. FIG. 4A shows the upper surface of the probe wafer 300, that is, the surface held in contact with the chuck 121 of the performance board 120.

  On the upper surface, the probe wafer 300 has a plurality of connection pads 320 arranged according to the arrangement of connection terminals on the chuck 121. Thereby, when the probe wafer 300 is attracted and held by the chuck 121, the chuck 121 and the probe wafer 300 are electrically connected. Note that a boundary 310 indicated by a dotted line in the drawing indicates the arrangement of the dies 210 in the device under test 200.

  FIG. 4B schematically shows the shape of the lower surface of the probe wafer 300, that is, the surface in contact with the upper surface of the device under test 200 when the test apparatus 100 executes a test. On the lower surface of the probe wafer 300, connection pads 350 on the probe wafer 300 side are formed at locations corresponding to the connection pads 220 of the device under test 200.

  Further, a lower end of a via hole 330 formed through the probe wafer 300 in the thickness direction appears in a region where the connection pad 320 of the probe wafer 300 itself is formed on the surface. Furthermore, the via hole 330 and the connection pad 350 are electrically coupled by the wiring 340. With such a structure, the connection pad 320 on the upper surface of the probe wafer 300 is coupled to the connection pad 350 on the lower surface via the via hole 330 and the wiring 340.

  FIG. 5 is a cross-sectional view showing a manufacturing process of the probe wafer 300. First, as shown in FIG. 5A, as a step of forming the via hole 330, a through hole penetrating the front and back of the semiconductor substrate 301 is formed in the semiconductor substrate 301 such as a silicon wafer, and then a conductive material is applied to the through hole. The via hole 330 is formed by filling. In this embodiment, the via hole 330 is formed on the boundary 310 of the die 210.

  Next, as shown in FIG. 5B, as a step of forming the connection pad 320 on the front surface side, the connection pad 320 is formed at the upper end of the via hole 330 on the upper surface of the semiconductor substrate 301. As a result, connection pads 320 that form electrical coupling to the chuck 121 are formed on the upper surface of the semiconductor substrate 301.

  The via hole formation step and the surface side connection pad formation step so far may include a mask process using a mask having a given light shielding pattern. That is, in the test apparatus 100 including the chuck 121 having a specific specification, the specification and arrangement of the connection pad 320 with respect to the chuck 121 are constant. Therefore, a fixed intermediate product can be mass-produced in advance using a mask that can be used repeatedly. Furthermore, when manufacturing a probe wafer 300 with another specification, as will be described later, the probe wafer 300 according to the specification for each model can be prepared in a short period of time by forming a conductor pattern on the lower surface of the semiconductor substrate 301.

  On the other hand, the arrangement of the wirings 340 and the connection pads 350 formed on the lower surface of the semiconductor substrate 301 may differ depending on the arrangement of the connection pads 220 in the device under test 200. Therefore, the step of forming the conductor pattern on the back surface side of the semiconductor substrate 301 described below is performed individually according to the specifications of the device under test 200.

  That is, when the specifications of the device under test 200 are known, the wiring 340 extending from the lower end of the via hole 330 is formed on the lower surface of the semiconductor substrate 301 as shown in FIG. Further, as shown in FIG. 5D, a connection pad 350 is formed at the tip of the wiring 340. Note that the order of the stage illustrated in FIG. 5C and the stage illustrated in FIG. 5D can be reversed.

  Through such a series of procedures, the back-side connection pad 350 disposed at a position corresponding to the connection pad 220 of the device under test 200, and the back-side end of the via hole 330 and the back-side connection pad 350 are electrically connected. And a wiring 340 on the back surface side connected to the. Therefore, the probe wafer 300 including the connection pad 320 for the chuck 121, the connection pad 350 for the device under test 200, the via hole 330 and the wiring 340 for connecting the connection pads 320 and 350 to each other is formed on the semiconductor substrate 301. .

  As described above, the wiring 340 and the connection pad 350 are individually formed according to the specifications of the device under test 200. For this reason, it is preferable to form using the drawing apparatus 400 which is demonstrated below.

  That is, FIG. 6 is a diagram schematically showing the structure of a line drawing device 400 that can be used when the wiring 340 and the connection pads 350 are formed. The line drawing device 400 includes a support device 430, a reference light source 440, an imaging device 450, and a line drawing unit 460 housed inside the housing 401, an image processing device 410 connected to the housing 401 from the outside via a cable 480, and And an image display device 420.

  The support device 430 includes an X stage 432, a Y stage 434, and a rotation stage 436. The X stage 432 is driven by a motor 438 and moves in a direction indicated by an arrow X in the drawing. The Y stage 434 moves horizontally in a direction orthogonal to the X stage 432 by a motor (not shown).

  Further, the rotary stage 436 rotates the X stage 432 and the Y stage 434 within a horizontal plane. By combining the operations of the X stage 432, the Y stage 434, and the rotary stage 436, the probe wafer 300 held by the substrate holding device 470 on the X stage 432 can be moved in an arbitrary direction. The probe wafer 300 is mounted with the surface on which the connection pads 320 on the front side are formed held by the substrate holding device 470 and the back side facing up.

  The reference light source 440 irradiates the reference light toward the probe wafer 300 mounted on the support device 430. The imaging device 450 images the reference light reflected by the probe wafer 300 to detect a specific position of the probe wafer 300, for example, an alignment mark, and to determine the amount of movement of the probe wafer 300 accompanying the operation of the support device 430. Measure precisely.

  The drawn part 460 includes an actuator 462 and an ejection head 464. The discharge head 464 discharges a liquid conductive material such as conductive ink downward. The ejection timing is instructed by an image processing apparatus 410 described later. The actuator 462 moves the ejection head 464 up and down and adjusts the distance between the probe wafer 300 mounted on the support device 430 and the ejection head 464.

  Accordingly, the liquid conductive material can be attached to the probe wafer 300 with high accuracy, and conductive patterns such as the wiring 340 and the connection pads 350 can be formed. Note that the ejection head 464 can eject a droplet-like insulating material instead of the conductive material to adhere to the probe wafer 300. Thereby, for example, an insulating layer covering the wiring 340 can be formed.

  The image display device 420 can display an image of the probe wafer 300 captured by the imaging device 450 via the image processing device 410. Thereby, the wiring 340 formed by the drawn line part 460, the connection pad 350, etc. can be monitored.

  Further, the position of the connection pad 220 of the device under test 200 can be measured by mounting the device under test 200 on the support device 430 and imaging the device under test 200 with the imaging device 450. The image processing apparatus 410 can arrange the connection pad 350 on the back surface of the probe wafer 300 in accordance with the information indicating the position of the connection pad 220 acquired in this way.

  In this way, a manufacturing method for manufacturing the probe wafer 300 for forming an electrical connection to the device under test 200, which includes a via hole forming step for forming a via hole 330 penetrating the semiconductor substrate 301 on the front and back sides in the semiconductor substrate 301; A surface-side connection pad forming step for forming a surface-side connection pad 320 connected to the surface-side end of the via hole 330 on the surface of the semiconductor substrate 301, and a droplet-shaped conductive material toward the back surface of the semiconductor substrate 301 By discharging and adhering, the back-side connection pad 350 disposed at a position corresponding to the connection pad 220 of the device under test 200 and the back-side end and back-side connection pad 350 of the via hole 330 are electrically connected. And a backside conductor pattern forming step for forming a backside wiring 340 connected to the probe wafer Production method is carried out.

  Note that the formation of the connection pad 320 on the front surface side may include a procedure of discharging and attaching a droplet-shaped conductive material toward the surface of the semiconductor substrate 301. Thereby, a surface conductor pattern can also be rapidly manufactured by arbitrary specifications.

  FIG. 7 is a cross-sectional view showing the structure and manufacturing method of a probe wafer 300 according to another embodiment. FIG. 7A shows the stage shown in FIG. 5B in the series of steps shown in FIG. 5, that is, the stage to be executed after the via hole 330 and the connection pad 320 on the surface side are formed. .

  As shown in FIG. 7A, at this stage, a groove 360 is formed on the back surface of the semiconductor substrate 301 prior to the formation of the wiring 340 and the connection pads 350 on the back surface side of the semiconductor substrate 301. The groove 360 is formed in a region where the wiring 340 is formed by laser processing or the like. Further, the depth of the groove 360 is smaller than or equal to the thickness of the wiring 340 formed in the next stage shown in FIG.

  A wiring 340 is formed on the back surface of the semiconductor substrate 301 in which the groove 360 is formed as shown in FIG. Thereby, the wiring 340 does not protrude from the back surface of the semiconductor substrate 301.

  Subsequently, as shown in FIG. 7C, a connection pad 350 on the back surface side is formed. The connection pad 350 has a thickness such that the top surface protrudes from the back surface of the semiconductor substrate 301. With such a structure, good contact with the connection pad 350 can be expected while maintaining the flatness of the back surface of the probe wafer 300.

  Thus, prior to the back surface side wiring formation step, a groove forming step of forming the groove 360 in the semiconductor substrate 301 may be further included in the region where the back surface side wiring 340 is formed. Accordingly, the thickness of the wiring 340 can be increased to reduce the electrical resistance, and the strength of the wiring 340 itself can be improved.

  FIG. 8 is a cross-sectional view showing the structure and manufacturing method of a probe wafer 300 according to still another embodiment. In this embodiment, the semiconductor substrate 301 on which the probe wafer 300 is formed has a device 380 previously formed on the surface. The device 380 is insulated from other devices, wirings, pads, and the like by an insulating layer 370 formed on the surface of the semiconductor substrate 301 around the device 380.

  When the probe wafer 300 is manufactured using such a semiconductor substrate 301, as shown in FIG. 8A, first, a region including the via hole 330 is formed, and a region wider than the region is made of a protective material. The formed protective layer 390 is formed. The protective layer 390 is formed through the insulating layer 370 in the thickness direction.

  As described above, the method for manufacturing the probe wafer 300 may include a protective layer forming step of forming the protective layer 390 that blocks between the region where the via hole 330 is formed and the insulating layer 370. Thus, the insulating layer 370 can be formed using a porous insulating material that easily infiltrates liquid. Therefore, the parasitic capacitance of the semiconductor substrate 301 can be reduced and the signal quality can be kept high.

  Subsequently, as shown in FIG. 8B, a through hole 332 is formed in a region where the protective layer 390 is formed. At this time, the protective layer 390 remains around the through hole 332. Thereby, the through hole 332 is surrounded by the protective layer 390. Therefore, the insulating layer 370 is not exposed on the inner surface of the through hole 332.

  The protective layer forming step may include a procedure of forming a protective layer 390 surrounding a region where the via hole 330 is formed. Furthermore, the method for manufacturing the probe wafer 300 may include a via hole forming step including a step of piercing the insulating layer 370 and the semiconductor substrate 301 by irradiating a region surrounded by the protective layer 390 with a laser. Thereby, the via hole 330 surrounded by the protective layer 390 can be reliably formed.

  Next, as shown in FIG. 8C, the via hole 330 is formed by filling the inside of the through hole 332 with a conductive material. At this stage, even when the plug of the via hole 330 is formed of, for example, a metal material by plating, the inner surface of the through-hole 332 is covered with the protective layer 390, so that the insulating layer 370 may come into contact with a wet environment. Absent.

  As described above, the insulating layer 370 may be formed of a low dielectric material including holes. As a result, the probe wafer 300 can be formed using a porous low-dielectric material, which is said to be unsuitable for a wet environment such as a plating method, since many are porous and easily infiltrated with liquid.

  In other words, it is preferable that the protective layer forming step is performed prior to the process of bringing the insulating layer 370 into contact with the liquid. Thereby, after the protective layer 390 is formed, the process which touches a liquid can be performed arbitrarily.

  Thereafter, as shown in FIG. 8D, and in the same manner as shown in FIGS. 5C and 5D, the wiring 340 and the connection pads 350 are formed on the back surface of the semiconductor substrate 301. . Further, according to requirements, a surface-side wiring 382 for connecting the device 380 on the surface of the semiconductor substrate 301 to the connection pad 320 or the like may be additionally formed.

  Thus, the protective layer forming step may include a procedure of forming the protective layer 390 through the insulating layer 370 in a direction perpendicular to the surface of the semiconductor substrate 301. Thereby, between the via hole 330 and the device 380 can be surely blocked by the protective layer 390, and the short circuit of the device 380 can be reliably prevented.

  As described above, the element formation stage for forming the device 380 disposed at a position separated from the via hole 330 in the semiconductor substrate 301 and the moisture permeability lower than the moisture permeability of the insulating layer 370 that insulates between the via hole 330 and the device 380. And a protective layer forming step of forming a protective layer 390 disposed between the region where the via hole 330 is formed and the region where the device 380 is formed prior to the via hole forming step. As a result, the holes of the insulating layer 370 do not communicate with the inner surface of the via hole 330, and in the case where the liquid is in contact with the liquid, the insulating layer 370 is prevented from infiltrating the liquid and causing an insulation failure. .

  In addition, although demonstrated with reference to embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. In addition, it is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  For example, the probe wafer 300 is an example of a probe apparatus that forms an electrical connection to a device under test, and the probe apparatus may be formed on a substrate that is not in the form of a wafer. For example, the probe device may be formed on a die-shaped substrate that is arranged corresponding to one or more dies 210. In this case, the probe apparatus can be manufactured by dividing the probe wafer 300 described with reference to FIGS. 1 to 8D into a die shape.

  For example, the probe device may be formed to be approximately the same size as one die 210 to be tested. Alternatively, these dies may be packaged with a film or the like in a state where one die of the probe apparatus and one die 210 to be tested are connected.

  The semiconductor substrate 301 is an example of a test substrate, and a substrate that is not a semiconductor may be used as the test substrate. For example, the test substrate may be a ceramic substrate. Also, a device such as a driver used for testing the device under test 200 may or may not be formed on the substrate of the probe apparatus.

  1 to 8D, an example in which the connection pad 350 and the wiring 340 are formed on the surface connected to the device under test 200 on the substrate of the probe apparatus has been described. In another example, the connection pad 350 and the wiring 340 may be formed on the surface opposite to the surface connected to the device under test 200 in the substrate of the probe apparatus. In this case, the connection pad 350 is formed according to the arrangement of the connection terminals on the test apparatus side. For example, the connection pad 350 may be formed according to the arrangement of the connection terminals in the chuck 121.

  The execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior”. It should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for the sake of convenience, it means that it is essential to carry out in this order. is not.

100 test equipment, 110 test head, 111, 121 chuck, 112, 122, 132, 401 housing, 113, 123, 480 cable, 114, 124, 134 pin electronics, 116, 118, 126, 128, 136 connector, 119 Motherboard, 120 performance board, 129 internal circuit, 130 prober, 200 device under test, 210 die, 220, 320, 350 connection pad, 300 probe wafer, 301 substrate, 310 boundary, 330 via hole, 332 through hole, 340, 382 wiring 360 groove, 370 insulating layer, 380 device, 390 protective layer, 400 line drawing device, 410 image processing device, 420 image display device, 430 support device, 432 X stage, 434 Y stage 436 rotating stage, 438 motor, 440 reference-light source, 450 an imaging device, 460 drawn line portion, 462 actuator, 464 ejection head, 470 a substrate holder

Claims (12)

A probe device manufacturing method for manufacturing a probe device that forms an electrical connection to a device under test,
A via hole forming step for forming a via hole penetrating between the front surface and the back surface of the test substrate on the test substrate;
A surface-side connection pad forming step for forming a surface-side connection pad connected to an end of the via hole on the surface side, on the surface of the test substrate;
A back surface side connection pad, a back surface side end portion of the via hole, and the back surface side connection pad are electrically connected by ejecting and attaching a droplet-shaped conductive material toward the back surface of the test substrate. And a back side conductor pattern forming step of forming a side wiring. The probe device manufacturing method according to claim 1, wherein, in the back surface side conductor pattern forming step, the back surface side connection pad is formed at a position corresponding to the connection pad of the device under test.   3. The probe device manufacturing method according to claim 2, wherein at least one of the via hole forming step and the front surface side connection pad forming step includes a mask process using a mask having a given light shielding pattern.   The probe device manufacturing method according to claim 3, wherein the surface-side connection pad forming step includes a procedure of discharging and attaching a droplet-shaped conductive material toward the back surface of the test substrate.   The probe device manufacturing method according to claim 4, further comprising a groove forming step of forming a groove in the test substrate in a region where the back surface side wiring is formed prior to the back surface side conductor pattern forming step. Forming an element for forming a test element disposed at a position spaced apart from the via hole in the test substrate;
The moisture permeability is lower than the moisture permeability of the insulating layer that insulates between the via hole and the test element, and is disposed between the region where the via hole is formed and the region where the test element is formed. The probe device manufacturing method according to claim 1, further comprising a protective layer forming step of forming a protective layer prior to the via hole forming step.   The probe device manufacturing method according to claim 6, wherein the protective layer forming step includes a procedure of forming the protective layer that blocks a region between the via hole and the insulating layer.   The probe device manufacturing method according to claim 7, wherein the protective layer forming step includes a procedure of forming the protective layer by surrounding a region where the via hole is formed.   The probe device manufacturing method according to claim 8, wherein the protective layer forming step includes a step of forming the protective layer through the insulating layer in a direction perpendicular to the surface of the test substrate.   The probe device manufacturing method according to claim 9, wherein the insulating layer is formed of a low dielectric material including holes.   The probe device manufacturing method according to claim 10, wherein the protective layer forming step is performed prior to a process of bringing the insulating layer into contact with a liquid.   The probe device manufacturing method according to claim 11, wherein the via hole forming step includes a step of piercing the insulating layer and the test substrate by irradiating a region surrounded by the protective layer with a laser.

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