WO2009147804A1 - Method for manufacturing probe device - Google Patents
Method for manufacturing probe device Download PDFInfo
- Publication number
- WO2009147804A1 WO2009147804A1 PCT/JP2009/002366 JP2009002366W WO2009147804A1 WO 2009147804 A1 WO2009147804 A1 WO 2009147804A1 JP 2009002366 W JP2009002366 W JP 2009002366W WO 2009147804 A1 WO2009147804 A1 WO 2009147804A1
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- WO
- WIPO (PCT)
- Prior art keywords
- via hole
- forming step
- forming
- surface side
- probe device
- Prior art date
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
- G01R1/0491—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets for testing integrated circuits on wafers, e.g. wafer-level test cartridge
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R3/00—Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments, e.g. of probe tips
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/06—Measuring leads; Measuring probes
- G01R1/067—Measuring probes
- G01R1/073—Multiple probes
- G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
- G01R1/07342—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being at an angle other than perpendicular to test object, e.g. probe card
Definitions
- the present invention relates to a probe device manufacturing method. More particularly, the present invention relates to a probe apparatus manufacturing method for manufacturing a probe apparatus that is used by being exchanged when forming an electrical connection to a device under test having different specifications in a test apparatus.
- this application is related to the following international application and claims priority from the following international application. For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.
- a part called a probe card or the like is used for the purpose of forming an electrical connection to a fine connection pad on the wafer.
- Probe cards are individually manufactured according to the arrangement of connection pads of devices under test having different specifications. Thereby, a probe card can be replaced
- Patent Document 1 describes a probe wafer used as a probe card.
- the probe wafer is manufactured by processing a wafer which is itself a semiconductor substrate, and electrical connections can be made to a large number of semiconductor devices formed on a single wafer.
- the probe wafer is manufactured individually for each specification of the device under test. Further, in the case of a wafer test, the number of connection pads that form electrical connections reaches a large number, and the arrangement of the connection pads becomes fine. For this reason, it takes time to manufacture the probe wafer, and the probe wafer itself becomes an expensive part.
- a probe apparatus manufacturing method for manufacturing a probe apparatus that forms an electrical connection to a device under test. And a via hole forming step for forming a via hole penetrating between the back surfaces, and a surface side connection pad forming step for forming a surface side connection pad connected to an end portion on the surface side of the via hole on the surface of the test substrate By discharging and adhering a droplet-shaped conductive material toward the back surface of the test substrate, the back surface side connection pad and the back surface side wiring for electrically connecting the back surface side end portion of the via hole and the back surface side connection pad And a backside conductor pattern forming step of forming a probe device.
- FIG. 1 is a diagram schematically showing components of a test apparatus 100.
- FIG. 1 is a diagram schematically showing the structure of a test apparatus 100.
- FIG. 2 is a perspective view showing the shape of a device under test 200.
- FIG. 2 is a perspective view showing a shape of a probe wafer 300.
- FIG. 5 is a cross-sectional view showing a manufacturing process of the probe wafer 300.
- FIG. It is a figure which shows typically the structure of the drawing apparatus 400 which forms the wiring 340.
- FIG. It is a cross-sectional head which shows the structure and manufacturing method of the probe wafer 300 which concern on another form. It is a section head showing the structure and manufacturing method of probe wafer 300 concerning still another form.
- FIG. 1 is a diagram schematically showing the components of the test apparatus 100 separated.
- the test apparatus 100 is formed by sequentially stacking a test head 110, a performance board 120, and a prober 130. Further, the test apparatus 100 may be further used by connecting to a main frame (not shown).
- the test head 110 includes a chuck 111, pin electronics 114, and a motherboard 119 housed in a housing 112.
- the chuck 111 slightly protrudes from the upper surface of the housing 112 and holds a wafer or the like that is the device under test 200 when a test is executed.
- the pin electronics 114 is disposed on the top of the housing 112 and supports the connector 118 with one end exposed on the top surface of the housing 112. In addition, the pin electronics 114 electrically connects the connector 118 to the motherboard 119 via the cable 113 and the connector 116.
- a circuit for comprehensively controlling the operation of the test apparatus 100 is mounted on the motherboard 119, and a storage unit for accumulating evaluation results is also mounted.
- the performance board 120 has a pin electronics 124 and a chuck 121 housed in a housing 122.
- the pin electronics 124 has a plurality of connectors 126 on the top surface.
- the pin electronics 124 is connected to a connector 128 exposed on the lower surface of the housing 122 via the cable 123. Further, an internal circuit 129 is mounted on the pin electronics 124.
- the chuck 121 is fixed with a slight offset upward from the lower surface of the housing 122.
- the probe wafer 300 is held on the chuck 121 of the performance board 120.
- the prober 130 has a housing 132 that houses a plurality of pin electronics 134.
- the pin electronics 134 includes a connector 136 at each lower end.
- the prober 130, the performance board 120, the test head 110, and the probe wafer 300 are provided as parts that can be separated from each other. With such a structure, a wide range of tests can be performed by arbitrarily combining the probe wafer 300, the performance board 120, and the pin electronics 134 according to the type of the device under test 200, the content of the test to be performed, and the like.
- test of the device under test 200 having different specifications such as the arrangement of the connection pads can be handled by exchanging some parts such as the probe wafer 300. Therefore, the operating rate of the test apparatus 100 can be improved and the cost related to the test can be reduced.
- FIG. 2 is a diagram schematically showing the structure of the test apparatus 100 assembled when the test is executed. Components that are the same as those in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted.
- the prober 130 is attached to the performance board 120.
- the connectors 136 and 126 are coupled to each other, the connector 128 of the performance board 120 is coupled to the chuck 121 via the prober 130.
- the probe wafer 300 is held on the lower surface of the chuck 121. As a result, the probe wafer 300 is electrically connected to the chuck 121.
- the assembly in which the prober 130, the performance board 120, and the probe wafer 300 are integrated is mounted on the casing 112 of the test head 110 from above.
- a wafer or the like which is the device under test 200 is mounted on the chuck 111.
- the device under test 200 is coupled to the probe wafer 300 and the connector 118 is coupled to the connector 128. Therefore, a signal path is formed from the mother board 119 of the test head 110 to the device under test 200 via the performance board 120, the prober 130 and the probe wafer 300.
- test of the device under test 200 in the test apparatus 100 When the test of the device under test 200 in the test apparatus 100 is executed, when the test for one device under test 200 is completed, the assembly in which the performance board 120 and the probe wafer 300 are integrated is lifted, and the next device under test is tested. Device 200 is inserted. By repeating this, tests for a plurality of devices under test 200 can be sequentially executed.
- the test is performed by changing the probe wafer 300 to a corresponding one. Can continue.
- any of the pin electronics 134 can be changed and dealt with.
- FIG. 3 is a perspective view schematically illustrating the shape of the device under test 200.
- a device under test 200 which is a semiconductor wafer, has a plurality of dies 210, each of which forms a circuit, an element, etc., formed in a matrix on the surface.
- Each die 210 has a plurality of connection pads 220 that are used when making electrical connections to the outside. In practice, however, the number and density of dies 210 are very high and the number and density of connection pads 220 are even higher.
- FIG. 4 is a perspective view showing the shape of the probe wafer 300.
- FIG. 4A shows the upper surface of the probe wafer 300, that is, the surface held in contact with the chuck 121 of the performance board 120.
- the probe wafer 300 On the upper surface, the probe wafer 300 has a plurality of connection pads 320 arranged according to the arrangement of the connection terminals in the chuck 121. Thereby, when the probe wafer 300 is attracted and held by the chuck 121, the chuck 121 and the probe wafer 300 are electrically connected. Note that a boundary 310 indicated by a dotted line in the drawing indicates the arrangement of the dies 210 in the device under test 200.
- FIG. 4B schematically shows the shape of the lower surface of the probe wafer 300, that is, the surface in contact with the upper surface of the device under test 200 when the test apparatus 100 executes a test.
- connection pads 350 on the probe wafer 300 side are formed at locations corresponding to the connection pads 220 of the device under test 200.
- connection pad 320 of the probe wafer 300 itself are formed on the surface, the lower end of the via hole 330 formed through the probe wafer 300 in the thickness direction appears. Furthermore, the via hole 330 and the connection pad 350 are electrically coupled by the wiring 340. With such a structure, the connection pad 320 on the upper surface of the probe wafer 300 is coupled to the connection pad 350 on the lower surface via the via hole 330 and the wiring 340.
- FIG. 5 is a cross-sectional view showing the manufacturing process of the probe wafer 300.
- a through hole penetrating the front and back of the semiconductor substrate 301 is formed in the semiconductor substrate 301 such as a silicon wafer, and then a conductive material is applied to the through hole.
- the via hole 330 is formed by filling. In this embodiment, the via hole 330 is formed on the boundary 310 of the die 210.
- connection pad 320 As the formation step of the connection pad 320 on the front surface side, the connection pad 320 is formed at the upper end of the via hole 330 on the upper surface of the semiconductor substrate 301. As a result, connection pads 320 that form electrical coupling to the chuck 121 are formed on the upper surface of the semiconductor substrate 301.
- the via hole formation step and the surface side connection pad formation step so far may include a mask process using a mask having a given light-shielding pattern. That is, in the test apparatus 100 including the chuck 121 having a specific specification, the specification and arrangement of the connection pad 320 with respect to the chuck 121 are constant. Therefore, a fixed intermediate product can be mass-produced in advance using a mask that can be used repeatedly. Furthermore, when manufacturing a probe wafer 300 with another specification, as will be described later, the probe wafer 300 according to the specification for each model can be prepared in a short period of time by forming a conductor pattern on the lower surface of the semiconductor substrate 301.
- the arrangement of the wirings 340 and the connection pads 350 formed on the lower surface of the semiconductor substrate 301 may differ depending on the arrangement of the connection pads 220 in the device under test 200. Therefore, the step of forming the conductor pattern on the back surface side of the semiconductor substrate 301 described below is performed individually according to the specifications of the device under test 200.
- the wiring 340 extending from the lower end of the via hole 330 is formed on the lower surface of the semiconductor substrate 301 as shown in FIG. Further, as shown in FIG. 5D, a connection pad 350 is formed at the tip of the wiring 340. Note that the order of the stage illustrated in FIG. 5C and the stage illustrated in FIG. 5D can be reversed.
- the back-side connection pad 350 disposed at a position corresponding to the connection pad 220 of the device under test 200, and the back-side end of the via hole 330 and the back-side connection pad 350 are electrically connected.
- the wiring 340 and the connection pad 350 are individually formed according to the specifications of the device under test 200. For this reason, it is preferable to form using the drawing apparatus 400 which is demonstrated below.
- FIG. 6 is a diagram schematically showing the structure of a line drawing device 400 that can be used when the wiring 340 and the connection pads 350 are formed.
- the line drawing device 400 includes a support device 430, a reference light source 440, an imaging device 450, and a line drawing unit 460 housed inside the housing 401, an image processing device 410 connected to the housing 401 from the outside via a cable 480, and And an image display device 420.
- the support device 430 includes an X stage 432, a Y stage 434, and a rotary stage 436.
- the X stage 432 is driven by a motor 438 and moves in a direction indicated by an arrow X in the drawing.
- the Y stage 434 moves horizontally in a direction orthogonal to the X stage 432 by a motor (not shown).
- the rotary stage 436 rotates the X stage 432 and the Y stage 434 within a horizontal plane.
- the probe wafer 300 held by the substrate holding device 470 on the X stage 432 can be moved in an arbitrary direction.
- the probe wafer 300 is mounted with the surface on which the connection pads 320 on the front side are formed held by the substrate holding device 470 and the back side facing up.
- the reference light source 440 irradiates the reference light toward the probe wafer 300 mounted on the support device 430.
- the imaging device 450 images the reference light reflected by the probe wafer 300 to detect a specific position of the probe wafer 300, for example, an alignment mark, and to determine the amount of movement of the probe wafer 300 accompanying the operation of the support device 430. Measure precisely.
- the drawn part 460 includes an actuator 462 and a discharge head 464.
- the discharge head 464 discharges a liquid conductive material such as conductive ink downward.
- the ejection timing is instructed by an image processing apparatus 410 described later.
- the actuator 462 moves the ejection head 464 up and down and adjusts the distance between the probe wafer 300 mounted on the support device 430 and the ejection head 464.
- a liquid conductive material can be attached to the probe wafer 300 with high accuracy, and conductive patterns such as the wiring 340 and the connection pads 350 can be formed.
- the ejection head 464 can eject a droplet-like insulating material instead of the conductive material to adhere to the probe wafer 300. Thereby, for example, an insulating layer covering the wiring 340 can be formed.
- the image display device 420 can display an image of the probe wafer 300 captured by the imaging device 450 via the image processing device 410. Thereby, the wiring 340 formed by the drawn line part 460, the connection pad 350, etc. can be monitored.
- the position of the connection pad 220 of the device under test 200 can be measured by mounting the device under test 200 on the support device 430 and imaging the device under test 200 with the imaging device 450.
- the image processing apparatus 410 can arrange the connection pad 350 on the back surface of the probe wafer 300 in accordance with the information indicating the position of the connection pad 220 acquired in this way.
- a manufacturing method for manufacturing the probe wafer 300 for forming an electrical connection to the device under test 200 which includes a via hole forming step for forming a via hole 330 penetrating the semiconductor substrate 301 on the front and back sides in the semiconductor substrate 301; A surface-side connection pad forming step for forming a surface-side connection pad 320 connected to the surface-side end of the via hole 330 on the surface of the semiconductor substrate 301, and a droplet-shaped conductive material toward the back surface of the semiconductor substrate 301
- the back-side connection pad 350 disposed at a position corresponding to the connection pad 220 of the device under test 200 and the back-side end and back-side connection pad 350 of the via hole 330 are electrically connected.
- a backside conductor pattern forming step of forming a backside wiring 340 connected to the probe wafer Manufacturing process is carried out.
- connection pad 320 on the front surface side may include a procedure of discharging and attaching a droplet-shaped conductive material toward the surface of the semiconductor substrate 301.
- a surface conductor pattern can also be rapidly manufactured by arbitrary specifications.
- FIG. 7 is a cross-sectional view showing the structure and manufacturing method of a probe wafer 300 according to another embodiment.
- FIG. 7A shows the stage shown in FIG. 5B in the series of steps shown in FIG. 5, that is, the stage to be executed after the via hole 330 and the connection pad 320 on the surface side are formed. .
- the groove 360 is formed on the back surface of the semiconductor substrate 301.
- the groove 360 is formed in a region where the wiring 340 is formed by laser processing or the like. Further, the depth of the groove 360 is smaller than or equal to the thickness of the wiring 340 formed in the next stage shown in FIG.
- wiring 340 is formed on the back surface of the semiconductor substrate 301 in which the groove 360 is thus formed. Thereby, the wiring 340 does not protrude from the back surface of the semiconductor substrate 301.
- connection pad 350 on the back side is formed.
- the connection pad 350 has a thickness such that the top surface protrudes from the back surface of the semiconductor substrate 301. With such a structure, good contact with the connection pad 350 can be expected while maintaining the flatness of the back surface of the probe wafer 300.
- a groove forming step of forming the groove 360 in the semiconductor substrate 301 may be further included in the region where the back surface side wiring 340 is formed. Accordingly, the thickness of the wiring 340 can be increased to reduce the electrical resistance, and the strength of the wiring 340 itself can be improved.
- FIG. 8 is a cross-sectional view showing the structure and manufacturing method of a probe wafer 300 according to still another embodiment.
- the semiconductor substrate 301 on which the probe wafer 300 is formed has a device 380 previously formed on the surface.
- the device 380 is insulated from other devices, wirings, pads, and the like by an insulating layer 370 formed on the surface of the semiconductor substrate 301 around the device 380.
- the probe wafer 300 is manufactured using such a semiconductor substrate 301, as shown in FIG. 8A, first, a region including the via hole 330 is formed, and a region wider than the region is made of a protective material.
- the formed protective layer 390 is formed.
- the protective layer 390 is formed through the insulating layer 370 in the thickness direction.
- the method for manufacturing the probe wafer 300 may include a protective layer forming step of forming the protective layer 390 that blocks between the region where the via hole 330 is formed and the insulating layer 370.
- the insulating layer 370 can be formed using a porous insulating material that easily infiltrates liquid. Therefore, the parasitic capacitance of the semiconductor substrate 301 can be reduced and the signal quality can be kept high.
- a through hole 332 is formed in the region where the protective layer 390 is formed.
- the protective layer 390 remains around the through hole 332.
- the through hole 332 is surrounded by the protective layer 390. Therefore, the insulating layer 370 is not exposed on the inner surface of the through hole 332.
- the protective layer forming step may include a procedure of forming a protective layer 390 surrounding a region where the via hole 330 is formed. Furthermore, the method for manufacturing the probe wafer 300 may include a via hole forming step including a step of piercing the insulating layer 370 and the semiconductor substrate 301 by irradiating a region surrounded by the protective layer 390 with a laser. Thereby, the via hole 330 surrounded by the protective layer 390 can be reliably formed.
- the via hole 330 is formed by filling the through hole 332 with a conductive material.
- the plug of the via hole 330 is formed of, for example, a metal material by plating
- the inner surface of the through-hole 332 is covered with the protective layer 390, so that the insulating layer 370 may come into contact with a wet environment. Absent.
- the insulating layer 370 may be formed of a low dielectric material including holes.
- the probe wafer 300 can be formed using a porous low-dielectric material, which is said to be unsuitable for a wet environment such as a plating method, since many are porous and easily infiltrated with liquid.
- the protective layer forming step be performed prior to the process of bringing the insulating layer 370 into contact with the liquid. Thereby, after the protective layer 390 is formed, the process which touches a liquid can be performed arbitrarily.
- the wiring 340 and the connection pads 350 are formed on the back surface of the semiconductor substrate 301.
- a surface-side wiring 382 for connecting the device 380 on the surface of the semiconductor substrate 301 to the connection pad 320 or the like may be additionally formed.
- the protective layer forming step may include a procedure of forming the protective layer 390 through the insulating layer 370 in a direction perpendicular to the surface of the semiconductor substrate 301. Thereby, between the via hole 330 and the device 380 can be surely blocked by the protective layer 390, and the short circuit of the device 380 can be reliably prevented.
- the element formation stage for forming the device 380 disposed at a position separated from the via hole 330 in the semiconductor substrate 301 and the moisture permeability lower than the moisture permeability of the insulating layer 370 that insulates between the via hole 330 and the device 380.
- the holes of the insulating layer 370 do not communicate with the inner surface of the via hole 330, and it is prevented that the liquid is infiltrated into the insulating layer 370 and causes insulation failure when the liquid is in contact with the liquid. .
- the probe wafer 300 is an example of a probe apparatus that forms an electrical connection to a device under test, and the probe apparatus may be formed on a substrate that is not in the form of a wafer.
- the probe device may be formed on a die-shaped substrate that is arranged corresponding to one or more dies 210.
- the probe apparatus can be manufactured by dividing the probe wafer 300 described with reference to FIGS. 1 to 8D into a die shape.
- the probe device may be formed to have substantially the same size as one test target die 210.
- these dies may be packaged with a film or the like in a state where one die of the probe apparatus and one die 210 to be tested are connected.
- the semiconductor substrate 301 is an example of a test substrate, and a substrate that is not a semiconductor may be used as the test substrate.
- the test substrate may be a ceramic substrate.
- a device such as a driver used for testing the device under test 200 may or may not be formed on the substrate of the probe apparatus.
- connection pad 350 and the wiring 340 are formed on the surface connected to the device under test 200 on the substrate of the probe apparatus.
- the connection pad 350 and the wiring 340 may be formed on the surface opposite to the surface connected to the device under test 200 in the substrate of the probe apparatus.
- the connection pad 350 is formed according to the arrangement of the connection terminals on the test apparatus side.
- the connection pad 350 may be formed according to the arrangement of the connection terminals in the chuck 121.
- test apparatus 110 test head, 111, 121 chuck, 112, 122, 132, 401 housing, 113, 123, 480 cable, 114, 124, 134 pin electronics, 116, 118, 126, 128, 136 connector, 119 Motherboard, 120 performance board, 129 internal circuit, 130 prober, 200 device under test, 210 die, 220, 320, 350 connection pad, 300 probe wafer, 301 substrate, 310 boundary, 330 via hole, 332 through hole, 340, 382 wiring 360 groove, 370 insulating layer, 380 device, 390 protective layer, 400 line drawing device, 410 image processing device, 420 image display device, 430 support device, 432 X stage 434 Y stage, 436 rotating stage, 438 motor, 440 reference-light source, 450 an imaging device, 460 drawn line portion, 462 actuator, 464 ejection head, 470 a substrate holder
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Adjustment in a short period of time corresponding to specifications of a device to be tested is made possible in manufacture of a probe device which forms electrical connection to the device to be tested.
A method for manufacturing a probe device includes: a via hole forming step of forming a via hole (330) which penetrates a testing substrate (301) from the front to the rear; a front surface side connecting pad forming step of forming a front surface side connecting pad (320) connected to a front surface side end portion of the via hole on the front surface of the testing substrate; and a rear surface side conductor pattern forming step of forming a rear surface side connecting pad (350) and a rear surface side wiring (340) which electrically connects the rear surface side end portion of the via hole and the rear surface side connecting pad, by jetting droplets of a conductive material toward the rear surface of the testing substrate and adhering the material thereon.
Description
本発明は、プローブ装置製造方法に関する。より詳細には、試験装置において仕様の異なる被試験デバイスへの電気的接続を形成する場合に交換して使用するプローブ装置を製造するプローブ装置製造方法に関する。また、本出願は、下記の国際出願に関連し、下記の国際出願からの優先権を主張する出願である。文献の参照による組み込みが認められる指定国については、下記の出願に記載された内容を参照により本出願に組み込み、本出願の一部とする。
PCT/JP2008/060170 出願日2008年6月2日 The present invention relates to a probe device manufacturing method. More particularly, the present invention relates to a probe apparatus manufacturing method for manufacturing a probe apparatus that is used by being exchanged when forming an electrical connection to a device under test having different specifications in a test apparatus. In addition, this application is related to the following international application and claims priority from the following international application. For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.
PCT / JP2008 / 060170 Filing date June 2, 2008
PCT/JP2008/060170 出願日2008年6月2日 The present invention relates to a probe device manufacturing method. More particularly, the present invention relates to a probe apparatus manufacturing method for manufacturing a probe apparatus that is used by being exchanged when forming an electrical connection to a device under test having different specifications in a test apparatus. In addition, this application is related to the following international application and claims priority from the following international application. For designated countries where incorporation by reference of documents is permitted, the contents described in the following application are incorporated into this application by reference and made a part of this application.
PCT / JP2008 / 060170 Filing date June 2, 2008
被試験デバイスをダイまたはウエハ状態のまま試験するウエハ試験においては、ウエハ上の微細な接続パッドに対して電気的な接続を形成する目的で、プローブカード等と呼ばれる部品が用いられる。プローブカードは、仕様の異なる被試験デバイスの接続パッドの配置に応じて個別に製造される。これにより、プローブカードを交換して、高価な試験装置の利用効率を向上させることができる。
In a wafer test in which a device under test is tested in a die or wafer state, a part called a probe card or the like is used for the purpose of forming an electrical connection to a fine connection pad on the wafer. Probe cards are individually manufactured according to the arrangement of connection pads of devices under test having different specifications. Thereby, a probe card can be replaced | exchanged and the utilization efficiency of an expensive test apparatus can be improved.
下記の特許文献1には、プローブカードとして用いるプローブウエハが記載される。プローブウエハは、それ自体が半導体基板であるウエハを加工して製造され、一枚のウエハに形成された多数の半導体デバイスに対して、電気的接続を一括して形成できる。
The following Patent Document 1 describes a probe wafer used as a probe card. The probe wafer is manufactured by processing a wafer which is itself a semiconductor substrate, and electrical connections can be made to a large number of semiconductor devices formed on a single wafer.
しかしながら、プローブウエハは、被試験デバイスの仕様毎に個別に製造される。また、ウエハテストの場合は、電気的な接続を形成する接続パッドの数が多数に及ぶと共に、接続パッドの配置も細密になる。このため、プローブウエハの製造に時間がかかると共に、プローブウエハ自体が高価な部品になる。
However, the probe wafer is manufactured individually for each specification of the device under test. Further, in the case of a wafer test, the number of connection pads that form electrical connections reaches a large number, and the arrangement of the connection pads becomes fine. For this reason, it takes time to manufacture the probe wafer, and the probe wafer itself becomes an expensive part.
上記課題を解決するために、本発明の第1の態様として、被試験デバイスに対する電気的接続を形成するプローブ装置を製造するプローブ装置製造方法であって、試験用基板に、試験用基板の表面および裏面の間を貫通するビアホールを形成するビアホール形成段階と、ビアホールの表面の側の端部に接続された表面側接続パッドを、試験用基板の表面に形成する表面側接続パッド形成段階と、試験用基板の裏面に向かって液滴状の導電材料を吐出して付着させることにより、裏面側接続パッドと、ビアホールの裏面側端部および裏面側接続パッドを電気的に接続する裏面側配線とを形成する裏面側導体パターン形成段階とを含むプローブ装置製造方法が提供される。
In order to solve the above-mentioned problem, as a first aspect of the present invention, there is provided a probe apparatus manufacturing method for manufacturing a probe apparatus that forms an electrical connection to a device under test. And a via hole forming step for forming a via hole penetrating between the back surfaces, and a surface side connection pad forming step for forming a surface side connection pad connected to an end portion on the surface side of the via hole on the surface of the test substrate By discharging and adhering a droplet-shaped conductive material toward the back surface of the test substrate, the back surface side connection pad and the back surface side wiring for electrically connecting the back surface side end portion of the via hole and the back surface side connection pad And a backside conductor pattern forming step of forming a probe device.
なお、上記の発明の概要は、本発明の必要な特徴の全てを列挙したものではない。また、これらの特徴群のサブコンビネーションもまた、発明となりうる。
Note that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.
以下、発明の実施の形態を通じて本発明を説明するが、以下の実施形態は請求の範囲にかかる発明を限定するものではない。また、実施形態の中で説明されている特徴の組み合わせの全てが発明の解決手段に必須であるとは限らない。
Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.
図1は、試験装置100の構成要素を分離して模式的に示す図である。試験装置100は、テストヘッド110、パフォーマンスボード120およびプローバ130を順次積層して形成される。また、試験装置100は、更に、図示されていないメインフレームに接続して使用され場合もある。
FIG. 1 is a diagram schematically showing the components of the test apparatus 100 separated. The test apparatus 100 is formed by sequentially stacking a test head 110, a performance board 120, and a prober 130. Further, the test apparatus 100 may be further used by connecting to a main frame (not shown).
テストヘッド110は、筐体112に収容された、チャック111、ピンエレクトロニクス114およびマザーボード119を有する。チャック111は、筐体112の上面から僅かに突出して、試験を実行する場合に被試験デバイス200であるウエハ等を保持する。
The test head 110 includes a chuck 111, pin electronics 114, and a motherboard 119 housed in a housing 112. The chuck 111 slightly protrudes from the upper surface of the housing 112 and holds a wafer or the like that is the device under test 200 when a test is executed.
ピンエレクトロニクス114は、筐体112の上部に配され、一端を筐体112の上面に露出させたコネクタ118を支持する。また、ピンエレクトロニクス114は、ケーブル113およびコネクタ116を介して、コネクタ118をマザーボード119に電気的に接続される。マザーボード119には、この試験装置100の動作を統括的に制御する回路が実装されると共に、評価結果を蓄積する格納部等も実装される。
The pin electronics 114 is disposed on the top of the housing 112 and supports the connector 118 with one end exposed on the top surface of the housing 112. In addition, the pin electronics 114 electrically connects the connector 118 to the motherboard 119 via the cable 113 and the connector 116. A circuit for comprehensively controlling the operation of the test apparatus 100 is mounted on the motherboard 119, and a storage unit for accumulating evaluation results is also mounted.
パフォーマンスボード120は、筐体122に収容された、ピンエレクトロニクス124およびチャック121を有する。ピンエレクトロニクス124は、複数のコネクタ126を上面に有する。また、ピンエレクトロニクス124は、ケーブル123を介して、筐体122の下面に露出したコネクタ128に接続される。更に、ピンエレクトロニクス124には、内部回路129が実装される。
The performance board 120 has a pin electronics 124 and a chuck 121 housed in a housing 122. The pin electronics 124 has a plurality of connectors 126 on the top surface. The pin electronics 124 is connected to a connector 128 exposed on the lower surface of the housing 122 via the cable 123. Further, an internal circuit 129 is mounted on the pin electronics 124.
チャック121は、筐体122の下面から、上方にややオフセットして固定される。試験装置100において試験が実行される場合、パフォーマンスボード120のチャック121にはプローブウエハ300が保持される。
The chuck 121 is fixed with a slight offset upward from the lower surface of the housing 122. When a test is executed in the test apparatus 100, the probe wafer 300 is held on the chuck 121 of the performance board 120.
プローバ130は、複数のピンエレクトロニクス134を収容する筐体132を有する。ピンエレクトロニクス134は、それぞれの下端にコネクタ136を備える。
The prober 130 has a housing 132 that houses a plurality of pin electronics 134. The pin electronics 134 includes a connector 136 at each lower end.
このように、プローバ130、パフォーマンスボード120、テストヘッド110およびプローブウエハ300は、相互に分離することができる部品として提供される。このような構造により、被試験デバイス200の種類、実行すべき試験の内容等に応じて、プローブウエハ300、パフォーマンスボード120およびピンエレクトロニクス134を任意に組み合わせて広範な試験を実行できる。
Thus, the prober 130, the performance board 120, the test head 110, and the probe wafer 300 are provided as parts that can be separated from each other. With such a structure, a wide range of tests can be performed by arbitrarily combining the probe wafer 300, the performance board 120, and the pin electronics 134 according to the type of the device under test 200, the content of the test to be performed, and the like.
また、接続パッドの配置等の仕様が異なる被試験デバイス200の試験も、プローブウエハ300等の一部の部品を交換することにより対応できる。従って、試験装置100の稼働率を向上させて試験に係るコストを圧縮できる。
Also, the test of the device under test 200 having different specifications such as the arrangement of the connection pads can be handled by exchanging some parts such as the probe wafer 300. Therefore, the operating rate of the test apparatus 100 can be improved and the cost related to the test can be reduced.
図2は、試験を実行する場合に組み立てられた試験装置100の構造を模式的に示す図である。なお、図1と共通の構成要素には同じ参照番号を付して重複する説明を省く。
FIG. 2 is a diagram schematically showing the structure of the test apparatus 100 assembled when the test is executed. Components that are the same as those in FIG. 1 are given the same reference numerals, and redundant descriptions are omitted.
組み立てられた試験装置100においては、パフォーマンスボード120に対して、プローバ130が装着される。このとき、コネクタ136、126が相互に結合されるのでパフォーマンスボード120のコネクタ128は、プローバ130を介して、チャック121に結合される。
In the assembled test apparatus 100, the prober 130 is attached to the performance board 120. At this time, since the connectors 136 and 126 are coupled to each other, the connector 128 of the performance board 120 is coupled to the chuck 121 via the prober 130.
また、チャック121の下面には、プローブウエハ300が保持される。これにより、プローブウエハ300は、チャック121に対して電気的に接続される。
Also, the probe wafer 300 is held on the lower surface of the chuck 121. As a result, the probe wafer 300 is electrically connected to the chuck 121.
また、プローバ130、パフォーマンスボード120およびプローブウエハ300が一体化された組立体は、テストヘッド110の筐体112に上方から搭載される。このとき、被試験デバイス200であるウエハ等が、チャック111に搭載される。これにより、被試験デバイス200はプローブウエハ300に、コネクタ118はコネクタ128に、それぞれ結合される。従って、テストヘッド110のマザーボード119から、パフォーマンスボード120、プローバ130およびプローブウエハ300を介した、被試験デバイス200までの信号経路が形成される。
The assembly in which the prober 130, the performance board 120, and the probe wafer 300 are integrated is mounted on the casing 112 of the test head 110 from above. At this time, a wafer or the like which is the device under test 200 is mounted on the chuck 111. As a result, the device under test 200 is coupled to the probe wafer 300 and the connector 118 is coupled to the connector 128. Therefore, a signal path is formed from the mother board 119 of the test head 110 to the device under test 200 via the performance board 120, the prober 130 and the probe wafer 300.
試験装置100における被試験デバイス200の試験を実行する場合、1枚の被試験デバイス200に対する試験が終了すると、パフォーマンスボード120およびプローブウエハ300が一体化された組立体を持ち上げて、次の被試験デバイス200が装入される。これを繰り返すことにより、複数の被試験デバイス200に対する試験を順次実行できる。
When the test of the device under test 200 in the test apparatus 100 is executed, when the test for one device under test 200 is completed, the assembly in which the performance board 120 and the probe wafer 300 are integrated is lifted, and the next device under test is tested. Device 200 is inserted. By repeating this, tests for a plurality of devices under test 200 can be sequentially executed.
また、被試験デバイスの仕様が変更になった場合、変更された仕様が、例えば被試験デバイス200の接続パッドの配置であれば、プローブウエハ300を、それに応じたものに変更することにより、試験を継続できる。また、試験内容が変更になった場合は、ピンエレクトロニクス134のいずれかを変更して対応することができる。
Further, when the specification of the device under test is changed, if the changed specification is, for example, the arrangement of the connection pads of the device under test 200, the test is performed by changing the probe wafer 300 to a corresponding one. Can continue. In addition, when the test contents are changed, any of the pin electronics 134 can be changed and dealt with.
図3は、被試験デバイス200の形状を模式的に例示する斜視図である。半導体ウエハである被試験デバイス200は、その表面に、各々が回路、素子等を形成する複数のダイ210をマトリクス状に形成されている。ダイ210の各々は、外部に対する電気的接続を形成する場合に使用される、複数の接続パッド220を有する。ただし、実際には、ダイ210の数および密度は非常に高く、接続パッド220の数および密度は更に高い。
FIG. 3 is a perspective view schematically illustrating the shape of the device under test 200. A device under test 200, which is a semiconductor wafer, has a plurality of dies 210, each of which forms a circuit, an element, etc., formed in a matrix on the surface. Each die 210 has a plurality of connection pads 220 that are used when making electrical connections to the outside. In practice, however, the number and density of dies 210 are very high and the number and density of connection pads 220 are even higher.
図4は、プローブウエハ300の形状を示す斜視図である。図4(a)は、プローブウエハ300の上面、即ち、パフォーマンスボード120のチャック121に接して保持される面を示す。
FIG. 4 is a perspective view showing the shape of the probe wafer 300. FIG. 4A shows the upper surface of the probe wafer 300, that is, the surface held in contact with the chuck 121 of the performance board 120.
当該上面において、プローブウエハ300は、チャック121における接続端子の配置に応じて配置された複数の接続パッド320を有する。これにより、プローブウエハ300がチャック121に吸着して保持された場合に、チャック121およびプローブウエハ300が電気的に接続される。なお、図中の点線で示す境界310は、被試験デバイス200におけるダイ210の配置を示す。
On the upper surface, the probe wafer 300 has a plurality of connection pads 320 arranged according to the arrangement of the connection terminals in the chuck 121. Thereby, when the probe wafer 300 is attracted and held by the chuck 121, the chuck 121 and the probe wafer 300 are electrically connected. Note that a boundary 310 indicated by a dotted line in the drawing indicates the arrangement of the dies 210 in the device under test 200.
図4(b)は、プローブウエハ300の下面、即ち、試験装置100が試験を実行する場合に被試験デバイス200の上面に接する面の形状を模式的に示す。プローブウエハ300の下面には、被試験デバイス200の接続パッド220に対応した箇所に、プローブウエハ300側の接続パッド350が形成される。
FIG. 4B schematically shows the shape of the lower surface of the probe wafer 300, that is, the surface in contact with the upper surface of the device under test 200 when the test apparatus 100 executes a test. On the lower surface of the probe wafer 300, connection pads 350 on the probe wafer 300 side are formed at locations corresponding to the connection pads 220 of the device under test 200.
また、表面においてプローブウエハ300自身の接続パッド320が形成された領域には、プローブウエハ300を厚さ方向に貫通して形成されたビアホール330の下端が現れる。更に、ビアホール330および接続パッド350は、配線340により電気的に結合される。このような構造により、プローブウエハ300の上面の接続パッド320は、ビアホール330および配線340を介して、下面の接続パッド350に結合される。
Also, in the region where the connection pads 320 of the probe wafer 300 itself are formed on the surface, the lower end of the via hole 330 formed through the probe wafer 300 in the thickness direction appears. Furthermore, the via hole 330 and the connection pad 350 are electrically coupled by the wiring 340. With such a structure, the connection pad 320 on the upper surface of the probe wafer 300 is coupled to the connection pad 350 on the lower surface via the via hole 330 and the wiring 340.
図5は、プローブウエハ300の製造工程を示す断面図である。まず、図5(A)に示すように、ビアホール330の形成段階として、シリコンウエハ等の半導体基板301に、半導体基板301の表裏を貫通する貫通孔を形成した後、当該貫通孔に導体材料を充填してビアホール330を形成する。なお、この実施形態においては、ビアホール330は、ダイ210の境界310上に形成される。
FIG. 5 is a cross-sectional view showing the manufacturing process of the probe wafer 300. First, as shown in FIG. 5A, as a step of forming the via hole 330, a through hole penetrating the front and back of the semiconductor substrate 301 is formed in the semiconductor substrate 301 such as a silicon wafer, and then a conductive material is applied to the through hole. The via hole 330 is formed by filling. In this embodiment, the via hole 330 is formed on the boundary 310 of the die 210.
次に、図5(B)に示すように、表面側の接続パッド320の形成段階として、半導体基板301の上面において、ビアホール330の上端に接続パッド320が形成される。これにより、半導体基板301の上面に、チャック121に対して電気的な結合を形成する接続パッド320が形成される。
Next, as shown in FIG. 5B, as the formation step of the connection pad 320 on the front surface side, the connection pad 320 is formed at the upper end of the via hole 330 on the upper surface of the semiconductor substrate 301. As a result, connection pads 320 that form electrical coupling to the chuck 121 are formed on the upper surface of the semiconductor substrate 301.
なお、ここまでのビアホール形成段階および表面側接続パッド形成段階は、所与の遮光パターンを有するマスクを用いたマスクプロセスを含んでもよい。即ち、特定仕様のチャック121を含む試験装置100において、チャック121に対する接続パッド320の仕様および配置は一定になる。従って、繰り返し使用できるマスクを用いて、定型の中間製品を予め量産して用意しておくことができる。更に、別の仕様のプローブウエハ300を製造する場合には、後述するように、半導体基板301下面の導体パターンを形成すれば、短期間で機種毎の仕様に応じたプローブウエハ300を調製できる。
Note that the via hole formation step and the surface side connection pad formation step so far may include a mask process using a mask having a given light-shielding pattern. That is, in the test apparatus 100 including the chuck 121 having a specific specification, the specification and arrangement of the connection pad 320 with respect to the chuck 121 are constant. Therefore, a fixed intermediate product can be mass-produced in advance using a mask that can be used repeatedly. Furthermore, when manufacturing a probe wafer 300 with another specification, as will be described later, the probe wafer 300 according to the specification for each model can be prepared in a short period of time by forming a conductor pattern on the lower surface of the semiconductor substrate 301.
これに対して、半導体基板301の下面に形成する配線340および接続パッド350の配置は、被試験デバイス200における接続パッド220の配置に応じて異なる場合がある。そこで、以下に説明する、半導体基板301の裏面側の導体パターンを形成段階は、被試験デバイス200の仕様に応じて、個別に実行される。
On the other hand, the arrangement of the wirings 340 and the connection pads 350 formed on the lower surface of the semiconductor substrate 301 may differ depending on the arrangement of the connection pads 220 in the device under test 200. Therefore, the step of forming the conductor pattern on the back surface side of the semiconductor substrate 301 described below is performed individually according to the specifications of the device under test 200.
即ち、被試験デバイス200の仕様が判った段階で、図5(C)に示すように、半導体基板301の下面に、ビアホール330の下端から延在する配線340が形成される。また、図5(D)に示すように、配線340の先端に、接続パッド350が形成される。なお、図5(C)に示す段階と、図5(D)に示す段階との順序は、逆にすることもできる。
That is, when the specifications of the device under test 200 are known, the wiring 340 extending from the lower end of the via hole 330 is formed on the lower surface of the semiconductor substrate 301 as shown in FIG. Further, as shown in FIG. 5D, a connection pad 350 is formed at the tip of the wiring 340. Note that the order of the stage illustrated in FIG. 5C and the stage illustrated in FIG. 5D can be reversed.
このような一連の手順により、被試験デバイス200の接続パッド220に対応した位置に配置された裏面側の接続パッド350と、ビアホール330の裏面側端部および裏面側の接続パッド350とを電気的に接続する裏面側の配線340とが形成される。従って、半導体基板301に、チャック121に対する接続パッド320と、被試験デバイス200に対する接続パッド350と、接続パッド320、350を相互に接続するビアホール330および配線340を備えたプローブウエハ300が形成される。
Through such a series of procedures, the back-side connection pad 350 disposed at a position corresponding to the connection pad 220 of the device under test 200, and the back-side end of the via hole 330 and the back-side connection pad 350 are electrically connected. And a wiring 340 on the back surface side connected to the. Therefore, a probe wafer 300 having a connection pad 320 for the chuck 121, a connection pad 350 for the device under test 200, a via hole 330 and a wiring 340 for connecting the connection pads 320 and 350 to each other is formed on the semiconductor substrate 301. .
なお、上記のように、配線340および接続パッド350は、被試験デバイス200の仕様に応じて個別に形成される。このため、以下に説明するような描線装置400を用いて形成することが好ましい。
Note that, as described above, the wiring 340 and the connection pad 350 are individually formed according to the specifications of the device under test 200. For this reason, it is preferable to form using the drawing apparatus 400 which is demonstrated below.
即ち、図6は、配線340および接続パッド350を形成する場合に使用し得る描線装置400の構造を模式的に示す図である。描線装置400は、筐体401の内部に収容された支持装置430、参照光源440、撮像装置450および描線部460と、ケーブル480を介して筐体401に外部から接続された画像処理装置410および画像表示装置420とを備える。
That is, FIG. 6 is a diagram schematically showing the structure of a line drawing device 400 that can be used when the wiring 340 and the connection pads 350 are formed. The line drawing device 400 includes a support device 430, a reference light source 440, an imaging device 450, and a line drawing unit 460 housed inside the housing 401, an image processing device 410 connected to the housing 401 from the outside via a cable 480, and And an image display device 420.
支持装置430は、Xステージ432、Yステージ434、回転ステージ436を含む。Xステージ432は、モータ438により駆動され、図中に矢印Xにより示す方向に移動する。Yステージ434は、図示されていないモータにより、Xステージ432と直交する方向に、水平に移動する。
The support device 430 includes an X stage 432, a Y stage 434, and a rotary stage 436. The X stage 432 is driven by a motor 438 and moves in a direction indicated by an arrow X in the drawing. The Y stage 434 moves horizontally in a direction orthogonal to the X stage 432 by a motor (not shown).
更に、回転ステージ436は、Xステージ432およびYステージ434を、水平面内で回転させる。これらXステージ432、Yステージ434、回転ステージ436の動作を組み合わせることにより、Xステージ432上の基板保持装置470に保持されたプローブウエハ300を、任意の方向に移動させることができる。なお、プローブウエハ300は、表面側の接続パッド320が形成された表面を基板保持装置470に保持され、裏面を上に向けて搭載される。
Further, the rotary stage 436 rotates the X stage 432 and the Y stage 434 within a horizontal plane. By combining the operations of the X stage 432, the Y stage 434, and the rotary stage 436, the probe wafer 300 held by the substrate holding device 470 on the X stage 432 can be moved in an arbitrary direction. The probe wafer 300 is mounted with the surface on which the connection pads 320 on the front side are formed held by the substrate holding device 470 and the back side facing up.
参照光源440は、支持装置430に搭載されたプローブウエハ300に向かって参照光を照射する。撮像装置450は、プローブウエハ300により反射された参照光を撮像して、プローブウエハ300の特定の位置、例えば、アラインメントマークを検出すると共に、支持装置430の動作に伴うプローブウエハ300の移動量を精密に測定する。
The reference light source 440 irradiates the reference light toward the probe wafer 300 mounted on the support device 430. The imaging device 450 images the reference light reflected by the probe wafer 300 to detect a specific position of the probe wafer 300, for example, an alignment mark, and to determine the amount of movement of the probe wafer 300 accompanying the operation of the support device 430. Measure precisely.
描線部460は、アクチュエータ462および吐出ヘッド464を含む。吐出ヘッド464は、導電性インク等の液体状の導電材料を下方に向かって吐出する。吐出するタイミングは、後述する画像処理装置410により指示される。アクチュエータ462は、吐出ヘッド464を昇降させ、支持装置430に搭載されたプローブウエハ300と吐出ヘッド464との間隔を調節する。
The drawn part 460 includes an actuator 462 and a discharge head 464. The discharge head 464 discharges a liquid conductive material such as conductive ink downward. The ejection timing is instructed by an image processing apparatus 410 described later. The actuator 462 moves the ejection head 464 up and down and adjusts the distance between the probe wafer 300 mounted on the support device 430 and the ejection head 464.
これにより、液体状の導電材料を、プローブウエハ300に精度よく付着させ、配線340、接続パッド350等の導電パターンを形成できる。なお、吐出ヘッド464は、導電材料に替えて、液滴状の絶縁材料を吐出してプローブウエハ300に付着させることもできる。これにより、例えば、配線340を被覆する絶縁層を形成することもできる。
Thereby, a liquid conductive material can be attached to the probe wafer 300 with high accuracy, and conductive patterns such as the wiring 340 and the connection pads 350 can be formed. Note that the ejection head 464 can eject a droplet-like insulating material instead of the conductive material to adhere to the probe wafer 300. Thereby, for example, an insulating layer covering the wiring 340 can be formed.
画像表示装置420は、画像処理装置410を介して、撮像装置450が撮像したプローブウエハ300の映像を表示できる。これにより、描線部460により形成される配線340、接続パッド350等を監視できる。
The image display device 420 can display an image of the probe wafer 300 captured by the imaging device 450 via the image processing device 410. Thereby, the wiring 340 formed by the drawn line part 460, the connection pad 350, etc. can be monitored.
また、支持装置430に、被試験デバイス200を搭載して撮像装置450により被試験デバイス200を撮像することにより、被試験デバイス200の接続パッド220の位置を測定することもできる。画像処理装置410は、こうして獲得した接続パッド220の位置を示す情報に対応して、プローブウエハ300の裏面に、接続パッド350を配置できる。
Also, the position of the connection pad 220 of the device under test 200 can be measured by mounting the device under test 200 on the support device 430 and imaging the device under test 200 with the imaging device 450. The image processing apparatus 410 can arrange the connection pad 350 on the back surface of the probe wafer 300 in accordance with the information indicating the position of the connection pad 220 acquired in this way.
このようにして、被試験デバイス200に対する電気的接続を形成するプローブウエハ300を製造する製造方法であって、半導体基板301に、半導体基板301を表裏に貫通するビアホール330を形成するビアホール形成段階と、ビアホール330の表面側端部に接続された表面側の接続パッド320を、半導体基板301の表面に形成する表面側接続パッド形成段階と、半導体基板301の裏面に向かって液滴状の導電材料を吐出して付着させることにより、被試験デバイス200の接続パッド220に対応した位置に配置された裏面側の接続パッド350と、ビアホール330の裏面側端部および裏面側の接続パッド350を電気的に接続する裏面側の配線340とを形成する裏面側導体パターン形成段階とを含むプローブウエハ製造方法が実施される。
In this way, a manufacturing method for manufacturing the probe wafer 300 for forming an electrical connection to the device under test 200, which includes a via hole forming step for forming a via hole 330 penetrating the semiconductor substrate 301 on the front and back sides in the semiconductor substrate 301; A surface-side connection pad forming step for forming a surface-side connection pad 320 connected to the surface-side end of the via hole 330 on the surface of the semiconductor substrate 301, and a droplet-shaped conductive material toward the back surface of the semiconductor substrate 301 By discharging and adhering, the back-side connection pad 350 disposed at a position corresponding to the connection pad 220 of the device under test 200 and the back-side end and back-side connection pad 350 of the via hole 330 are electrically connected. And a backside conductor pattern forming step of forming a backside wiring 340 connected to the probe wafer Manufacturing process is carried out.
なお、表面側の接続パッド320の形成も、半導体基板301の表面に向かって液滴状の導電材料を吐出して付着させる手順を含んでもよい。これにより、表面導体パターンも、任意の仕様で迅速に製造できる。
It should be noted that the formation of the connection pad 320 on the front surface side may include a procedure of discharging and attaching a droplet-shaped conductive material toward the surface of the semiconductor substrate 301. Thereby, a surface conductor pattern can also be rapidly manufactured by arbitrary specifications.
図7は、他の形態に係るプローブウエハ300の構造と製造方法を示す断面図である。図7(A)は、図5に示した一連の工程のうち、図5(B)に示した段階、即ち、ビアホール330および表面側の接続パッド320が形成された後に実行される段階を示す。
FIG. 7 is a cross-sectional view showing the structure and manufacturing method of a probe wafer 300 according to another embodiment. FIG. 7A shows the stage shown in FIG. 5B in the series of steps shown in FIG. 5, that is, the stage to be executed after the via hole 330 and the connection pad 320 on the surface side are formed. .
図7(A)に示すように、この段階においては、半導体基板301の裏面側における配線340および接続パッド350の形成に先立って、半導体基板301の裏面に、溝360を形成する。溝360は、レーザ加工等により、配線340が形成される領域に形成される。また、溝360の深さは、図7(B)に示す次の段階で形成される配線340の厚さよりも小さいか等しい。
As shown in FIG. 7A, at this stage, prior to the formation of the wiring 340 and the connection pad 350 on the back surface side of the semiconductor substrate 301, the groove 360 is formed on the back surface of the semiconductor substrate 301. The groove 360 is formed in a region where the wiring 340 is formed by laser processing or the like. Further, the depth of the groove 360 is smaller than or equal to the thickness of the wiring 340 formed in the next stage shown in FIG.
こうして溝360を形成された半導体基板301の裏面には、図7(B)に示すように、配線340が形成される。これにより、配線340が、半導体基板301の裏面から隆起することがない。
As shown in FIG. 7B, wiring 340 is formed on the back surface of the semiconductor substrate 301 in which the groove 360 is thus formed. Thereby, the wiring 340 does not protrude from the back surface of the semiconductor substrate 301.
続いて、図7(C)に示すように、裏面側の接続パッド350が形成される。接続パッド350は、その頂面が、半導体基板301の裏面から突出する厚さを有する。このような構造により、プローブウエハ300の裏面の平坦性を維持しつつ、接続パッド350による良好な接触を期することができる。
Subsequently, as shown in FIG. 7C, a connection pad 350 on the back side is formed. The connection pad 350 has a thickness such that the top surface protrudes from the back surface of the semiconductor substrate 301. With such a structure, good contact with the connection pad 350 can be expected while maintaining the flatness of the back surface of the probe wafer 300.
このように、裏面側配線形成段階に先立って、裏面側の配線340が形成される領域において、半導体基板301に溝360を形成する溝形成段階を更に含んでもよい。これにより、配線340の膜厚を大きくして電気抵抗を低減できると共に、配線340自体の強度を向上させることができる。
Thus, prior to the back surface side wiring formation step, a groove forming step of forming the groove 360 in the semiconductor substrate 301 may be further included in the region where the back surface side wiring 340 is formed. Accordingly, the thickness of the wiring 340 can be increased to reduce the electrical resistance, and the strength of the wiring 340 itself can be improved.
図8は、更に他の形態に係るプローブウエハ300の構造と製造方法を示す断面図である。この実施形態において、プローブウエハ300を形成する半導体基板301は、予め表面に形成されたデバイス380を有している。また、デバイス380は、その周囲において、半導体基板301表面に形成された絶縁層370により、他のデバイス、配線、パッド等から絶縁されている。
FIG. 8 is a cross-sectional view showing the structure and manufacturing method of a probe wafer 300 according to still another embodiment. In this embodiment, the semiconductor substrate 301 on which the probe wafer 300 is formed has a device 380 previously formed on the surface. The device 380 is insulated from other devices, wirings, pads, and the like by an insulating layer 370 formed on the surface of the semiconductor substrate 301 around the device 380.
このような半導体基板301を用いてプローブウエハ300を製造する場合は、図8(A)に示すように、まず、ビアホール330を形成する領域を含み、当該領域よりも広い領域に、保護材料により形成された保護層390が形成される。保護層390は、絶縁層370を厚さ方向に貫通して形成される。
When the probe wafer 300 is manufactured using such a semiconductor substrate 301, as shown in FIG. 8A, first, a region including the via hole 330 is formed, and a region wider than the region is made of a protective material. The formed protective layer 390 is formed. The protective layer 390 is formed through the insulating layer 370 in the thickness direction.
このように、プローブウエハ300の製造方法は、ビアホール330が形成される領域および絶縁層370の間を遮断する保護層390を形成する保護層形成段階を含んでもよい。これにより、液体の浸潤し易い多孔質の絶縁材料を用いて絶縁層370を形成することができる。従って、半導体基板301の寄生容量を低減して、信号品質を高く保つことができる。
As described above, the method for manufacturing the probe wafer 300 may include a protective layer forming step of forming the protective layer 390 that blocks between the region where the via hole 330 is formed and the insulating layer 370. Thus, the insulating layer 370 can be formed using a porous insulating material that easily infiltrates liquid. Therefore, the parasitic capacitance of the semiconductor substrate 301 can be reduced and the signal quality can be kept high.
続いて、図8(B)に示すように、保護層390の形成された領域に、貫通孔332が形成される。このとき、貫通孔332の周囲には保護層390が残る。これにより、貫通孔332は保護層390により包囲される。従って、貫通孔332の内面には、絶縁層370が露出されない。
Subsequently, as shown in FIG. 8B, a through hole 332 is formed in the region where the protective layer 390 is formed. At this time, the protective layer 390 remains around the through hole 332. Thereby, the through hole 332 is surrounded by the protective layer 390. Therefore, the insulating layer 370 is not exposed on the inner surface of the through hole 332.
保護層形成段階は、ビアホール330が形成される領域を包囲して保護層390を形成する手順を含んでもよい。更に、プローブウエハ300の製造方法において、保護層390により包囲された領域にレーザを照射して絶縁層370および半導体基板301を穿孔する手順を含むビアホール形成段階を備えてもよい。これにより、保護層390に包囲されたビアホール330を確実に形成できる。
The protective layer forming step may include a procedure of forming a protective layer 390 surrounding a region where the via hole 330 is formed. Furthermore, the method for manufacturing the probe wafer 300 may include a via hole forming step including a step of piercing the insulating layer 370 and the semiconductor substrate 301 by irradiating a region surrounded by the protective layer 390 with a laser. Thereby, the via hole 330 surrounded by the protective layer 390 can be reliably formed.
次に、図8(C)に示すように、貫通孔332の内部に導体材料を充填して、ビアホール330が形成される。この段階において、ビアホール330のプラグを、例えば、メッキ法による金属材料により形成した場合も、貫通孔332の内面は保護層390により被覆されているので、絶縁層370が湿潤環境に接触することがない。
Next, as shown in FIG. 8C, the via hole 330 is formed by filling the through hole 332 with a conductive material. At this stage, even when the plug of the via hole 330 is formed of, for example, a metal material by plating, the inner surface of the through-hole 332 is covered with the protective layer 390, so that the insulating layer 370 may come into contact with a wet environment. Absent.
このように、絶縁層370は、空孔を含む低誘電材料により形成されてもよい。これにより、多くは多孔質で液体が浸潤し易いので、メッキ法等の湿潤環境に適さないといわれる多孔質低誘電体材料を用いてプローブウエハ300を形成できる。
As described above, the insulating layer 370 may be formed of a low dielectric material including holes. As a result, the probe wafer 300 can be formed using a porous low-dielectric material, which is said to be unsuitable for a wet environment such as a plating method, since many are porous and easily infiltrated with liquid.
換言すれば、上記保護層形成段階は、絶縁層370を液体に触れさせる処理に先立って実行されることが好ましい。これにより、保護層390が形成された後は、液体に触れる処理を任意に実行できる。
In other words, it is preferable that the protective layer forming step be performed prior to the process of bringing the insulating layer 370 into contact with the liquid. Thereby, after the protective layer 390 is formed, the process which touches a liquid can be performed arbitrarily.
以下、図8(D)に示すように、また、図5(C)および図5(D)に示した場合と同様に、半導体基板301の裏面に、配線340および接続パッド350が形成される。また、要求に応じて、半導体基板301表面のデバイス380を接続パッド320等に接続する表面側の配線382を付加的に形成してもよい。
Thereafter, as shown in FIG. 8D, and in the same manner as shown in FIGS. 5C and 5D, the wiring 340 and the connection pads 350 are formed on the back surface of the semiconductor substrate 301. . Further, according to requirements, a surface-side wiring 382 for connecting the device 380 on the surface of the semiconductor substrate 301 to the connection pad 320 or the like may be additionally formed.
このように、保護層形成段階は、半導体基板301の表面に対して垂直な方向について、絶縁層370を貫通して保護層390を形成する手順を含んでもよい。これにより、ビアホール330およびデバイス380の間を、保護層390により確実に遮断して、デバイス380の短絡等を確実に防止できる。
Thus, the protective layer forming step may include a procedure of forming the protective layer 390 through the insulating layer 370 in a direction perpendicular to the surface of the semiconductor substrate 301. Thereby, between the via hole 330 and the device 380 can be surely blocked by the protective layer 390, and the short circuit of the device 380 can be reliably prevented.
このように、半導体基板301においてビアホール330から離間した位置に配されたデバイス380を形成する素子形成段階と、ビアホール330およびデバイス380の間を絶縁する絶縁層370の透湿性よりも低い透湿性を有して、ビアホール330が形成される領域、および、デバイス380が形成される領域の間に配された保護層390を、ビアホール形成段階に先立って形成する保護層形成段階を更に含んでもよい。これにより、ビアホール330の内面に、絶縁層370の空孔が連通することがなくなり、液体に触れさせる処理をした場合に、絶縁層370に液体が浸潤して絶縁不良を起こすことが防止される。
As described above, the element formation stage for forming the device 380 disposed at a position separated from the via hole 330 in the semiconductor substrate 301 and the moisture permeability lower than the moisture permeability of the insulating layer 370 that insulates between the via hole 330 and the device 380. And a protective layer forming step of forming a protective layer 390 disposed between the region where the via hole 330 is formed and the region where the device 380 is formed prior to the via hole forming step. As a result, the holes of the insulating layer 370 do not communicate with the inner surface of the via hole 330, and it is prevented that the liquid is infiltrated into the insulating layer 370 and causes insulation failure when the liquid is in contact with the liquid. .
なお、実施の形態を参照して説明したが、本発明の技術的範囲は上記実施の形態に記載の範囲には限定されない。上記実施の形態に、多様な変更または改良を加え得ることが当業者に明らかである。また、その様な変更または改良を加えた形態も本発明の技術的範囲に含まれ得ることは、請求の範囲の記載から明らかである。
In addition, although demonstrated with reference to embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. In addition, it is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.
例えば、プローブウエハ300は、被試験デバイスに対する電気的接続を形成するプローブ装置の一例であり、プローブ装置はウエハ状でない基板に形成されてもよい。例えばプローブ装置は、1または複数のダイ210と対応して配置される、ダイ状の基板に形成されてよい。この場合、プローブ装置は、図1から図8(D)に関連して説明したプローブウエハ300を、ダイ形状に分割することで製造できる。
For example, the probe wafer 300 is an example of a probe apparatus that forms an electrical connection to a device under test, and the probe apparatus may be formed on a substrate that is not in the form of a wafer. For example, the probe device may be formed on a die-shaped substrate that is arranged corresponding to one or more dies 210. In this case, the probe apparatus can be manufactured by dividing the probe wafer 300 described with reference to FIGS. 1 to 8D into a die shape.
例えば、プローブ装置は、一つの試験対象のダイ210と略同一の大きさに形成されてよい。また、プローブ装置の一つのダイと、一つの試験対象のダイ210とを接続した状態で、これらのダイをフィルム等によりパッケージしてもよい。
For example, the probe device may be formed to have substantially the same size as one test target die 210. Alternatively, these dies may be packaged with a film or the like in a state where one die of the probe apparatus and one die 210 to be tested are connected.
また、半導体基板301は、試験用基板の一例であり、試験用基板として半導体でない基板を用いてもよい。例えば試験用基板は、セラミック基板であってよい。また、プローブ装置の基板には、被試験デバイス200の試験に用いるドライバ等のデバイスが形成されてよく、また、形成されていなくともよい。
The semiconductor substrate 301 is an example of a test substrate, and a substrate that is not a semiconductor may be used as the test substrate. For example, the test substrate may be a ceramic substrate. Also, a device such as a driver used for testing the device under test 200 may or may not be formed on the substrate of the probe apparatus.
また、図1から図8(D)においては、プローブ装置の基板において、被試験デバイス200に接続される面において接続パッド350および配線340を形成する例を説明した。他の例では、プローブ装置の基板において、被試験デバイス200と接続される面の逆側の面に、接続パッド350および配線340を形成してもよい。この場合、接続パッド350は、試験装置側の接続端子の配置に応じて形成される。例えば接続パッド350は、チャック121における接続端子の配置に応じて形成されてよい。
1 to 8D, an example in which the connection pad 350 and the wiring 340 are formed on the surface connected to the device under test 200 on the substrate of the probe apparatus has been described. In another example, the connection pad 350 and the wiring 340 may be formed on the surface opposite to the surface connected to the device under test 200 in the substrate of the probe apparatus. In this case, the connection pad 350 is formed according to the arrangement of the connection terminals on the test apparatus side. For example, the connection pad 350 may be formed according to the arrangement of the connection terminals in the chuck 121.
請求の範囲、明細書、および図面中において示した装置、システム、プログラム、および方法における動作、手順、ステップ、および段階等の各処理の実行順序は、特段「より前に」、「先立って」等と明示しておらず、また、前の処理の出力を後の処理で用いるのでない限り、任意の順序で実現しうることに留意すべきである。請求の範囲、明細書、および図面中の動作フローに関して、便宜上「まず、」、「次に、」等を用いて説明したとしても、この順で実施することが必須であることを意味するものではない。
The execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior”. It should be noted that they can be implemented in any order unless the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for the sake of convenience, it means that it is essential to carry out in this order. is not.
100 試験装置、110 テストヘッド、111、121 チャック、112、122、132、401 筐体、113、123、480 ケーブル、114、124、134 ピンエレクトロニクス、116、118、126、128、136 コネクタ、119 マザーボード、120 パフォーマンスボード、129 内部回路、130 プローバ、200 被試験デバイス、210 ダイ、220、320、350 接続パッド、300 プローブウエハ、301 基板、310 境界、330 ビアホール、332 貫通孔、340、382 配線、360 溝、370 絶縁層、380 デバイス、390 保護層、400 描線装置、410 画像処理装置、420 画像表示装置、430 支持装置、432 Xステージ、434 Yステージ、436 回転ステージ、438 モータ、440 参照光源、450 撮像装置、460 描線部、462 アクチュエータ、464 吐出ヘッド、470 基板保持装置
100 test apparatus, 110 test head, 111, 121 chuck, 112, 122, 132, 401 housing, 113, 123, 480 cable, 114, 124, 134 pin electronics, 116, 118, 126, 128, 136 connector, 119 Motherboard, 120 performance board, 129 internal circuit, 130 prober, 200 device under test, 210 die, 220, 320, 350 connection pad, 300 probe wafer, 301 substrate, 310 boundary, 330 via hole, 332 through hole, 340, 382 wiring 360 groove, 370 insulating layer, 380 device, 390 protective layer, 400 line drawing device, 410 image processing device, 420 image display device, 430 support device, 432 X stage 434 Y stage, 436 rotating stage, 438 motor, 440 reference-light source, 450 an imaging device, 460 drawn line portion, 462 actuator, 464 ejection head, 470 a substrate holder
Claims (12)
- 被試験デバイスに対する電気的接続を形成するプローブ装置を製造するプローブ装置製造方法であって、
試験用基板に、前記試験用基板の表面および裏面の間を貫通するビアホールを形成するビアホール形成段階と、
前記ビアホールの前記表面の側の端部に接続された表面側接続パッドを、前記試験用基板の表面に形成する表面側接続パッド形成段階と、
前記試験用基板の裏面に向かって液滴状の導電材料を吐出して付着させることにより、裏面側接続パッドと、前記ビアホールの裏面側端部および前記裏面側接続パッドを電気的に接続する裏面側配線とを形成する裏面側導体パターン形成段階と
を含むプローブ装置製造方法。 A probe device manufacturing method for manufacturing a probe device that forms an electrical connection to a device under test,
A via hole forming step for forming a via hole penetrating between the front surface and the back surface of the test substrate on the test substrate;
A surface-side connection pad forming step for forming a surface-side connection pad connected to an end of the via hole on the surface side, on the surface of the test substrate;
A back surface side connection pad, a back surface side end portion of the via hole, and the back surface side connection pad are electrically connected by ejecting and attaching a droplet-shaped conductive material toward the back surface of the test substrate. And a back side conductor pattern forming step of forming a side wiring. - 前記裏面側導体パターン形成段階において、前記裏面側接続パッドを、前記被試験デバイスの接続パッドに対応した位置に形成する
請求項1に記載のプローブ装置製造方法。 The probe apparatus manufacturing method according to claim 1, wherein, in the back surface side conductor pattern forming step, the back surface side connection pad is formed at a position corresponding to the connection pad of the device under test. - 前記ビアホール形成段階および前記表面側接続パッド形成段階の少なくとも一方は、所与の遮光パターンを有するマスクを用いたマスクプロセスを含む請求項2に記載のプローブ装置製造方法。 3. The probe device manufacturing method according to claim 2, wherein at least one of the via hole forming step and the surface side connection pad forming step includes a mask process using a mask having a given light shielding pattern.
- 前記表面側接続パッド形成段階は、前記試験用基板の前記裏面に向かって液滴状の導電材料を吐出して付着させる手順を含む請求項3に記載のプローブ装置製造方法。 4. The probe device manufacturing method according to claim 3, wherein the front surface side connection pad forming step includes a procedure of discharging and attaching a droplet-shaped conductive material toward the back surface of the test substrate.
- 前記裏面側導体パターン形成段階に先立って、前記裏面側配線が形成される領域において、前記試験用基板に溝を形成する溝形成段階を更に含む請求項4に記載のプローブ装置製造方法。 5. The probe device manufacturing method according to claim 4, further comprising a groove forming step of forming a groove in the test substrate in a region where the back surface side wiring is formed prior to the back surface side conductor pattern forming step.
- 前記試験用基板において前記ビアホールから離間した位置に配された試験用素子を形成する素子形成段階と、
前記ビアホールおよび前記試験用素子の間を絶縁する絶縁層の透湿性よりも低い透湿性を有し、前記ビアホールが形成される領域、および、前記試験用素子が形成される領域の間に配された保護層を、前記ビアホール形成段階に先立って形成する保護層形成段階を更に含む請求項1に記載のプローブ装置製造方法。 Forming an element for forming a test element disposed at a position spaced apart from the via hole in the test substrate;
The moisture permeability is lower than the moisture permeability of the insulating layer that insulates between the via hole and the test element, and is disposed between the region where the via hole is formed and the region where the test element is formed. The probe device manufacturing method according to claim 1, further comprising a protective layer forming step of forming a protective layer prior to the via hole forming step. - 前記保護層形成段階は、前記ビアホールが形成される領域および前記絶縁層の間を遮断する前記保護層を形成する手順を含む請求項6に記載のプローブ装置製造方法。 The method for manufacturing a probe device according to claim 6, wherein the protective layer forming step includes a step of forming the protective layer that blocks a region between the via hole and the insulating layer.
- 前記保護層形成段階は、前記ビアホールが形成される領域を包囲して前記保護層を形成する手順を含む請求項7に記載のプローブ装置製造方法。 The probe device manufacturing method according to claim 7, wherein the protective layer forming step includes a procedure of forming the protective layer by surrounding a region where the via hole is formed.
- 前記保護層形成段階は、前記試験用基板の表面に対して垂直な方向について、前記絶縁層を貫通して前記保護層を形成する手順を含む請求項8に記載のプローブ装置製造方法。 9. The probe device manufacturing method according to claim 8, wherein the protective layer forming step includes a procedure of forming the protective layer through the insulating layer in a direction perpendicular to the surface of the test substrate.
- 前記絶縁層は、空孔を含む低誘電材料により形成される請求項9に記載のプローブ装置製造方法。 10. The probe device manufacturing method according to claim 9, wherein the insulating layer is formed of a low dielectric material including holes.
- 前記保護層形成段階は、前記絶縁層を液体に触れさせる処理に先立って実行される請求項10に記載のプローブ装置製造方法。 The probe device manufacturing method according to claim 10, wherein the protective layer forming step is performed prior to a process of bringing the insulating layer into contact with a liquid.
- 前記ビアホール形成段階は、前記保護層により包囲された領域にレーザを照射して前記絶縁層および前記試験用基板を穿孔する段階を含む請求項11に記載のプローブ装置製造方法。 12. The probe device manufacturing method according to claim 11, wherein the via hole forming step includes a step of piercing the insulating layer and the test substrate by irradiating a region surrounded by the protective layer with a laser.
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TW098118192A TWI393201B (en) | 2008-06-02 | 2009-06-02 | Fabrication method of probe apparatus |
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JP2011149938A (en) * | 2010-01-22 | 2011-08-04 | Kodi-S Co Ltd | Film type probe unit, and method of manufacturing the same |
US10229877B2 (en) | 2016-06-22 | 2019-03-12 | Nanya Technology Corporation | Semiconductor chip and multi-chip package using thereof |
US10761146B2 (en) | 2017-05-29 | 2020-09-01 | Samsung Electronics Co., Ltd. | Wafer probe card for evaluating micro light emitting diodes, analysis apparatus including the same, and method of fabricating the wafer probe card |
KR102452488B1 (en) * | 2017-05-29 | 2022-10-11 | 삼성전자주식회사 | Wafer probe card and analysis apparatus thereof and method for fabricating the wafer probe card |
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