JPS6379350A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6379350A JPS6379350A JP22357586A JP22357586A JPS6379350A JP S6379350 A JPS6379350 A JP S6379350A JP 22357586 A JP22357586 A JP 22357586A JP 22357586 A JP22357586 A JP 22357586A JP S6379350 A JPS6379350 A JP S6379350A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- base
- wiring
- gnd
- interconnection layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000010410 layer Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 7
- 239000000919 ceramic Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000000452 restraining effect Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、％Ｋ、当該装置における高
速化、ノイズの低減および線間容量の低減技術に関する
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and relates to techniques for increasing the speed, reducing noise, and reducing line capacitance in the device.
半導体集積回路の高速化に対して、該回路装置のパッケ
ージにおいてもその配線距離を短（するなど高速化が要
求される。As the speed of semiconductor integrated circuits increases, the package of the circuit device is also required to increase its speed by shortening the wiring distance.
従来、多層配線構造を有するセラミック基板（パッケー
ジベース）上に、半導体チップを搭載し、該チップと当
該ベース上に形成された表層配線とをボンディングワイ
ヤにより接続し、該表層配線と外部接続端子（リードビ
ン）とを内部配線により接続したセラミックパッケージ
において、表層配線に対する線間容量を低減し、パッケ
ージの信号の入出力を高速化するために、当該衣屑配線
の下部であって、ベース内部に、グランド層を布設した
ものがある。Conventionally, a semiconductor chip is mounted on a ceramic substrate (package base) having a multilayer wiring structure, and the chip and the surface wiring formed on the base are connected by bonding wires, and the surface wiring and external connection terminals ( In a ceramic package that is connected to a lead bin (lead bin) by internal wiring, in order to reduce the line capacitance with respect to the surface wiring and speed up the input/output of signals to the package, there is a Some have a ground layer installed.
なお、かかる回路技術について述べた文献の例としては
、１９８０年１月１５日（株）工業調立会発行ｒＩＣ化
実装技術Ｊ Ｐ１６０〜１７５があげられる。An example of a document describing such circuit technology is rIC Mounting Technology JP 160-175, published by Kogyo Chorikai Co., Ltd. on January 15, 1980.
しかしながら、上記のように、なメ関容誼低浅のために
表層配線の下部にグランド（ＧＮＤ）層を設けた構造の
ものでは、このグランド層の布設により、パッケージベ
ースにソリ（反り）が発生し易いという難点がある。However, as mentioned above, in the case of a structure in which a ground (GND) layer is provided below the surface wiring in order to reduce the thickness of various connections, the installation of this ground layer may cause warping of the package base. The problem is that it is easy to occur.
本発明はかかるソリの発生を防止する技術を提供するこ
とを目的とする。An object of the present invention is to provide a technique for preventing the occurrence of such warpage.
本発明の前記ならびＫそのほかの目的と新規な特徴は、
本明ｍ書の記述および絡付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention are:
This will become clear from the description in this document and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
本発明では表層配線に対するグランド層に加えて、内層
配線に対するグランド層をも布設した。In the present invention, in addition to the ground layer for the surface layer wiring, a ground layer for the inner layer wiring is also provided.
このように、内層配役に対するグランド層をも布設する
ことＫより、パッケージベースのソリが低減し、さらに
、線間容量の低減が促進され、がっ、これらグランド層
により外部ノイズがシールドされるという利点をも有す
ることができた。In this way, by also providing a ground layer for the inner layer, warpage of the package base is reduced, furthermore, line capacitance is reduced, and external noise is shielded by these ground layers. It could also have advantages.
次に、本発明を、図面に示す実施例に基づいて説明する
。Next, the present invention will be explained based on embodiments shown in the drawings.
第１図は本発明の実施例を示す要部断面図、第２図は本
発明の実施例を示すビングリッドアレイタイプのセラミ
ックパッケージの全体構成断面図である。FIG. 1 is a cross-sectional view of a main part showing an embodiment of the present invention, and FIG. 2 is a cross-sectional view of the overall configuration of a bin grid array type ceramic package showing an embodiment of the present invention.
第１図に示すように、ベース１の表面には表層配線２が
布設されている。As shown in FIG. 1, surface wiring 2 is laid on the surface of the base 1.
該表層配線２の下部であって、ベース１の内部にＧＮＤ
層３が布設され【いる。A GND is connected to the bottom of the surface wiring 2 and inside the base 1.
Layer 3 has been installed.
ベースｌの底面から垂直方向にリードビン４が複数引き
出しされており、ベース１内部には、表層配線２と該リ
ードビン４とを接続している内部配線（内層配線）５が
形成されている。該内部配線５は、表層配線２から垂下
した配線部５ａと該配線部から直角方向に、かつ、ＧＮ
ＤＪｉ＊３と平行に布設された配線部５ｂと該配＃ｉ１
部の端部とＩＪ−ドビン４の上部とを接続している配線
部５ｃとから成る。A plurality of lead bins 4 are drawn out in the vertical direction from the bottom surface of the base 1, and internal wiring (inner layer wiring) 5 is formed inside the base 1 to connect the surface wiring 2 and the lead bins 4. The internal wiring 5 is connected to a wiring part 5a hanging down from the surface wiring 2 and in a direction perpendicular to the wiring part, and is connected to the GN
The wiring section 5b laid parallel to DJi*3 and the wiring #i1
The wiring part 5c connects the end of the IJ-dobin 4 to the upper part of the IJ-dobin 4.
ベース１の底面側に、ＧＮＤ層３と平行に、内部配線５
に対するＧＮＤ層６を布設する。Internal wiring 5 is placed on the bottom side of the base 1 in parallel with the GND layer 3.
A GND layer 6 is laid for the ground.
こねらＧＮＤＪ＠３．６は、ベース１を横切る中心線７
に対し上下対称位置に布設されており、バランスがとら
れている。Konera GNDJ@3.6 is the center line 7 that crosses the base 1
The cables are laid in vertically symmetrical positions to ensure balance.
これら表層配線２や内部配線５やＧＮＤ層３．６の形成
は、従来公知の？８膜形成技術や厚膜形成技術により行
なうことができる。The formation of these surface wirings 2, internal wirings 5, and GND layers 3.6 is performed using conventional methods known in the art. This can be performed using an 8-film formation technique or a thick-film formation technique.
表層配線２は、例えば、アルミニウム（Ａりを蒸着する
ことにより形成することができる。The surface layer wiring 2 can be formed, for example, by vapor depositing aluminum (A).
ＧＮＤ層３．６は、例えば、タングステン（Ｗ）導体な
厚膜形成技術を用いて敷設することにより形成できる。The GND layer 3.6 can be formed, for example, by using a tungsten (W) conductor thick film formation technique.
これらＧＮＤＩｍ３．６を布設して成る多層構造のベー
ス１の内部配線５は、スルーホールメッキ技術による配
線部５ａ、５ｃの形成や、焼結アルミナグリーンシート
上にＷ、Ｍｏなどの導体ペーストを印刷、積ＡＪＬ、て
行う配線ｇ５ｂの形成などＫより、接続導体として形成
される。The internal wiring 5 of the base 1 with a multilayer structure formed by laying these GNDIm3.6 is formed by forming the wiring parts 5a and 5c by through-hole plating technology, or by printing a conductive paste such as W or Mo on a sintered alumina green sheet. , product AJL, etc., and is formed as a connection conductor by forming the wiring g5b.
第１図や第２図に示すように、ベース１上に半導体素子
８を、例えば人ｕ−８ｉ合金共晶法により固着し、該素
子８のポンディングパッド部（図示せず）と表層配線２
とをボンディングワイヤ９によりワイヤボンディングす
る。As shown in FIGS. 1 and 2, a semiconductor element 8 is fixed onto a base 1 by, for example, a U-8I alloy eutectic method, and a bonding pad portion (not shown) of the element 8 and a surface wiring 2
are wire-bonded using a bonding wire 9.
このワイヤボンディングにより、半導体素子８内の内部
配線は、ボンディングワイヤ９、表層配線２、次いで、
内部配！Ｂ５を経由して、リードビン（外部接続端子）
４と導通し、ＭＸ素子８への信号の入出力が行われる。Through this wire bonding, the internal wiring within the semiconductor element 8 is connected to the bonding wire 9, the surface wiring 2, and then the internal wiring within the semiconductor element 8.
Internal arrangement! Lead bin (external connection terminal) via B5
4, and input/output of signals to the MX element 8 is performed.
半導体素子（チップ）８は、例えはシリコン単結晶基板
から成り、周知の技術によってこのチップ内には多数の
回路素子が形成され、１つの回路機能が与えられている
。回路素子の具体例は、例えばＭＯＳトランジスタから
成り、これらの回路素子によって、例えば論理回路およ
びメモリの回路機能が形成されている。The semiconductor element (chip) 8 is made of, for example, a silicon single crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A specific example of the circuit element is, for example, a MOS transistor, and these circuit elements form the circuit functions of, for example, a logic circuit and a memory.
ベース１上には、ガラス材料を制止材料ＩＯとして、キ
ャップ１１を取着する。A cap 11 is attached onto the base 1 using a glass material as a restraining material IO.
キャップ１１も、ベース１と同様にセラミック材により
構成される。Like the base 1, the cap 11 is also made of ceramic material.
本発明では、ベース１を横切る中心線７に対して上下対
称位置に、表層配線２に対するＧＮＤＲ３を設けるとと
もに、内部配線５に対するＧＮＤｌｌ ６を設けるよう
にしたので、パッケージ内部において中心線７を境にし
て上下対称構造となり、パッケージベース１の上方向へ
のソリが防止され、パッケージ全体がノリ難くなるとと
もに、パッケージベース１の上面（表面）からの外部ノ
イズはＧＮＤＪ置３装よりシールドされるとともにベー
ス１底面側からの外部ノイズはＧＮＤＪｔ！６によりシ
ールドされ、また、内部配線５はこれらＧＮＤＮＳＯ２
により挾まれる形になるので外部からのノイズを受は難
くなる。In the present invention, the GNDR 3 for the surface wiring 2 is provided at vertically symmetrical positions with respect to the centerline 7 that crosses the base 1, and the GNDll 6 for the internal wiring 5 is provided. This creates a vertically symmetrical structure, which prevents the package base 1 from warping upward, making the entire package difficult to glue, and shielding external noise from the top (surface) of the package base 1 from the 3 GNDJ devices. 1 External noise from the bottom side is GNDJt! 6, and the internal wiring 5 is shielded by these GNDNSO2
Since it is sandwiched between the two, it is difficult to receive noise from the outside.
また、ＧＮＤＮＳＯ２在忙より、線間容量が低減される
のに加えて、さらに、ＧＮＤＪ４６を設けたので、より
一層、線間容量が低減され、半導体素子８の高速化に対
応したセラミックパッケージの高速化に寄与する点大で
ある。In addition to the line capacitance being reduced compared to GNDNSO2, the provision of GNDJ46 further reduces the line capacitance, making it possible to achieve high speed ceramic packages that are compatible with the high speeds of semiconductor elements 8. This is a major contribution to the development of
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるビングリッドプレイ
タイプのセラミックパッケージに適用した場合について
説明したが、それに限定されるものではなく、各種の半
導体装置に適用できる。In the above explanation, the invention made by the present inventor was mainly applied to a bin lid play type ceramic package, which is the background field of application. Applicable to
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとうりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
本発明によれば、パッケージのソリが防止され、外部ノ
イズに対し強くなり、かつ、低線間容せの促進を図るこ
とができ、半導体素子の高速化に対応した高速板パッケ
ージを実現することができた。According to the present invention, it is possible to realize a high-speed board package that can prevent warping of the package, be strong against external noise, and promote low line spacing, and that is compatible with the increasing speed of semiconductor devices. was completed.
第１図は本発明の実施例を示す要部断面図、第２図は本
発明の実施例を示す半導体装置の構成断面図である。
１・・・ベース、２・・・表層配線、３・・・表層配線
に対するグランド層、４・・・外部接続端子（リードビ
ン）、５・・・内部配線（内層配線）、６・・・内部配
線に対するグランド層、７・・・中心線、８・・・半導
体素子、９・・・ボンディングワイヤ、１０・・・封止
材料、１１・・・キャップ。
Ｘ、、−・′
第 １ 図
第 ２１ａFIG. 1 is a sectional view of a main part showing an embodiment of the invention, and FIG. 2 is a sectional view of a structure of a semiconductor device showing an embodiment of the invention. 1... Base, 2... Surface wiring, 3... Ground layer for surface wiring, 4... External connection terminal (lead bin), 5... Internal wiring (inner layer wiring), 6... Internal Ground layer for wiring, 7... Center line, 8... Semiconductor element, 9... Bonding wire, 10... Sealing material, 11... Cap. X,,-・' Figure 1, Figure 21a
Claims (1)
層を当該パッケージベース内部に形成するとともに、前
記表層配線と外部接続端子とを接続している内部配線に
対するグランド層を当該パッケージベース内部に形成し
て成ることを特徴とする半導体装置。 ２、特許請求の範囲第１項記載の半導体装置において、
パッケージベースを横切る中心線に対して上下対称位置
にそれぞれグランド層を形成して成る、特許請求の範囲
第１項記載の半導体装置。[Claims] 1. A ground layer for surface wiring on the surface of the package base is formed inside the package base, and a ground layer for internal wiring connecting the surface wiring and external connection terminals is formed inside the package base. A semiconductor device characterized by being formed in. 2. In the semiconductor device according to claim 1,
2. The semiconductor device according to claim 1, wherein ground layers are formed at vertically symmetrical positions with respect to a center line that crosses the package base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22357586A JPS6379350A (en) | 1986-09-24 | 1986-09-24 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22357586A JPS6379350A (en) | 1986-09-24 | 1986-09-24 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6379350A true JPS6379350A (en) | 1988-04-09 |
Family
ID=16800311
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22357586A Pending JPS6379350A (en) | 1986-09-24 | 1986-09-24 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6379350A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005175097A (en) * | 2003-12-10 | 2005-06-30 | Kyocera Corp | Wiring board |
| WO2012128271A1 (en) * | 2011-03-24 | 2012-09-27 | 株式会社村田製作所 | High frequency module |
| WO2023054374A1 (en) * | 2021-09-29 | 2023-04-06 | 株式会社村田製作所 | Tracker module and communication device |
-
1986
- 1986-09-24 JP JP22357586A patent/JPS6379350A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005175097A (en) * | 2003-12-10 | 2005-06-30 | Kyocera Corp | Wiring board |
| JP4508620B2 (en) * | 2003-12-10 | 2010-07-21 | 京セラ株式会社 | Wiring board |
| WO2012128271A1 (en) * | 2011-03-24 | 2012-09-27 | 株式会社村田製作所 | High frequency module |
| CN103430457A (en) * | 2011-03-24 | 2013-12-04 | 株式会社村田制作所 | High frequency module |
| JP5655937B2 (en) * | 2011-03-24 | 2015-01-21 | 株式会社村田製作所 | High frequency module |
| CN103430457B (en) * | 2011-03-24 | 2015-05-13 | 株式会社村田制作所 | High frequency module |
| US9300019B2 (en) | 2011-03-24 | 2016-03-29 | Murata Manufacturing Co., Ltd. | High-frequency module |
| WO2023054374A1 (en) * | 2021-09-29 | 2023-04-06 | 株式会社村田製作所 | Tracker module and communication device |
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