JPS63308656A - Block access system for changeable access cycle - Google Patents

Abstract

PURPOSE:To increase the flexibility of a system by changing over an access cycle at the time of block access execution depending on the type of response signal returned from a bus slave. CONSTITUTION:The CPU of a bus master side reads necessary data from an external memory M of the bus slave side, when the necessary data are not found in a cache memory C. For this purpose, a control circuit A transmits a block access request signal BLOCK to the bus slave. A control circuit B to receive such a signal returns a response signal BLOCKF or BLOCKS respectively to the bus master side depending on an block access executed whether by a high speed transfer system or by a low speed transfer system. The control circuit A to receive this, transfers a data memory from the external memory M to a memory C by changing over an access cycle depending on the type of response signal. Thus, a different memory in an access time can be freely used and the flexibility of the system can be increased.

Description

[Detailed Description of the Invention] [Summary] A means for providing a block access request signal from a bus master to a bus slave so as to transfer a plurality of consecutive data to a single address output in a single bus cycle. , a means for starting block access in response to a start data transfer end signal indicating the end of the start data transfer from the bus slave and a response signal to the block access request signal; and means for performing a block-in operation to store data in a cache memory, and an access cycle during block access execution is switched depending on the type of a response signal to the block access request signal, the access cycle being switched when executing the block access, the type of the response signal being Since it is possible to decide whether to access the block at high speed or low speed, for example, external memories with different access times can be used freely, increasing the flexibility of the system.

[Industrial application field]

The present invention relates to a block access method, and in particular, to a method for transferring a plurality of consecutive data from a bus slave side (for example, an external memory side) to a bus master side (CPU side) in response to a single address output in one bus cycle. Regarding block access method.

[Conventional technology]

Generally, on the bus master side including a CPU, for example, in a microprocessor, a cache memory is placed near the CPU, and part of the data that the CPU needs for the time being is stored in the cache memory. Necessary data is read from external memory only when the data is not present on the cache memory.

At this time, the data is transferred to the cache memory at once in blocks of a certain size on the external memory (the required data and multiple peripheral data that exist contiguously together). A block-in operation is performed to store. In this case, the data to be transferred is on consecutive addresses within the block on the external memory, so 1
Data transfer is performed by a block access operation that transfers a plurality of consecutive data to a single address output in one bus cycle.

By the way, in the conventional technology, the CPU side system determines the execution of this block access transfer operation.
And it is executed only in the execution cycle determined by the system.

Therefore, when connecting memories with different access times, the speed of the system's execution cycle must be adjusted to the memory with the slowest access speed (if the speed of the execution cycle performed by the system is adjusted to the memory with the slowest access speed, it is necessary to ), the problem was that the performance of the entire system deteriorated.

[Problem that the invention seeks to solve]

The present invention was made to solve this problem, and depending on the type of response signal returned from the bus slave side in response to a block access request from the bus master side, the block access is executed at high speed or at low speed. By having the bus master decide whether to
This increases the flexibility of the system.

[Means for solving problems]

In order to solve the above problems, in the present invention, a block access request signal is sent from a bus master to a bus slave so that a plurality of consecutive data can be transferred to a single address output in a single bus cycle. means for starting block access in response to a start data transfer end signal indicating the end of the start data transfer from the bus slave and a response signal to the block access request signal; A block access method is provided, which has means for performing a block-in operation to store blocks in a cache memory in units of blocks, and an access cycle during block access execution is switched depending on the type of response signal to the block access request signal. .

[For production]

According to the above configuration, the access cycle of the block access executed by the bus master is switched depending on the type of the response signal sent back from the bus slave. As a result, for example, a memory with a slow access speed is accessed with a block that can insert a wait cycle, and a memory with a fast access speed is accessed with a block that allows high-speed transfer.

〔Example〕

FIG. 1 schematically shows the overall configuration for executing the block access operation according to the present invention. In addition to the CPU and cache memory C, the microprocessor on the bus master side also has a CPU and a cache memory C. A control circuit A is provided for executing the block access operation, while a control circuit B for executing the block access operation is provided in addition to the external memory M on the bus slave side.

FIG. 2 shows the internal configuration of each of the control circuits A and B. Control circuit A is composed of a bus control section, a block access request section E, a block access execution/judgment section F, and a launch circuit G. , On the other hand, the control circuit B is composed of a latch counter J, a decoder, and a block access clearance signal generation section.

As mentioned above, when the CPU on the bus master side does not have the required data in the cache memory C, the CPU on the bus master side reads the required data from the external memory M.
The U outputs an external access request signal and a read signal to the bus control section, and further sends out an address request signal for reading required data from the external memory.

In response to various signals output from the CPU, the bus control unit generates a memory address signal Ad for accessing a predetermined address of the external memory M on the bus slave side.
In response to the read request signal sent from the bus control unit to the block access request unit E, the block access request unit E sends a block access request signal to the bus slave side at the time of block access execution. Drunken face 1 is sent out.

On the bus slave side, in order to perform block access, the value of the address signal Address is latched by a latch counter J and sequentially counted up to generate addresses for one block. 1 generated by the latch counter
The address for the block is decoded by a decoder, and the decoded address signal is input to the external memory M, where predetermined data is read out, and is also supplied to the block access/acknowledge signal generation section. Furthermore, the block access request signal 1 from the bus master side is inputted to the block access/acknowledge signal generating section, and it is determined from this that the bus master side requests data transfer using the block access method. Here, the block access/acknowledge signal generation unit determines whether the address area to be accessed is an area that can be transferred using a high-speed transfer block access method according to the access time of the external memory allocated to the address area. or a region that can only be transferred using a low-speed transfer block access method, and returns a block access/acknowledge signal corresponding to the block access method to be executed to the bus master side. That is, if the address area to be accessed can be transferred using the high-speed block access method, a BLACKF signal is returned, and when the address area can be transferred using the low-speed block access method, a ■π correction is returned.

In other words, the block access/acknowledge signal generation unit determines whether or not to access the block according to the input of the block access request signal BLOCK, and furthermore, when executing the block access, accesses the block using a high-speed transfer method. response signal BLACKF or BL depending on whether the execution is executed using the low-speed transfer method.
Returns ACKS to the bus master side. Note that after the start of the block access, when the first data is transferred from the bus slave side (external memory) to the bus master side, the first data transfer end signal 11r is sent from the block access/acknowledge signal generation section to the bus master side. .

At this time, on the bus master side (block access execution determination unit F), the access signal (B
LACKF or BLACKS), selects the block access cycle to be executed depending on which one is received, transmits the selection result (high-speed mode or normal mode) to the bus controller, and The bus control section is
The latch circuit G is controlled to transfer data from the external memory M (one block of data including data required by the CPU) to the cache memory C by the selected block access cycle.

FIG. 3 is a timing diagram showing changes in various signals transmitted and received during block access execution between the respective control circuits shown in FIG. is not in the cache memory C, the bus master side outputs the memory address signal Address in which the data required is stored to the bus slave side, and then sends out the block access request signal BLO (J. (Block access/accuracy signal generation unit L) detects whether the bus master side is asserting the signal top 1. Then, when detecting the signal top 1,
When executing the block access, if the memory area to be accessed at that time is an area where high-speed transfer is possible, the bus slave side sends a block access acknowledge signal for high-speed transfer along with the start data transfer end signal DC. BLA (JF is returned. In this way, when the bus master side (block access execution determination section F) receives the signal BLACKF together with the start data transfer end signal ■, the data after the start data (the third
In the case of the figure, the following three pieces of data) are sequentially fetched into the bus master side in synchronization with a predetermined clock signal, regardless of each data transfer end signal. In other words, in this case, as shown in the left half of FIG.
CP at the timing marked with ○ attached to each data in the diagram.
Read into U.

On the other hand, when executing block access, if the access time of the memory area to be accessed at that time is slow and the above-mentioned high-speed transfer is not possible, the bus slave side sends the first data transfer end signal and the block for low-speed transfer. Returns the access/acknowledge signal BLACKS. In this way, when the bus master side receives the signal fi■ along with the first data transfer end signal, the data after the first data (in the case of FIG. 3, the following three data) is transferred to the third As shown in the right half of the figure, the data transfer end signal corresponding to each data is taken into the bus master side only when it is returned from the bus slave side. In other words, in this case, multiple pieces of data (four pieces of data in this case) are sequentially transferred to the bus master side through low-speed →lock access, and the CP is transferred at the timing marked with ○.
Read into U. When low-speed block access is executed in this way, each data is processed by inserting a wait cycle during the transfer cycle until the corresponding data transfer end signal is returned from the bus slave side. You will be forced to wait for the transfer. Therefore, data can be transferred sequentially even to a memory with a slow access speed while inserting a required wait cycle depending on the access time of the memory.

Specific circuit examples of each part constituting the control circuit A will be described below with reference to FIGS. 4 to 16.

First, FIG. 4 shows a specific example of the circuit of the block access request section E, and FIG. 5 is a timing diagram showing the operation of the circuit shown in FIG.

In FIG. 4, El and E are first and second stage flip-flops, Ex is a latch circuit, E4 to E are Nant gates, and φ. and φ2 are clock signals. (See FIGS. 5(a) and (b)). Here, the read request signal inputted from the CPU via the bus control unit causes the first stage flip-flop E to be inverted, as shown in FIG. 5(c). and (d)), the output signal Q of the flip-flop E is latched by the clock signal φ2 in the latch circuit E2. (see FIG. 5(e)), and the latch circuit E! output signal Q and clock signal φ. is input to the NAND circuit E4, the second stage flip-flop E is inverted with the output signal of the NAND circuit E4, and the output signal 10 is used as the block access request signal BLOCK. (See Figure 5(f)). Then, the first stage flip-flop E1 is reset by the output of the signal BLOCK via the Nant gate E6. Note that the block access request signal BLOCK is negated via the Nant gate ES when the block access ends (when the block access end signal BIEND becomes a low level) (see FIG. 5 (g>)), and similarly It is also negated via the Nant gate E when no block access is performed (when the block access cancel signal BLACAN goes low) and when the reset signal RESET goes low. While the block access request signal 1 is being output, the high speed block access or low speed block access shown in FIG. 3 is executed.

Next, FIG. 6 shows a specific circuit example of the block access execution determination section F, and FIG. 7 is a timing diagram showing the operation of the circuit shown in FIG.

In FIG. 6, Fl to F are data transfer end signals, respectively, a block access/acknowledge signal BLACKF for high-speed transfer, and a block access/acknowledge signal BLACKF for low-speed transfer.
This is a latch circuit into which the acknowledgment signal BLACKS is input, and each of the above signals ■τ is sent back from the bus slave side.
, BLACKP, and BLACKS respectively as clock signals φ. Latch with.

For example, as described above, when the block access/acknowledge signal BLACKF for high-speed transfer is returned from the bus slave side at the same time as the start data transfer end signal (refer to FIGS. 7(C) and (d)). The output signals of each latch circuit F+ and Fz are shown in FIG. 7(e) and (
f), and the high-speed mode request signal is output from the output side of the latch circuit F4 via the Nant gate F- (see FIG. 7(g)), while the start data transfer end signal If the block access signal BLACKS for low-speed transfer is returned at the same time as DC, the output signals of each latch circuit F+ and Fi, and the Nant gate F? A normal mode request signal is output from the output side of the latch circuit FS via the +inverter F1 and the Nandt gate F.

In addition, when the first data transfer end signal ■ is returned, if the block access/acknowledge signals 7 and m are not returned and remain at high level (the output sides of latch circuits F, , F remain at low level). (Figure 7 (h)
, (i).

(Refer to (j)) And gate F1゜ and Nand gate F
Block access cancellation signal BLAC via Il
AN becomes low level (see FIG. 7(k)), and block access is not performed. Furthermore, each time the data transfer end signal is returned, the output side of the launch circuit F becomes high level, and the high level signal DCL is supplied to the bus control section, etc. (see FIG. 8).

Next, FIG. 8 shows a specific circuit example of the bus control section, and FIGS. 9 and 10 show timing diagrams showing the operation of the circuit in FIG. 8 in high-speed mode and normal mode. It is a diagram.

That is, when a high-speed mode request signal is sent from the block access execution determination section F, the output side of the flip-flop D1 is set and inverted, as shown in FIG. 9(f).
(see (g))), a high-speed mode signal for performing high-speed mode block access is generated via the launch circuit (see Fig. 9 (h)), while a normal mode request signal is sent. At times, the output side of flip-flop D is set and inverted as shown in FIG. 10(e).

(see FIG. 10(f)), and a normal mode signal for performing normal mode (low speed mode) block access is generated via the latch circuit D4 (see FIG. 10(g)).

When high-speed mode block access is performed, the level of the 0 point in FIG. 8 changes via the AND gate DS as shown in FIG. 9(i) every time the clock signal φ3 is input, and the NOR gate D7 is Through this, the level of 0 point in Figure 8 becomes the 9th level.
It changes as shown in Figure (j) and is input to the counter D.

This 0 point or level change at 0 point is also synchronized with data transfer from the bus slave side (see Figure 9 (n)).
, the number of data transfers after the first data transfer is counted by the counter D8. When the counter D8 counts the specified number of data transfers (in this case, three subsequent data have been transferred), the level of the 0 point on the output side of the counter D becomes low level (FIG. 9(k)). , Or Gate Dl! A block access end signal n indicating the end of block access is outputted via (see FIG. 9).

Furthermore, the or gate D1□ and Nante gate fats (
The block access cancel signal ■■■ and the reset signal ■I are also inputted to the flip-flop D.
, the value is set. Further, since the level of the 0 point becomes a low level, the level of the [F] point becomes a high level via the OR gate D+o and the Nant gate DII (FIG. 9(m)), and the counter D11 is cleared.

Note that the signal BCIJ shown in FIG. 9(e) rises with the rise of the clock signal φ, and the signal BCIJ shown in FIG.
This is a bus clock signal that falls with the rise of .

On the other hand, when a normal mode block access is performed, each time the signal DCL indicating the end of data transfer goes high (see FIG. 10(h)), the data is accessed via the AND gate D and the NOR gate D7. The level of the 0 point changes as shown in the 10th output (i) and is input to the counter D. Then, as described above, when the counter D counts the specified number of data transfers (in this case, three subsequent data have been transferred), the level of the output point 0 of the counter D8 becomes low level (the 10th (j)), the block access end signal BIEND is output (Fig. 10 (j)).
(see k)). Furthermore, the flip-flop D8 is reset and the 8-counter D11 is cleared. Note that the flip-flop D1 or D! While ADH is set, signal ADH is generated via OR gate DI4 and is supplied to the circuit of FIG.

Further, FIG. 11 shows a specific circuit example of other parts of the bus control section, and FIG. 12 shows the circuit of FIG. 11.
FIG. 4 is a timing diagram showing operations in high-speed mode and normal mode.

That is, FIG. 11 shows a circuit portion for generating the data enable signal DE for controlling the launch section G when transferring data from the bus slave side to the cache memory on the bus master side. Only data when DE becomes high level is transferred to the bus master side.

When executing block access in the high speed mode, as shown in FIG. 12(a), the high speed mode signal (8th
(generated by the circuit shown in the figure) is at a high level,
Every time the clock signal φ is input to the AND gate Dt4 via the OR gate Dts and the AND gate Dza, the data enable signal DE is supplied from the output side of the flip-flop D□ to the latch unit G (see FIG. 12). See C).

On the other hand, when executing block access in normal mode,
As shown in FIG. 12(b), each time the clock signal φ1 is input with each data transfer end signal DCL at a high level, the inverter D□ and the AND gate D are input. , the above-mentioned flip-flop D! via the above-mentioned OR gate Dts and the above-mentioned AND gate I)z4. A data enable signal DE is supplied to the latch section G from the output side of 5 (see FIG. 12(g)).

Further, FIG. 13 shows a specific circuit example of still another part of the bus control section, and FIG. 14 is a timing diagram showing the operation of the circuit shown in FIG. 13.

In other words, FIG. 13 shows the address signal (
In this case, OAO~0A31) is received and the address signal ^ddress (in this case, AO~
This is a circuit portion for outputting as A31). Normally, as shown in FIG. 14, each access request signal is output and each time the clock signal φ2 rises, 1. Noah Gate D3! The address signals AO to A31 are outputted via the respective watch circuits D0 to D3I (first
(See Figures 4(a) to (d)). However, when a block access is executed and the signal ADH shown in FIG. 8 is at a high level, the output side of the NOR gate I)+t becomes a low level, and the outputs of the address signals AO to A31 do not change.

Further, FIG. 15 shows a specific circuit example of the latch section G, and FIG. 16 is a timing diagram showing the operation of the circuit shown in FIG. 15.

That is, FIG. 15 shows a circuit portion for sampling data from the bus slave side (DO to D31 in this case) and inputting it to the bus master side as internal data (IDO to ID31 in this case).

and a clock signal φ. Every time the data (Do-D31) from the bus slave side rises, the data (Do-D31) is transferred to the first stage latch circuit G.
0 to G31 (see FIG. 16(d)), and furthermore, when the data enable signal DE described above is at a high level, the clock signal φ is output.

rises, the output of the AND gate G32 changes the output of the first stage latch circuit to the second stage latch circuits GO' to G.
31', and its output signal is transmitted to the CPU side as internal data IDO to ID31 (see Fig. 16 (g).
)reference).

〔Effect of the invention〕

According to the present invention, since the access cycle for block access can be switched depending on the type of response signal from the bus slave side, it is possible to create a system that can flexibly respond even when external memory is configured with memories with different access times. It can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram for schematically explaining the block access method of the present invention, FIG. 2 is a block diagram for explaining the internal configuration of each control circuit in FIG. 1, and FIG. Figure 4 is a circuit diagram illustrating the specific configuration of the block access request section in Figure 2; Figure 5 is the operation of the circuit in Figure 4; FIG. 6 is a circuit diagram illustrating a specific configuration of the block access execution determination unit in FIG. 2, and FIGS. 7(a) and (b)
is a timing diagram showing the operation of the circuit in FIG. 6, and FIG. 8 is a timing diagram showing the operation of the circuit in FIG. 2.
A circuit diagram illustrating its specific configuration, FIG. 9 and 1θ
11 is a timing diagram showing the operation of the circuit in FIG. 8 in high-speed mode and normal mode, respectively. FIG. 11 is a circuit illustrating the specific configuration of other parts of the bus control section in FIG. 2. Figure, Figure 12 (a
), (b) is a timing diagram showing the operation of the circuit in FIG. 11; FIG. 13 is a circuit diagram illustrating the specific configuration of still another part of the bus control section in FIG. 2; 13 is a timing diagram showing the operation of the circuit in FIG. 13. FIG. 15 is a circuit diagram illustrating the specific configuration of the latch section in FIG. 2. FIG. 16 is a timing diagram showing the operation of the circuit in FIG. FIG. (Explanation of symbols) A... Control circuit on the bus master side, B... Control circuit on the bus slave side, C... Cache memory, D... Bus control unit, E... Block access request unit, F...Block access execution determination unit, G...Latch unit, J...Latch counter, K...Decoder, L...Block access/accrual signal generation unit, M...External memory.

Claims (1)

[Claims] 1. Means for providing a block access request signal from a bus master to a bus slave so as to transfer a plurality of consecutive data to a single address output in a single bus cycle; means for starting block access in response to a start data transfer end signal indicating the end of the start data transfer from the block access request signal and a response signal to the block access request signal; 1. A block access method, comprising: means for performing a block-in operation for storing data in a block, and an access cycle during block access execution is switched depending on the type of response signal to the block access request signal. 2. If a response signal for high-speed transfer is returned as the response signal, each access cycle after the first data transfer cycle is determined according to a predetermined clock signal; If a response signal is returned, each access cycle after the first data transfer cycle is determined according to each data transfer end signal indicating the end of the corresponding data transfer.
Block access method described in section.