JPS60175146A - Programmable controller - Google Patents

Abstract

PURPOSE:To increase the processing speed of a programmable controller by controlling independently the precedent read starting timing of an instruction and data and read waiting timing. CONSTITUTION:A control means controls separately the precedent read starting timing and read waiting timing from a program memory 1 and a data memory 2 in accordance with a microinstruction from a microprogram memory 8. The control means is constituted of an instruction synchronizing flip flop 16 for synchronizing the program memory 1 or the data memory 2 with an arithmetic circuit 9, data synchronizing flip flop 17, a NOR circuit 19 finding out NOR of respective oututs from these flip flops 16, 17, and a switch 20 for inhibiting the sending of a clock signal 117 from a clock circuit 15 to a microprogram counter 7 in accordance with the output from the NOR circuit 19.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a programmable controller used for plant process control, and in particular, to a programmable controller suitable for use in control requiring high speed and high functionality. Regarding control method.

[Background of the invention]

Our programmable control roller started with simple sequence control. However, in recent years, as the field of application has expanded and the need to process numerical operations at high speed has led to the adoption of parallel processing methods for prefetching instructions and data and executing instructions, including increasing the speed of the used elements themselves. . However, due to the increasing complexity of the controlled object,
There is a need for a highly detailed control system for parallel processing and for high-performance processing such as processing multiple pieces of data with one command.

Here, FIG. 1 shows an example of a conventional programmable controller. First, I will give an overview. This controller employs a control system that pre-reads commands and data. Pre-reading means reading in advance the instructions and data that will be needed next in the currently executing operation.

FIG. 2 shows the format of instructions used in this controller, which are stored in program memory 1 in FIG.

FIG. 3 shows the format of microinstructions when the instructions in FIG. 2 are further executed by a microprogram,
It is stored in microprogram memory 8 in FIG. The contents of the control code of this microinstruction are as follows:
This is the table of contents.

Table 1 102...Program counter update (+1) 103.
...Memory address register update (+1) 104...
D register write 105...Set data in write data register 10
6...Start reading data 107...Start writing data 108...JMAP (Execute next command) Next, the fourth
The figure shows an operation time chart of each part of the controller described above.

The major feature of this control method is that the instruction includes a data prefetch permission bit (hereinafter abbreviated as POF bit), and in terms of the structure, program memory 1 and data memory 2 exist independently. There are two stages of instruction registers, a first instruction register 3 and a second instruction register 4, and the address portion of the first instruction register 3 is connected to the memory address register 5.

The operational features will be explained below. The instructions stored in the second instruction register 4 in FIG.
The instruction is decoded by the microprogram counter 7, microprogram memory 8, and then sent to the arithmetic circuit 9, where an arithmetic operation is executed according to the instruction. At this time, if the next instruction to be executed has already been stored in the first instruction register 3, and the POF bit 101 (Figure 2) is 11'', the data readout for this instruction (prefetching, data prefetching) is executed. On the other hand, the program counter 6 is reading the next instruction after the currently executed instruction.Then, when the currently executed instruction ends and the next instruction is executed, the program counter 6 reads the next instruction after the currently executed instruction. The data has entered the read data register 18, and the next instruction that was being read is stored in the first instruction register 3.

A time chart of the above operation is shown in FIG. In FIG. 4, A, B, C, . . . indicate instructions, and it can be seen that they are processed in parallel.

In the above system, the operations of each part of the program memory interface circuit 1O, data memory interface circuit 11, first instruction register 3, second instruction register 4, and arithmetic circuit 9 are performed based on the delimiter of each instruction. Since the process proceeds in synchronization with the JMAP signal 108 shown, there is an advantage that the circuit and concept are simple. Here, the JMAP signal is an abbreviation for JUMP-MAP signal, and is a signal for converting specific bits of an instruction into a microprogram address.It is a signal that specifies the start address and executes the next instruction. .

Now, in the above method, it is necessary that the number of data processed by one instruction is 1 or a fixed number, and if any number of data is processed by one instruction, for example, double-length operations are mixed. etc., speeding up is hindered by the inability to process them.

Next, details of the configuration of the controller shown in FIG. 1 will be shown below. As mentioned earlier, program instructions as shown in FIG. 2 are stored in the program memory l. Data to be operated on is written into the data memory 2, and data is read out from the data memory 2.

Instructions read from program memory 1 are stored in first instruction register 3 and then transferred to second instruction register 4. The format of this instruction is the same as shown in FIG. 2, and the instruction code section 112 indicates the number of instructions.
, POFI 01, and data address 113. POFIOI is 11'' for an instruction that reads and processes data, and 10# for an instruction that outputs data.For the @1# instruction, data can be read in advance before execution of the operation.

The address when reading an instruction from the program memory 1 is given by the program counter 6, and every l instruction length, using the program counter update signal 102,
Count up. The program memory interface circuit 10, which interfaces with the program memorandum 1 when reading instructions, generates the read timing shown in FIG. 4. The arrows in FIG. 4 indicate the order of signal changes. This program memory
A PFE (instruction prefetch start) signal 114 activates the interface circuit 10 to start reading.

The instruction decoder 5 decodes the instruction code of the instruction entered into the second stage of the instruction register, and sets in the microprogram counter 7 the starting address where the microprogram to process the instruction is stored. .

The microprogram counter 7 provides the address of the microprogram to be executed to the microprogram memory 8 in order to execute the microprograms sequentially.

The microprogram memory 8 stores microinstructions (third
Each time the program (Figure) is called, the contents defined in Table 1 are executed, i.e., the operation code, the next microprogram to be executed, etc.
The hardware is operated as shown in addresses and 102-108.

Next, the arithmetic circuit 9 performs various operations including addition and subtraction according to the operation code of the microinstruction. The inside of the arithmetic circuit 9 includes an accumulator A 91. AL
92 and a T register 93 used for temporary purposes for calculation,
an arithmetic unit 94 and temporarily stores a carry of the arithmetic result;
It consists of a carry flag 95 used for carry, etc. in double word operations. Outside the arithmetic circuit 9, there is a D register 12 between the read data register 18 and the arithmetic circuit 9.
Used for exchanging data. The internal data bus 115 is used as a route for transferring data between the arithmetic circuit 9 and its peripheral registers. Addresses for reading and writing data memory 2 are given from memory address register 5. Two methods are used to set an address in the memory address register 5: first, in the case of data prefetching, in which the address field of the 1K-1st instruction register 3 is directly set; and in the second case, the address is set from the arithmetic circuit 9. There are cases.

The above switching is performed by the switch 13, and the conditions for data prefetching, the command prefetching signal (PFE) 11
4 is given and the POF signal 101 of the instruction set in the first stage 3 of the instruction register is '1#, the address part of the first stage 3 of the instruction register is directly set in the memory address register 5.

The read data register 18 is set with data read from the data memory.

The timing to be set is when the response signal 116 of the data memory 2 is returned.

Data to be written into the data memory 2 is set in the write data register 14, and the data memory interface circuit 11 is activated to execute data writing.

The data memory interface circuit 11 also works when reading data and generates the timing shown in FIG.

Clock circuit 15 generates a clock signal 117 for executing the microprogram.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a programmable controller that can process an arbitrary number of data using an l instruction, thereby improving processing speed.

[Summary of the invention]

In order to achieve the above object, the programmable controller according to the present invention independently sets the instruction prefetch start timing and instruction read wait timing, and the data prefetch start timing and data read wait timing into microprogram instructions. It is characterized by the provision of a control means for better control.

According to the present invention, with one instruction such as a double word length instruction,
Even in processes that handle multiple data, prefetching instructions,
Even while reading data ahead or reading multiple data,
Internal calculations can be performed in parallel, thus improving processing speed.

[Embodiments of the invention]

Next, one embodiment of the programmable controller according to the present invention will be described based on the drawings. Embodiments of the present invention are shown in FIGS. 5 to 1O, and parts that overlap with those in FIGS. 1 to 4 are given the same reference numerals, and detailed explanation thereof will be omitted.

In FIG. 5, the main parts that are different from the conventional controller (FIG. 1) are indicated by thick lines. That is, in this embodiment, in addition to the configuration of the conventional controller (FIG. 1), the timing to start prefetching instructions from program memory 1 and the timing to wait for reading instructions, and the timing to start prefetching data from data memory 2, and It has a KfF feature in that it is provided with means for independently controlling the data read wait timing using microinstructions from the microprogram memory 8 (specifically, set signals 110 and 111).

This control means includes an instruction synchronization flip-flop 16 and a data synchronization clip-flop 17 for synchronizing the program memo IJ 1 or data memory 2 and the arithmetic circuit 9, and a NOR circuit for NORing their respective outputs.
It consists of an R circuit 19 and a switch 20 for inhibiting the output of the NOR circuit 19 from sending the clock signal 117 from the clock circuit 15 to the microprogram counter 7 .

In this embodiment (FIG. 5), the program memory 1 stores a program as shown in FIG. 8, for example. An example of the instruction specification is shown in Table 2 below.

゛Table 2 instruction specifications (1) LDD (load double) Set the data at address D100 in the AL register.

Set address DI01101 in the AU register.・ (2) X2D (double x2) Double the contents of the AL and AU registers to AL.

Set to AU.

However, the data in the AU register is treated as the upper digits of AL.

(3) SUBD (subtraction double) D300°D30130 from the contents of AL and AU registers
Subtract address 1 and set it in the AL and AU registers.

However, the AU register and address D301301 are treated as upper digits.

In addition, the read timing of the program memory interface circuit IO when reading an instruction is shown in FIG.
a) K is shown, and the write timing is shown in FIG. 7(b).

The arrows in FIG. 7 indicate the order of signal changes.

Furthermore, the microprogram memory 8 stores microinstructions in the format shown in FIG. As shown in the microprogram address to be executed next and (1) to αυ,
Get the hardware working.

Table 3 102...Program counter update (+1) ((PC
)+1-4PC) 103...Memory address register update (+i)((
MAR)+1-4MAR) 104... D register forward retreat [(几り几)→D] 10
5...Set data in write data register 109.
...DFE (Start reading data ahead) lpE] 106... Start reading data (Read) 107
...Start writing data 110...Data synchronization flip/70 knobs)
(DWRQ) 111...Set of instruction synchronous slip-flop [P
WRQ) 108...JMAP (Execute next command) (JMAP
] 114...PFE (instruction prefetch start) (PFE) 几D
R: Read data register Next, the operation will be explained. Command synchronization 7 lips/70 tubes 16
works as follows. First, in a state in which an instruction prefetch start signal (PFE) 114 is applied from the microprogram memory 8 to the program memory interface circuit 1O to execute prefetching, a set signal (PFE) is input from the microprogram memory 8. ) 111 is applied to the instruction synchronous flip 70 knob 16, this instruction synchronous flip 70 knob 16 is set, the switch 20 is opened through the No. 1 circuit 19, and the clock circuit 1
The clock signal 117 from the program memory 1 is inhibited until reading of the instructions from the program memory 1 is completed, putting the microprogram in a wait state. Data sync flip 7
In the same way, the data memory interface circuit 11 receives the data prefetch start signal (DFE).
109, or if the data synchronization flip-flop set signal (DwnQ) 11o is applied in a state activated by the data read start signal 106, the clock signal 117 is inhibited until the data read is completed, and the microprogram enters the wait state. Become.

Next, the operation will be explained using the example program shown in FIG. Instruction L written in this program (Figure 8)
The specifications of the DD, 2D, and 8UBD are shown in Table 2, and an example of a microprogram for executing each instruction is shown in FIG. The mnemonic in FIG. 9 is shown in parentheses along with the operation definition of the microprogram in FIG. 6.

Here, the content of (), for example, (D) indicates the meaning of "content of D register", and → indicates the data transfer direction. In Figure 9, the microprogram addresses are discontinuous for each instruction because each instruction is microprogrammed and stored at a fixed address. This is done using JMAP, an instruction decoder 5 and a microprogram counter 7. In addition, in FIG. 9 VC, the part surrounded by a dotted line indicates that pre-reading is performed and processing is performed in parallel with calculation. A time chart when this program example is executed is shown in Fig. 1θ.

In Fig. 1θ, times Ts to Txs indicate the time period during which the LDD command is executed, and the reading of the two-word data starts at T6 (V), and the time Txs waits until the reading is finished at T7 to T9. Indicates the condition.

In this case, parallel processing is not performed, but TIO"
``At T1.3, it can be seen that the reading of the 5UBD instruction, which is the next instruction, and the operation of setting data to the AU, which is internal processing, are processed in parallel.Furthermore, at T14 to Tty, the 2D instruction In this case, the instruction prefetch and data prefetch timings can be performed as early as T14, so after performing the calculations from T14 to Tty,
It can be seen that since synchronization is achieved at T17, the waiting time for the memory is low and efficient parallel processing is performed.

In this way, by finely controlling the parallel processing of instructions and data prefetching and instruction execution, it is possible to perform parallel processing of instructions that process a plurality of data.

〔Effect of the invention〕

As described above, according to the present invention, the control means independently controls the instruction prefetch start timing and instruction read wait timing, and the data prefetch start timing and data read wait timing, respectively, by instructions of a microprogram. By providing this, an arbitrary number of data can be processed in parallel with one instruction, and therefore the processing speed of the programmable controller can be improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional programmable controller, Fig. 2 is an explanatory diagram showing an example of an instruction format output from a program memory, and Fig. 3 is an example of a conventionally used microinstruction 7 format. FIG. 4 is a time chart showing the operation of a conventional programmable controller, FIG. 5 is a block diagram showing an embodiment of the programmable controller according to the present invention, and FIG.
Figure 7 is an explanatory diagram showing 7 formats of microinstructions used in the present invention, Figure 7 is a time chart showing the operation of the interface, Figure M8 is an explanatory diagram showing an example of a program stored in the program memory, and Figure 9 is an explanatory diagram showing an example of a program stored in the program memory. The figure is an explanatory diagram showing an example of the contents of the microprogram in the present invention, and FIG. 10 is a time chart showing the operation when the program of FIG. 8 is executed. DESCRIPTION OF SYMBOLS 1... Program memory, 2... Data memory, 3... First instruction register, 4... Second instruction register, 5... Instruction decoder, 6... Program counter, 7 ...Microprogram counter, 8...
・Microprogram memory, 9...Arithmetic circuit, 1
0...program memory interface circuit,
DESCRIPTION OF SYMBOLS 11...Data memory interface circuit, 4...Write data register, 15...Clock circuit, 16...Instruction synchronization flip-flop, 17...
・Data synchronization flip-flop, 18... Read data register, 19... NOI% circuit, 20...
·switch. 1st country 2nd unit 3rd item 4th country 5th item 6th day δ concave 7th (0-) (b)

Claims (1)

[Claims] 1. In a programmable controller that executes an operation in a microprogram and an operation circuit based on the instruction while prefetching the instruction stored in the program memory and the data necessary for the operation stored in the data memory, the above-mentioned The microprogram is characterized by comprising a control means for independently controlling the instruction prefetch start timing and instruction read wait timing, and the data prefetch start timing and data read wait timing, respectively, according to the instructions of the microprogram. Programmable controller.