JPS63280544A - Loopback test system - Google Patents

Abstract

PURPOSE:To attain accurate loopback test by object channel separately by applying multiple circuit setting depending on time division of a line interface in details in response to a channel number. CONSTITUTION:A selector control circuit 27 is provided, which outputs a control signal to 1st and 2nd selector switches 14, 15 and 3rd and 4th selector switches 16, 17. Based on a command signal including channel designation from a central controller, when the designated channel and the channel number are coincident with each other, the selector control circuit 27 controls the 1st-4th selector switches 14-17 to form the line interface 11 to be a loopback circuit toward an internal bus 19 or an external line 18. On the other hand, if the designated channel is dissident with the channel number, the line interface 11 transfers data between the external line 18 and the internal bus 19. Thus, only a data of a terminal equipment of a required specific channel is subject to loopback test and other communication channel continues the data communication successively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer-controlled loopback test method for a line interface in a time division multiplex communication system.

[Conventional technology]

FIG. 4 shows a conventional loopback test method for a line interface section, where 1 is a line interface, 2 is a transmission control section, 3 is a reception control section, 81 to S4 are selective setting type selector switches, and 4 is an external A line such as a LAN, 5 is an internal data bus, and 6 is a terminal interface (1/F) to which different channels are assigned. A plurality of terminals 1/F 6 a to 6n are time-divisionally connected to the line interface 1 of -, and 7 to 10 are unidirectional expansion gates. Selector switch S1 and 82
One terminal of S3 and one terminal of S84 are connected in advance. First, as shown in the figure, when performing a loopback test to the internal data bus 5 side, selector switch S1
buffer gate 7 in S2, buffer gate 8 in S2, S
In Step 3, one terminal is selected by the buffer gate 9, and in Step S4, one terminal is selected. This is set by a command from a CPU (not shown), and may be an electronic switch operation, a relay type operation, or a manual setting using a dip switch. An internal test signal is applied to the line interface 1 from the terminal I/F 61 of a predetermined channel on the internal data bus 5 side, and a continuity test and loopback test are performed.

Next, when performing a loopback test to the external line 4 side, use selector switch S1 to select one terminal other than buffer gate 7.
S2 connects one terminal, s3 connects the buffer gate 9, and S4
Select Panfa Gate 10 with . As a result, the line interface 1 is disconnected from the internal data bus 5, and an external test signal is applied from the external line 4 side to the internal circuit of the line interface 1 to perform a continuity test and loopback test.

[Problem that the invention seeks to solve]

Conventionally, all multi-channel transmission data was looped back based on instructions from the CPU or switch operations.

Therefore, if only a data loopback test was performed for a specific terminal communicating using a specific channel, all channels passing through the line interface 1 would be loopbacked. Therefore, data communication on other channels is also interrupted at the same time, resulting in the disadvantage that multiplexing becomes meaningless.

This invention was made in order to solve these drawbacks, and it provides a multiplex communication loopback test method that allows loopback testing of only the data of terminals on specific channels that are required, while continuing data communication on other communication channels. is intended to provide.

[Means for solving problems]

In this invention, a plurality of terminal interfaces 20 are connected to the line interface II via an internal path 19 and each channel is assigned, an external line 18 is connected to the line interface 11, and a terminal interface 20 is provided to the line interface 11. a first selector switch 14 provided between the internal bus 19 and the transmission control circuit 12; and a first selector switch 14 provided between the internal bus 19 and the reception control circuit 13. 2 selector switch 15, the transmission control circuit 12, and the external bus 18.
and a fourth selector switch 16 provided between the reception control circuit 13 and the external line 18.
The selector switch 17, the transmission control circuit 12, and the reception control circuit 13 give the channel number of the data being transferred, and the central control unit CPU gives a return command to each of the first and second selector switches 14. 15, and a selector control circuit 27 that outputs a control signal to the third and fourth selector switches 16 and 17, and the selector control circuit 27 outputs a control signal to the channel designation i from the central control unit CPU. If the channel i and the channel number match, the first . Second. The third and fourth selector switches 14 to 17 are controlled to make the line interface 11 a loopback circuit towards the internal bus 19 or towards the external line 1B.On the other hand, if the designated channel and channel number i do not match, , the line interface 11 is configured to transfer data between the external line 18 and the internal bus 19.

[Operation] If the designated channel and detection channel number match, the third. The return signal B=1 is given to the fourth selector switch 16, 17 from the selector control circuit 27, the output side of the transmission control circuit 12 and the input side of the reception control circuit 13 are connected, and the return circuit towards the internal bus 19 is connected. 1. When the return signal A=1 is given to the second selector switch 14.15, the output side of the reception control circuit 13 and the input side of the transmission control circuit 12 are connected, forming a return circuit in the direction of the external bus 18. . If the designated channel and the data channel number being transferred are different, the selector control circuit 27 sets A=
0. A normal signal of B=O is output, the first to fourth selector switches 14 to 17 do not operate, and data transfer is maintained.

〔Example〕

The present invention will be explained below based on the drawings.

In FIG. 1, 11 is a line interface, and 12 is a transmission control circuit that detects and outputs each channel number in transmission data. 13 is a reception control circuit that detects and outputs each channel number within the received data.

14 to 17 are alternative type first to fourth selector switches,
18 is a line with the outside connected to a communication path such as an external LAN, and 19 is an internal data bus.

20 is a terminal interface (I/F) to which different channels are assigned;
~20n are connected in a time-division manner. 21
24 is a unidirectional amplifier gate, and 27 is a selector control circuit.

The selector 14 has a buffer gate 21 and a second selector 15
is alternatively selected and connected to the transmission control circuit 12. The second selector 15 selectively connects the reception control circuit 13 to either the buffer gate 22 or the first selector 14, and the third selector 16 connects the transmission control circuit 12 to either the buffer gate 23 or the fourth selector 17. Connect to either one alternatively. Also, the fourth selector 17 is the buffer gate 2
4 and one terminal of the third selector 16 are alternatively selected and connected to the reception control circuit 13.

The selector control circuit 27 receives instructions from a CPU (not shown) and channel numbers c from the transmission control circuit 12 and reception control circuit 13.
Each selector switch 14 to 17 is controlled according to h. 1st. The second selector switch 14.15 is the same signal A,
Third. The fourth selector switches 16, 17 are each controlled by another identical signal B.

Next, the operation will be explained using FIG. 2.3.

First, the CPU sends a return direction signal h, indicating whether to return to the internal bus 1a side or to the line 18 with the outside. A specific channel number i, which is characterized by simultaneous loopback, is also specified. Next, the selector control circuit 27 checks the channel number ch obtained from the transmission control circuit 12 and the reception control circuit 13, and selects the channel number i specified by the CPU.
When detected, each selector switch 14 to 17 is controlled in the sequence shown below.

First, a return signal and a channel designation signal i are given from the CPU to the internal bus 19 side, and the selector control circuit 27 selects the transmission control circuit 1 as the channel number of the data being communicated.
When given the channel number i from 2, it outputs selector signals A and B in the form By shown in FIG. At this time, the signal A is "0", and the first . Second selector switch 14
．． 15 is not operated and selects the original connection position, and the buffer gate 21, the transmission control circuit 12, and the reception control circuit 13 and the buffer 22 are connected, respectively.

- the force signal is 1” and the 3rd and 4th selector switch 1
6.17 is operated, and the selector switch 16 selects the position where the output side of the transmission control circuit 12 is connected to one terminal of the fourth selector switch 17. At the same time, the fourth selector switch 17 selects a position where this one terminal is tangent to the input side of the reception control circuit 13. In this way, Figure 3 (a)
As shown in , when data of designated channel number i is input to line interface 11, designated channel number i
A loopback test is performed between the terminal 1/F 20i and the line interface 11.

Next, data a that is not specified channel number i is terminal 1/F2.
When input from 0a to the line interface 11, the selector control circuit 27 is in the state ■! shown in FIG. outputs selector signals A and B. At this time, both signals A and B are “0”
Therefore, the first to fourth selector switches 14 to 17 are not operated and select the original connection position, and as shown in FIG. and buffer gate 23 are connected.

At the same time, the buffer gate 24 and the reception control circuit 13 are connected, and the reception control circuit 13 and the buffer gate 22 are connected. In this way, the original data communication is performed for channel a which is not specified.

Next, when a command is received from the CPU to return the return direction signal to the external line 8 while leaving the designated channel number i unchanged,
The selector control circuit 27 outputs selector signals A and B in state (2) in FIG. At this time, the signal is “L” and the signal B is “0”
”. Therefore, the third and fourth selector switches 16.1
7 is not operated, the original connection position is selected, and the output side of the transmission control circuit 12 and the buffer gate 23 are connected, and the buffer gate 24 and the input side of the reception control circuit 27 are connected, respectively.

Ichirikitsutsu 1. The second selector switch 14,15 is operated by the signal A, and the second selector switch 15 connects the output side of the reception control circuit 13 to one terminal of the first selector switch 14, and the first selector switch 14 connects the output side of the reception control circuit 13 to one terminal of the first selector switch 14. The positions at which these are connected to the input side of the transmission control circuit 12 are selected. In this way, as shown in FIG. 3(B), when data of the designated channel number i is input to the line interface 11, a loopback test is performed between the external line 18 and the line interface 11.

Next, data a that is not specified channel number i is sent to terminal 1/
When input from F20a to the line interface 11, both selector signals A and B become "0" as described above.
Then, the original data communication is performed as shown in FIG. 3(C). In this way, multiplex circuit settings are made by time division of the line interface 11 in detail according to the channel number, so that the high performance of multiplex communication can be fully utilized.

〔Effect of the invention〕

As described above, according to the present invention, there are a plurality of terminal interfaces connected to a line interface via an internal bus and to which channels are assigned, an external bus to which the line interface is connected, and a terminal interface connected to the line interface. a transmission control circuit and a reception control circuit; a first selector switch provided between the internal bus and the transmission control circuit; a second selector switch provided between the internal bus and the reception control circuit; A third selector switch provided between the control circuit and the external bus, a fourth selector switch provided between the reception control circuit and the external bus, and these transmission control circuits and reception control circuits are transferred. a selector control circuit configured to output a control signal to each of the first and second selector switches and the third and fourth selector switches in response to a return command given from the central control device as well as a channel number of the data therein; Based on a command signal including channel designation from the central control device, if the designated channel and channel number match, the selector control circuit selects the first. 2nd degree Controls the third and fourth selector switches to set the line interface as a loopback circuit to the internal bus or to the external line.On the other hand, if the designated channel and channel number do not match, the line interface is Since data transfer is performed between the external line and the internal bus, the line interface is disconnected and the loopback test is performed only on the channel for which the loopback test is desired, and data transfer can be continued for a while or other channels allows the same line interface to be connected in a time-sharing manner without disrupting the channel in operation. In this way, by taking advantage of the advantages of time division multiplex communication, it is possible to separate and accurately perform loopback tests for each target channel.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the loopback test device of the present invention, Fig. 2 is a state diagram of a selector signal, Fig. 3 is a data direction diagram explaining the present invention in detail, and Fig. 4 is a block diagram of a conventional line interface. It is a diagram. DESCRIPTION OF SYMBOLS 11... Line interface, 12... Transmission control circuit, 13... Reception control circuit, 14-17... Selector switch, 18... External line, 19... Internal bus, 20...・Terminal ■/F121-24...Panther gate, 27...Selector control circuit, A, B...
Selector signal, h: return direction signal, i: return channel number signal. Agent Masuo Oiwa (and 2 others) Figure 3 (A) (B) (C) Procedural amendment translation Jizoku 1, Indication of case Patent Application No. 116105 No. 1988 2,
Invention title folding test method 3, person making the amendment Representative Moriya Shiki 4, agent 5, detailed explanation of the invention to be amended, grasp of drawings. 6. Contents of amendment +11 On page 3 of the specification, lines 11 to 13, the phrase “-1111 is selected at buffer gate 9” was replaced with “the other terminal other than buffer gate 9.” , the other terminal other than the buffer gate 10 is selected in S4.'' (2) In the same book, page 3, lines 14 to 15, the phrase "relay type operation" is corrected to "relay type operation." (3) In the same book, page 4, line 1, the phrase ``rS2 connects one terminal,'' is corrected to read ``rS2 connects the other terminal that is not the buffer gate 8.'' (4) In the same book, page 6, line 13, the phrase "with the specified channel" is corrected to read "the return direction is specified on the internal bus side and with the specified channel." (5) In the same book, page 9, line 19, the phrase "-The force signal is "1"" is corrected to "-The force signal B is "1"." (6) In the same book, page 10, lines 10 to 11, "the line starts from channel number i...--" is corrected to "the data from the terminal I/F 20a that is not channel number i is the line". do. (7) In the third and fourth lines of page 12 of the same book, the phrase ``Number i is not...---Interface'' is replaced with ``Number i.''
The data for channel number a that is not a line interface is corrected. (8) The drawings and Figure 1 shall be amended as shown in the attached sheet. that's all

Claims (1)

[Claims] a plurality of terminal interfaces connected to the line interface via an internal bus and to which each channel is assigned;
an external bus to which the line interface is connected; a transmission control circuit and a reception control circuit provided in the line interface; a first selector switch provided between the internal bus and the transmission control circuit; a second selector switch provided between the receiver control circuit and the external bus; a third selector switch provided between the transmitter control circuit and the external bus; and a third selector switch provided between the receiver control circuit and the external bus. The fourth selector switch provided in each of the first and second selector switches, the transmission control circuit, and the reception control circuit give the channel number of the data being transferred, and a return command is given from the central control unit to each of the first and second selector switches and a selector control circuit that outputs a control signal to a third and fourth selector switch, and based on a command signal including a channel designation from the central control device, the selector control circuit determines whether the designated channel and the channel number match. In this case, the first, second, third, and fourth selector switches are controlled to make the line interface a return circuit to the internal bus or to the external bus, while the designated channel and the channel number do not match. In this case, a loopback test method is used in which the line interface performs data transfer between the external bus and the internal bus.