JPS63233382A - Skew detector - Google Patents

Abstract

PURPOSE:To increase an accuracy by providing two latch circuits for using a pulse signal from a pulse generating circuit as a strobe signal, taking-in the complementary output voltage of a differential amplifier circuit at the time when the strobe signal is applied to and holding the strobe signal until a reset signal is applied to. CONSTITUTION:Input signal converting circuits 1a and 1b convert the logical levels of pulse signals (a) and (b) to be measured with different amplitudes and the like to the same level. A difference between the output levels of the circuits 1a and 1b is amplified 2 and, only while a skew is generated, complementarily amplified pulse signals are obtained in the output ends (j) and (k) of a differential amplifier circuit 2. The output ends (j) and (k) are connected to the input ends (m) and (n) of latch circuits 3a and 3b, respectively, so that polarities are reversed and a strobe signal (o) is applied to the circuits 3a and 3b in synchronism with the rising of one of the signal (a) and (b). Then, the outputs of the circuits 3a and 3b are complementarily fixed to a logical level in accordance with the polarity of the skew between the signals (a) and (b). The strobe signals synchronized with the rising and falling of the signal (a) and (b) necessary for detecting the skew can be self-generated by a strobe/reset pulse generating circuit 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a skew detection device that detects a time lag between the rise or fall of two input pulses, that is, a timing skew, and particularly relates to a skew detection device that detects a timing skew between two input pulses. The present invention relates to a skew detection device that is suitable for detecting timing skew between pulse signals generated from a plurality of test bins in an integrated circuit testing device and the like.

(Prior art) As the operating speed of integrated circuits increases, integrated circuit testing equipment is required to have higher accuracy in test timing, and the timing skew that occurs between multiple test pulse signals generated by integrated circuit testing equipment is becoming increasingly important. It is necessary to compensate for the high accuracy.

There is a need for a timing skew detection device with high time resolution.

In the conventional technology, via a strobe signal applied externally to a latch circuit that captures skew information,
The presence or absence of skew has been determined by separately detecting the timing of two pulse signals to be measured. FIG. 11 is a circuit block diagram showing an example of a conventional skew detection device used in integrated circuit testing equipment and the like. In this circuit, the first . Of the second pulse signals a and b, only the first pulse signal a is first applied to the comparator 20, and the voltage level is compared with a reference signal C set to an intermediate level of the first pulse signal a, for example. In the latch circuit 21 connected to the next stage to hold the result, the application timing of the strobe signal d applied from the timing signal source 25 is continuously changed by the strobe timing control circuit 26, and the output terminal e of the latch circuit 21 is The level transition timing at which the voltage changes from low to high or high to low is detected, the strobe timing at this time is detected as the rising or falling timing of the pulse signal a, and then the strobe timing is detected in the middle of the second pulse signal. After setting the level of the reference signal C again, the switch 22 is switched to apply the second pulse signal S to the comparator 20, and the strobe signal d is applied to the latch circuit 21 at the level transition timing of the first pulse signal a. At this time, if the logic level of the output terminal e of the latch circuit 21 is low or high, it is determined that there is a skew, and if it is at an intermediate level, it is determined that there is no skew. That is, two pulse signals a,
The timing skew of b was detected.

Further, when the latch circuit 21 cannot output an intermediate level, for example, the output e of the latch circuit 21 and the strobe signal d
a waveform shaping circuit 23 that generates a pulse signal by the AND of
A counter 24 whose clock input is the output signal f of the waveform shaping circuit 23 is added, a second pulse signal is applied a plurality of times,
It was determined that there was no skew when the number counted by the counter 24 became half the number of times the second pulse signal was added, that is, half the number of times skew was detected.

(Problems to be Solved by the Invention) As described above, in the conventional technology, it is difficult to miniaturize the device because it requires a latch strobe signal source whose output timing can be arbitrarily set and a circuit that controls the strobe timing. Ta. In addition, since the skew between two pulse signals cannot be directly detected with a single latch strobe, it takes a long time to detect the skew.
Another problem is that dynamic jitter in the strobe signal causes a decrease in detection accuracy, making it unsuitable for achieving high accuracy.

(Object of the Invention) The present invention solves the conventional problems, eliminates the need to supply a strobe signal for the latch circuit from the outside, and allows the timing skew of two pulse signals to be directly detected with a single latch strobe. The purpose of the present invention is to provide a simple and highly accurate skew detection device.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides two independent solutions.
Normalize the voltage levels of two input pulse signals individually 2
a differential amplifier circuit that detects the potential difference between the output terminals of the two level conversion circuits; and a differential amplifier circuit that shapes a single pulse wave based on a signal change at least at the rising edge of one of the input pulse signals. a pulse shaping circuit; and two pulse shaping circuits that use one of the pulse signals outputted by the pulse shaping circuit as a strobe signal, take in the complementary output voltage of the differential amplifier circuit when the strobe signal is applied, and hold it until a reset signal is applied. It is characterized by comprising a latch circuit.

In the skew detection device of the present invention, after normalizing the voltage levels of two pulse signals to be measured, a differential amplifier circuit directly detects the voltage level difference between the two signals. Using a strobe pulse generated in synchronization with the falling edge, the detection result of the differential amplifier circuit is taken into the latch circuit and held. Therefore, a timing skew can be detected in real time every time a pulse is input without requiring a new signal source for the strobe.

Next, examples of the present invention will be described. It should be noted that the embodiments are merely illustrative, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

(Embodiment) FIG. 1 is a circuit block diagram showing an example of a skew detection device according to the present invention, where la and lb are input signal level conversion circuits, 2 is a skew detection differential amplifier circuit, 3a,
3b is a latch circuit for holding skew information; 4 is a strobe/reset pulse generation circuit, that is, a pulse shaping circuit; 5
is a connection switch, 6 is an AND gate, 7 is a NAND
gate, 8 is an inverter, 9 is a delay circuit, a and b are pulse signals to be measured, g is a reference signal for the level conversion circuit, h,
t is the output of the level conversion circuit, J is the output of the differential amplifier circuit, m and n are the inputs of the latch circuit, 0 is the latch strobe signal, p is the latch reset signal, q and r are the outputs of the latch circuit, W indicates select data. Also, Figure 2 is
FIG. 6 is a waveform diagram of a main part of the circuit shown in the figure for explaining the circuit operation when detecting a skew at the time of rising. Figures 1 and 2
The functions and operations of each component will be explained below based on the diagram.

The input signal level conversion circuits 1a and lb have a function of converting the logic low level and logic high level of two pulse signals a and b to be measured having different amplitudes and voltage levels to the same level.

FIG. 3 shows an embodiment of a level conversion circuit which is a component of the skew detection device according to the present invention.

In the figure, Q1 to Q3 are npn transistors, R1
-R3 is the resistance, a is the pulse signal to be measured, g is the reference signal for the level conversion circuit, h is the output of the level conversion circuit, V cc
is a pull-up power supply, V1111 is a pull-down power supply, ■
c indicates a gate current control power source.

For example, one pulse signal under test a is CM L (Cur
Rent Mode Logic) level, the pulse signal under test is an LCML signal with a different amplitude from the signal a.
(LouLevel Current Mode Lo
gic) In case of failure, a one-curve coupling type level conversion circuit as shown in FIG. By setting the high level to Vcc and the low level to Vcc (Vcs Vbe V*,)X R1/
Converted to R2. However, V- is the power supply potential for the pull amplifier, ■, is the power supply potential for pull-down, Vk is the base-emitter voltage of the constant current source transistor Q3, and ■
. represent the base potential of the transistor Q3, therefore, each potential of V ee+ v@@i vcs and R1゜R2
By setting the respective resistance values to the same values as those used in the LCML circuit, for example, both wave measurement pulse signals can be converted to the same LCML level. Therefore, a voltage level difference occurs between the output signals of the level conversion circuit and i only due to the deviation of the rising and falling edges of the pulses, that is, the skew.

When the output level difference between the input signal level conversion circuits 1a and lb is amplified by the next-stage differential amplifier circuit 2, the output terminals j and k of the differential amplifier circuit 2 have a skew as shown in Fig. 2. , a complementary amplified pulse signal is obtained.

FIG. 4 shows an example of a latch circuit that is a component of the present invention, in which Q4 to Qll are npn transistors, Ve (is a pull-up power supply, V am is a pull-down power supply, and V cm is a gate current control R4-R6 are resistors, m and n are differential inputs, q is an output, and V is a reference signal for the second level of the LCML circuit.

For example, the differential amplification type latch circuit 3 shown in FIG. 4 is applied to the two latch circuits 3a and 3b connected to the next stage of the differential amplifier circuit 2, and the k are respectively connected to input terminals m and n of the latch circuit so that their polarities are reversed. Then, if the strobe signal O is applied to the latch circuits 3a and 3b in synchronization with the rise of one of the pulse signals a and b under test, the latch will be latched according to the polarity of the skew occurring between the pulse signals a and b. Circuit 3a, 3
The output of b is fixed to a complementary logic low level or logic high level. For example, in accordance with the above example, when the latch circuit shown in FIG. 4 is introduced into the latch circuit section shown in FIG. If the rise timing of the output h) is later than that of the pulse signal b to be measured (output l of the level conversion circuit tb), the output q of the latch circuit 3a becomes a logic high level, and in the opposite case, the latch The output r of the circuit 3b becomes a logic high level.

On the other hand, if no skew occurs between the pulse signals a and b under test, the output of the differential amplifier circuit @j.

Since both k remain at the intermediate level and no pulse signal is generated, the outputs q and r of the latch circuits 3a and 3b remain in the state determined before strobe signal 0 is applied, as shown in Figure 2. be. Therefore, before applying the strobe signal 0, if a reset signal is applied to the reset terminal p shown in FIG. Even after application, it is fixed at the same logic low level.

Therefore, the presence or absence of skew can be determined by whether the output levels of latch circuits 3a and 3b are complementary to each other, and the polarity of skew can be determined by determining which output of latch circuits 3a and 3b is at a logic high level. It can also be determined which of the two pulse signals a and b is leading in phase.

The skew at the falling edge can be detected in the same way as the skew at the rising edge described above by adding a strobe signal synchronized with the falling edge of one of the pulse signals a and b.

A strobe signal synchronized with the rise and fall of the pulse signal under test, which is necessary for skew detection, can be self-generated by installing the strobe/reset pulse generation circuit 4 shown in FIG. 1, for example. There is no need to supply it externally. This strobe/reset pulse generation circuit consists of an AND gate 6, a NAND gate 7, an inverter 8, and a delay circuit 9. The pulse signal a to be measured and this signal a are inverted by the inverter 8 and are processed by the delay circuit 9 for the required time δt. By ANDing and NANDing the delayed signal, it is possible to generate two pulse signals that are synchronized with the rising and falling edges of the pulse signal under test. If one is used as a strobe signal and the other as a reset signal, the A strobe/reset signal synchronized with the measurement pulse signal is obtained.

Since the pulse width obtained in this strobe/reset pulse generation circuit is determined by the delay time δt, δt may be set according to the response characteristics of the latch circuit used to the strobe pulse.

If the pulse signal generated by performing the above AND is used as a strobe signal, the timing skew at the rising edge can be detected. If the pulse signal generated by NAND is used as the strobe signal, the timing skew at the falling edge can be detected. As shown in FIG. 1, a changeover switch 5 is added to connect the two pulse signals generated by the strobe/reset pulse generation circuit to the strobe input 0 and reset input p of the latch circuit according to the selection data W. By switching, it is possible to detect either the skew at the rising edge or the skew at the falling edge of the pulse signal under test.

Furthermore, this strobe/reset pulse generation circuit
Since the reset signal can be automatically generated within one cycle of the pulse signal under test, even if the pulse signal under test is a repetitive signal, individual rising or falling edges can be generated without applying a special control signal from outside. Skew can be detected in real time. FIG. 5 is a circuit block diagram showing another embodiment of the skew detection device according to the present invention. In FIG. 0, 10a and 10b indicate counter circuits, and all other symbols are the same as in FIG. In the above case, for example, as shown in FIG. 5, by connecting counters 10a and 10b which use the outputs q and r of the latch circuit as clock signals, respectively, the number of positive skew detections and the number of negative skew detections can be adjusted. can be stored individually.

Therefore, it is possible to statistically determine the presence or absence of skew between the number of repetitions of the pulse signal under test, as well as the polarity of the skew, making it possible to achieve high accuracy even in minute time domains where waveform jitter is a problem. Skew can be detected.

FIG. 6 is a circuit block diagram showing another embodiment of the skew detection device according to the present invention. 11 is the NOR gate,
12 is a set/reset flip-flop, 13 is an up/down counter, 14 is a skew detection circuit, and S is N.
The output of the OR gate, U is the output of the set/reset flip-flop, x and y are the set input and reset input of the set/reset flip-flop, respectively, and all other symbols are the same as in FIG. 1. Thus, a NOR gate 11 receives the outputs q and r of the latch circuits 3a and 3b as inputs, and a set/reset flip-flop 12 receives the output q of the latch circuit 3a as a set input and the output r of the latch circuit 3b as a reset input. Up/down counter 13 that performs counting operation on the rising edge of the clock
and the output S of the NOR gate 11, and the set/
The output U of the reset flip-flop 12 is increased/
It serves as a clock input for the down counter 13 and an up/down control signal input.

For example, when counting up when the up/down control signal is at a high level and counting down when it is at a low level, counting up is performed when the skew is in the positive direction, and counting down is performed when the skew is in the negative direction. Therefore, in this case, if the up/down counter 13 is reset in advance and the output data is set to zero before starting the skew detection operation, if the output data of the up/down counter is a positive value, the skew will be in the positive direction. If the output data has a negative value, it can be seen that there is a large amount of skew in the negative direction.

If the output data is zero, it indicates that the skew in both the positive and negative directions is the same, or that both are zero. The polarity of the output data can be determined by looking at the most significant bit assigned to the sign bit, so the polarity of the skew can be determined from only the most significant pin of the output data, regardless of the number of bangs in the signal under test, or in other words, the number of skew detections. It is possible to do so. In addition, in this circuit, when the magnitude of the skew becomes small to the same extent as the amount of jitter present in the pulse signal under test, the absolute value of the counter output data starts to decrease from the total number of measurements, and as the magnitude of the skew decreases, the counter output data decreases. The output data of the counter approaches zero. Therefore, for a skew that is smaller than the jitter amount of the pulse signal under test, it is also possible to determine the magnitude of the skew based on the absolute value of the output data of the counter.

Next, still other embodiments of the present invention will be described.

FIG. 7 is a circuit block diagram showing another embodiment of the skew detection device according to the present invention, where la and lb are input signal level conversion circuits, 2 is a differential amplifier circuit for skew detection, and 3 is a circuit block diagram showing another embodiment of the skew detection device according to the present invention.
a, 3b are latch circuits for holding skew information, 4'' is a strobe pulse generation circuit, and 5° is a connection switch. Fig. 8 shows a circuit for detecting skew at the rising edge of the circuit shown in Fig. 7. FIG. 7 is a main part waveform diagram illustrating the operation.

Based on FIG. 8, the functions and operations of each component will be explained below.

The input signal level conversion circuits 1a and lb have a function of converting the logic low level and logic high level of two pulse signals a and b to be measured having different amplitudes and voltage levels to the same level.

Similarly to the embodiment shown in FIG.
gic) level, the other pulse signal under test signal a
L CM L (Lou Level
At the Current Mode Logic) level, an emitter-coupled level conversion circuit as shown in FIG. 3 can be applied to convert both wave measurement pulse signals a and b to the same LCML level. Therefore, between the output signal of the level conversion circuit and i, the rising edge of the pulse,
A difference in voltage level occurs only due to a shift in the falling edge, that is, a skew.

When the output level difference between the input signal level conversion circuits 1a and lb is amplified by the next-stage differential amplifier circuit 2, the output terminals J and k of the differential amplifier circuit 2 will have a skew as shown in Fig. 8. , a complementary amplified pulse signal is obtained.

Two latch circuits 3 connected to the next stage of the differential amplifier circuit 2
For example, the differential amplification type latch circuit 3 shown in FIG. Connect each one so that Similar to the embodiment shown in FIG. 1, when the latch circuit shown in FIG. 4 is introduced into the latch circuit shown in FIG. The rising timing of the output h of the conversion circuit 1a) is the timing of the rise of the pulse signal under test b (the output i of the level conversion circuit 1b).
), the output q of the latch circuit 3a
becomes a logic high level, and in the opposite case, the latch circuit 3b
The output r becomes a logic high level.

On the other hand, if no skew occurs between the pulse signals a and b under test, the output terminal j of the differential amplifier circuit.

Since both k remain at the intermediate level and no pulse signal is generated, the outputs q and r of the latch circuits 3a and 3b remain in the state determined before strobe signal 0 is applied, as shown in Figure 8. be. Therefore, before applying the strobe signal 0, for example, a reset signal is applied to the reset terminal p shown in FIG.
If the outputs q and r are both set to a logic low level, they will be fixed at the same logic low level even after the strobe signal is applied.

Therefore, the presence or absence of skew can be determined by whether the output levels of the launch circuits 3a and 3b are complementary to each other, and the polarity of the skew can be determined by determining which output of the latch circuits 3a and 3b is at a logic high level. It can also be determined whether the phase of either of the two measured pulse signals a and b is leading.

The skew at the falling edge can be detected in the same way as the skew at the rising edge described above by adding a strobe signal synchronized with the falling edge of one of the pulse signals a and b.

A strobe signal synchronized with the rise and fall of the pulse signal under test, which is necessary for skew detection, can be generated self-generated by installing a strobe pulse generation circuit 4 shown in FIG. 7, for example, or externally. This strobe pulse generation circuit 4' has the same configuration as the strobe/reset pulse generation circuit shown in FIG. Pulse signals can be generated, and if one of them is used as a strobe signal, a strobe signal that is always synchronized with the rise or fall of the pulse signal under test can be obtained. The pulse width obtained at this strobe pulse generation tCa path 4° is determined by the delay time δL, so δt can be set according to the response characteristics of the latch circuit used to the strobe pulse. If this pulse signal is used as a strobe signal, the timing skew at the rise time can be detected, and
If the pulse signal generated by
As shown in the figure, by adding a changeover switch 5' and switching the connection between one of the two pulse signals generated by the strobe pulse generation circuit 4'' and the strobe input 0 of the latch circuit according to the selection data W. , it is possible to detect both the skew at the rising edge and the skew at the falling edge of the pulse signal under test.

As described above, the circuit configuration shown in FIG. 7 uses an NRZ signal (Non Return-to-Zer
For example, as in another embodiment of the present invention shown in FIG.
By taking D, the RZ multiplied signal Return-to-
Zero) It is also possible to obtain outputs q+, r+.

In this case, by connecting counters 10a and 10b each using signals q+, q+, and + as clock signals, it is possible to individually store the number of positive skew detections and the number of negative skew detections. Therefore, it is possible to statistically determine the presence or absence of skew and the polarity of skew between the number of repetitions of the pulse signal under test, providing high accuracy even in the time domain where waveform jitter is a problem. skew can be detected.

FIG. 10 shows another embodiment of the present invention, in which an OR gate 1 receives outputs q and r of latch circuits 3a and 3b as inputs.
1', an AND gate 6 which receives the output S of the OR gate 11' and the pulse signal under test a, and a set input which takes the output q of the latch circuit 3a as the set input and the output r of the latch circuit 3b as the reset input. a reset flip-flop 12;
An amplifier/down counter 13 that performs a counting operation on the rising edge of the clock is added, and the output S° of the AND gate 16 and the set/reset flip-flop 12 are added.
The output U of the up/down counter 13 is used as a clock input and an up/down control signal input, respectively. A
The output signal 3' of the ND gate 16 becomes an RZ multiplied signal when a skew occurs in either positive or negative polarity.

For example, when counting up when the up/down control signal is at a high level and counting down when it is at a low level, counting up is performed when the skew is in the positive direction, and counting down is performed when the skew is in the negative direction. Therefore, in this case, as in the embodiment shown in FIG. 6, if the up/down counter 13 is reset in advance and the output data is set to zero before the start of the skew detection operation, the output of the up/down counter 13 can be set to zero. It can be seen that if the data is a positive value, there is a lot of skew in the positive direction, and if the output data is a negative value, there is a lot of skew in the negative direction. If the output data is zero, it indicates that the skew in both the positive and negative directions is the same, or that both are zero. The polarity of the output data can be determined by looking at the most significant bit assigned to the sign bit, so the polarity of the skew can be determined from only the most significant bit of the output data, regardless of the number of bangs in the signal under test, or in other words, the number of skew detections. It is possible to do so. In addition, in this circuit, when the magnitude of the skew becomes small to the same extent as the jitter amount of the pulse signal under test, the absolute value of the counter output data starts to decrease from the total number of measurements, and as the magnitude of the skew decreases, the counter The output data of the counter approaches zero. Therefore, for a skew that is smaller than the jitter amount of the pulse signal under test, it is also possible to determine the magnitude of the skew based on the absolute value of the output data of the counter.

In addition, in the embodiment described above, FIG.

The embodiments shown in FIGS. 5 and 6 are used to evaluate the presence or absence of skew by counting the number of pulses, and the embodiment shown in FIG.

The embodiments shown in FIGS. 8, 9, and 1θ are suitable for measuring the skew width.

(Effects of the Invention) As is clear from the above description, according to the present invention, there are provided two level conversion circuits that individually normalize the voltage levels of two mutually independent input pulse signals, and a A differential amplifier circuit that detects the potential difference between output terminals,
A pulse shaping circuit that shapes a single pulse wave based on at least a rising edge signal change of one input pulse signal, and one pulse signal outputted by the pulse shaping circuit is used as a strobe signal, and when the strobe signal is applied, Two latch circuits that take in the complementary output voltages of the differential amplifier circuit and hold them until a reset signal is applied. There is no need to install a source or a strobe timing control circuit, and the timing skew between two pulse signals can be directly detected in real time. Further, since the strobe/reset pulse generation circuit or the strobe pulse generation circuit, which is a component of the present invention, can be realized with only a few logic gates, there is no problem with the circuit scale. For example, when configured with an LCML circuit, the basic configuration without adding a counter circuit has approximately 5
It can be realized with 0 transistors and about 15 resistors. For example, even if two 10-bit counters are added, the number of transistors can be about 700, so it can be realized with one mask slice of 500 gates. In addition, since the strobe pulse is internally generated in synchronization with the rising or falling edge of the pulse signal under test, it is possible to eliminate most of the variation in latch strobe timing that causes a decrease in detection accuracy, resulting in higher accuracy. 0 For example, the present invention uses ultra-high-speed bipolar process technology S S T
(Super Self-aligned Process
ss Technology), it is possible to achieve performance with a time resolution of 2 ps and an absolute accuracy of about ±10 ps.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of the skew detection device in the present invention, FIG. 2 is a waveform diagram of main parts explaining the operation of the circuit shown in FIG. 1, and FIG. 3 is a skew detection device in the present invention. FIG. 4 is a diagram showing an example of a level conversion circuit that is a component of the device, FIG. 4 is a diagram showing an example of a latch circuit that is a component of the skew detection device of the present invention, and FIG. A circuit block diagram showing another embodiment of the skew detection device, FIG. 6 is a circuit block diagram showing another embodiment of the skew detection device in the present invention, and FIG. 7 is a circuit block diagram showing another embodiment of the skew detection device in the present invention. FIG. 8 is a main part waveform diagram explaining the operation of the circuit shown in FIG. 7, and FIG. 9 and FIG. 1O are circuit blocks showing other embodiments of the skew detection device according to the present invention. FIG. 11 shows a circuit plotter diagram showing an example of a conventional skew detection device. la, lb...Input signal level conversion circuit 2...
-Differential amplifier circuit 3...Differential amplification type latch circuit 3a, 3b...Latch circuit 4...Strobe/recent pulse generation circuit 4'...Strobe pulse generation circuit 5 .5゛...
・Connection switching switch ・・AND gate 7・・・・・NAND gate 8・・・・・Inverter 9・・・・Delay circuit 10a, 10b・Counter circuit 11・・・NOR gate 11′ ...OR gate 12...Set/reset flip-flop 13...Amplifier/down counter 14...
- Skew detection circuit body 15a, 15b -ANDNO gate...AND gate 20...Comparator 21...Latch circuit 22...Selector switch 23...For waveform shaping AND circuit 24...Counter 25...Strobe signal source 26...Strobe timing control circuit Ql-
Q3・npn transistor R1~R3・Resistor Q4~Qll・npn transistor R4~R6・Resistor V eC...Pull-up power supply V am...Pull-down power supply ■c,...Power supply patent for gate current control Applicant Nippon Telegraph and Telephone Corporation Agent Patent Attorney Satoshi Takayama 1, 1 husband (1 other person)”’
l5. ,' @1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (3)

[Claims] (1) Two level conversion circuits that individually normalize the voltage levels of two mutually independent input pulse signals; a differential amplifier circuit that detects the potential difference between the output terminals of the two level conversion circuits; a pulse shaping circuit that shapes a single pulse wave based on at least a signal change in the rising edge of an input pulse signal; and one pulse signal outputted by the pulse shaping circuit is used as a strobe signal, and the difference when the strobe signal is applied is A skew detection device comprising two latch circuits that take in complementary output voltages of a dynamic amplifier circuit and hold them until a reset signal is applied. (2) A pulse shaping circuit that independently shapes a single pulse wave at each rising and falling timing based on signal changes at the rising edge and falling edge of the input pulse signal, and 2. The skew detection device according to claim 1, wherein a pulse wave shaped by the pulse shaping circuit at each timing is used as a reset signal. (3) The skew detection device according to claim 1, which uses a reset signal supplied from the outside.