JP3025551B2 - DC characteristics test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for easily performing a DC characteristic test among semiconductor device tests.

[0002] Semiconductor device tests can be divided into DC characteristic tests and AC characteristic tests. Among them, the DC characteristics test includes an input current test, a _VOH / _VOL test, an _ICC test, and the like.

In order to perform a V _OH · V _OL test, an “H” or “L” potential must be set to each terminal of a semiconductor device. However, the setting is complicated with the recent high integration of semiconductor devices. And it's getting harder. for that reason,
Effective means for easily setting the “H” or “L” potential to each terminal is desired.

[0004]

2. Description of the Related Art Some semiconductor devices to be tested have
To set the “H” or “L” potential to the output terminal
First, a predetermined timing and
And waveform mode. Then, for each semiconductor device
By flowing measurement patterns unique to each other,
Are set to the “H” or “L” potential.
V _OH・ V_OLIn the test, this "H" or "L" state
Measure the voltage value at and verify that it is within regulation
You.

In order to set an "H" or "L" potential to another output terminal, measurement patterns unique to the semiconductor device to be tested are flown again one after another. That is,
Each time the output terminal changes, each measurement pattern is flown to set the potential of the output terminal.

[0006]

As described above, conventionally,
For each output terminal, set the input side of the semiconductor device
While changing in various ways_OH・ V_OLTest
I was Therefore, as the number of input terminals increases,
The conditions for setting the output terminal are complicated. at the same time,
When the number of output terminals increases, the potential of “H” or “L”
It takes extra time for the set time. And especially near
Years of high integration of semiconductor devices, V _OH・ V_OLTess
The problem is that the time required for
is there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide an effective means for easily setting an "H" or "L" potential to an output terminal of a semiconductor device. .

[0008]

According to the present invention, the above objects are achieved by the means as set forth in the appended claims. That is, the present invention relates to a test circuit which is provided between an internal circuit unit and an output unit of a semiconductor device and outputs a predetermined signal in response to an input signal in a semiconductor device test. In response to this, when a pulse of one control signal is detected, the state is initialized, and a high level or a low level is determined regardless of the type of an input signal received from the internal circuit section. Is a DC characteristic test circuit that outputs the signal to the output unit and inverts the output to the output unit from a high level to a low level or from a low level to a high level every time a pulse of another control signal is detected.

[0009]

FIG. 1 is a diagram illustrating the principle of the present invention. FIG.
1A shows a DC characteristic test circuit 1 according to the present invention, which includes terminals for receiving two control signals Ca and Cb, terminals for receiving input signals Ia to In, and input signal Ia.
and terminals for sending output signals Oa to On for a to In.

FIG. 1B is a timing chart for explaining the operation of the DC characteristic test circuit 1 of FIG. 1A. In FIG. 1B, while the two control signals are both "L", the input signals Ia and Ib are directly output as the output signals Oa and Ob. When the two control signals both become "H", the output signals Oa and Ob are determined by the state of the DC characteristic test circuit 1 at that time, and here whether "H" or "L" is undefined.

At the timing indicated by the alphabetical character T1 in FIG. 1B, a pulse appears in the control signal Ca. At this time, the DC characteristic test circuit 1 is in the initial state, and the output signals Oa to
On is forcibly set to “H” or “L”. FIG.
In (b), as can be seen from the output signals Oa and Ob,
It is "L" in the initial state. Subsequently, each time a pulse appears in another control signal Cb, each output signal Oa
On is forcibly inverted from “H” to “L” or from “L” to “H”. The output signals Oa and Ob are inverted from "L" to "H" at the timing indicated by the alphabetical letter T2 in FIG.
Ob is inverted from “H” to “L”.

As a matter of course, in the timing chart of FIG. 1B, even if the logic of the control signals Ca and Cb is reversed, if the circuit configuration is adjusted to the reverse logic, the same between the input signal and the output signal. Needless to say, the above relationship can be easily generated.

[0013]

FIG. 2 is a diagram for explaining an embodiment of the present invention. FIG. 2A illustrates where in the semiconductor device the DC characteristic test circuit 9 according to the present invention is provided. When the semiconductor device is roughly divided into an input section 7 including an input pin, an output section 10 including an output pin, and an internal circuit section 8, as shown in FIG. It is provided in a stage preceding to 10.

FIG. 2B shows a configuration example of the DC characteristic test circuit 9 according to the present invention and a schematic configuration of the LSI 11 which is a semiconductor device. 2 to the DC characteristic test circuit 9
At the same time as two control signals are sent from the two input pins 12 and 13 and four input signals are sent from the internal circuit unit 8, output signals for each input signal are sent from the DC characteristic test circuit 9 to the output pins 14 to 17. Has been sent.

When the two control signals are both "L", A
Since the output of the ND circuit 20 is “1” and the output of the AND circuit 21 is “0”, the input signal to the DC characteristic test circuit 9 becomes the output signal as it is. Further, when both of the control signals become “H” and a pulse signal of “L” is transmitted to the input pin 12 thereafter, the two FF circuits 18 and 19 are cleared to be in an initial state. At this time, since the output of the AND circuit 20 is "0", the outputs of the four AND circuits 22 to 25 are "0", and at the same time, the output of the AND circuit 21 is also "0". The output is also "0".

Since the output of the AND circuit 20 does not become "1" unless the two control signals both become "L", the outputs of the four AND circuits 22 to 25 maintain the state of "0". Therefore, the output signal of the DC characteristic test circuit 9 is determined by the output of the AND circuit 21.

As shown, two FF circuits 18, 1
9, the AND circuit 21 sets the output to “0”.
From “1” to “1” or from “1” to “0”. Since each of the two FF circuits 18 and 19 is inverted each time a pulse signal applied to the input pin 13 is received, each output signal of the DC characteristic test circuit 9 is set to “H” or “H” by transmitting the pulse signal to the input pin 13. It can be "L".

[0018]

As described above, according to the present invention,
"H" level and "L" level are applied to the output terminal of the semiconductor device.
Since the level potential can be easily set, V _OH
There is an advantage that the _VOL test can be performed easily and in a short time.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

[Explanation of symbols]

 1, 2, 18, 19 FF circuit 3 to 5, 20 to 25 AND circuit 6, 26 to 29 OR circuit 7 Input unit 8 Internal circuit unit 9 DC characteristics test circuit 10 Output unit 11 LSI 12, 13 Input pin 14 to 17 Output pin

Claims (1)

(57) [Claims] In a semiconductor device test, a test circuit is provided between an internal circuit unit and an output unit of a semiconductor device and outputs a predetermined signal in response to an input signal. In response, when a pulse of one control signal is detected, the state becomes an initialization state. Regardless of what kind of input signal is received from the internal circuit unit, a high level or a low level is determined. A DC characteristic test characterized by outputting a signal to an output unit and inverting an output from the output unit from a high level to a low level or from a low level to a high level each time a pulse of another control signal is detected. circuit.