JPS63236358A - Semiconductor device - Google Patents

Abstract

PURPOSE:To conductive to be able to form thinner by about 1/3 a P<-> GaAs collector layer than that in the conventional structure without deteriorating breakdown strength of a base-collector by a method wherein the P<-> GaAs collector layer of a two-dimensional electron gas heterobipolar transistor (2DEG- HBT) is permuted to a P<-> AlxGa1-xAs layer. CONSTITUTION:For example, a P<+> GaAs layer 41 (collector layer) containing Be of 1X10<19>cm<-3>, a P<-> AlxGa1-xAs (x-0.3) layer 50 containing Be of 10<15>cm<-3>, an undoped GaAs layer 42, an N-type AlyGa1-yAs (y-0.3) layer 43 containing Si of 4X10<18>cm<-3>, an AleGa1-eAs layer 45 containing Be of 1X10<17>cm<-3> and moreover, a P<+> (Be-10<19>cm<-3>) GaAs layer 45' are respectively formed on a semi-insulative GaAs substrate 40 in 4000 Angstrom , 1000 Angstrom , 100 Angstrom , 250 Angstrom , 2000 Angstrom and 1000 Angstrom using an MBE (molecular beam epitaxy) method. After that, after an emitter region, a base region and an interelement isolation region are formed by a normal method, a metal emitter electrode 25, a metal base electrode 24 and a metal collector electrode 26 are each formed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a bipolar transistor using a two-dimensional assembly in the base layer, and in particular to a bipolar transistor suitable for improving the base-collector breakdown voltage or the cut-off frequency fT. Regarding two-dimensional electron gas hetero-bipolar transistors.

[Conventional technology]

We have developed an HBT with a new structure (generally referred to as 2DEC-HBT) using a two-dimensional carrier formed at the heterojunction interface between gallium arsenide (GaAs) and aluminum gallium arsenide (AQzGal-xAs) as the base layer. Patent applications have already been filed (Japanese Patent Application No. 164126/1980, 164128/1980, 40244/1982)
.

In addition, these applications disclose, in JP-A No. 60-134479, a junction type gate structure (as shown in Fig. 5-6 of the same publication, the gate is of P type A Q Ga As or Ga
It can also be said to be a bipolar transistor based on a new principle that uses the unique action of the case (corresponding to the case of A s).

The transistors described in the above patent applications are collectively referred to as 2DEG-HBT.

The present invention relates to an improvement of the 2DEC-HBT with respect to the structure of the 2DEG-HBT that provides a high breakdown voltage between base and collector and a high cutoff frequency.

[Problem that the invention seeks to solve]

In the structure of the above patent application, G.a.A.s.

When a two-dimensional electron gas at the A Q Ga As heterointerface is used as the base, the base-collector transit time t is given by: However, Dn is the base diffusion coefficient of holes W
B is the base film thickness Xn, and collector film thickness V3 is the hole saturation velocity. The first term on the right side is the transit time of the two-dimensional electron layer, which is approximately 0.
, 05 psec, and the second term is approximately 1.50 psec when the number of P″-GaAs collector layers is 3000.

That is, t is almost entirely dominated by the p″″G a As collector transit time.

In order to further reduce t, the most effective method is to make the p--GaAs collector layer thinner (x, → smaller), but in the case of a conventional 2DEG-HBT, the lower limit is 1500 to 2000. If the p-type collector layer can be made thinner to about 700 to 1000 layers, t can be reduced from the conventional 1.55 psec to 0.
．． It can be reduced to about 1/3 of 55 psec.

It is impossible to realize such a thin collector layer (700 to 1000 people) with a normal HBT, and in this case,
Although the pnp type 2DEG-HBT is a pnp type, it is about three times faster than a normal npn type HBT.

[Means for solving problems]

The above purpose is to convert the p-type GaAs collector layer into p
This can be achieved by replacing it with a -type AΩx Gal-X As layer.

Figure 1 shows the device cross-sectional structure of the 2DEG-HBT of the present invention (
An energy band diagram (FIG. 1(b), ((1)') corresponding to FIG. 1(a)) is shown. 40 is a semi-insulating GaAs substrate, and 41 is a P-type GaAs.

50 is p""" type AA xG a t-xA g (P type doping level is approximately 101 to 1017aa'")
)', 42 is undoped GaAs and has a film thickness of about 100 to 150 layers.

43 is n-type AQGaAs, 45 is p-type AQGaAa (or GaAs), and 24, 25, and 26 are base electrode metal, emitter electrode metal, and collector electrode/pole metal, respectively. 59 indicates a two-dimensional electron gas (20EG).

In addition, p-type AQ, xG a 1-xA s 50 has a graded AQ composition,
It is also possible to make the energy band diagram as shown in FIG. 1 (Q). That is, the AQ composition X on the 2DEG side is made thicker (0,
2 to 0.45) P+: Make the I-rector layer side X smaller (~0.45)
0) is also possible.

[Effect]

By making the p-type collector layer p-type A Q GaAs in this way, when a potential is applied between the base and collector (1) the avalanche breakdown voltage of AI2GaAs is Ga
A Q G a A
2DEC remains undisappeared up to high base-collector voltages because it is difficult to dissipate due to the heterojunction barrier of s.

That is, at the same base-collector voltage, the P-type collector layer 50.50' is made thinner than before (700 to 10
00 people), so the conventional 1ntrivoic f
It is possible to realize a value that is approximately three times as large as t, and it is possible to achieve a high speed that is approximately three times that of the conventional npn type HBT.

〔Example〕

The present invention will be explained in more detail below through examples.

Example 1 Figure 1 (a) shows Ga As / A Q Ga
PNP type 2DEG-HBT using A s Helaro junction
This is a prototype example.

MBE (Molecular Beam Epitaxy) on semi-insulating GaAs40 substrate
xy) method to prepare a small G a A 541 (collector layer) containing Be at 4000 A
P-type AnxGaz containing 1QLIs B e
−xAs(x~0.3)50 to 1000, undoped GaAs42 to 100, Si to 4×10”am
-” containing n-type Al2yGat-yAs (y~0.3
) 43 to 250 people.

A Q EG containing Be I X 1017am-8
2000 people with a t-pA s45 and P+ type (B
e ~101gcm-8) Ga As 41 to 10
Format 00 people. Thereafter, after forming an emitter region, a base region and an inter-element isolation region by a normal method, an emitter electrode metal 25 (AuRn/Au) and a base electrode metal 24 (
A collector electrode metal 26 (AuGe/Ni/Au) (AuRn/Au) was formed.

In order to improve the propagation of holes through the p-type AQGaAs layer 50, the AQ composition ratio X may be graded as shown in FIG. 1(c). That is, p-type G a A
s collector [X = O, O on the 41 side, x on the 2DEG side
= 0.35, and the AQ composition ratio between them was changed in a connected manner.

The doping level of P-type AΩGaAs45 is usually used in the range of 1×10 17 to 5×10”−8 depending on the purpose.

Example 2 FIGS. 2(a) and 2(b) show an example in which an HBT and a FET were fabricated on the same substrate.

For the same two-layer wafer as in Example 1, 2DEG-HBT
can be formed in the same manner as in Example 1. On the other hand, 2DEG is F
E T (Field Effect Transis
for), the source/drain electrodes 20.21 are A u G s / N i / A
A u Rn is formed on the n-type A Q Ga As layer 43 using A u Rn as the junction type gate electrode metal 22.
/Au was used to form a 2DEG-FET.

In Fig. 2(a), the 2DEG-FET part is DE
The G-HBT portion is indicated by B.

Furthermore, since 2DEG-FETs often use a Schottky junction type gate structure, in that case, a P-type emitter 145.45' is used as shown in part A of FIG. 2(b).
Schottky gate metal 22' (for example, T i / P t / A u ).

A n + W S x, etc.) is formed.

The threshold value V th of the FET part is A Q G a A
The film thickness is determined by adjusting it by etching or the like, as in conventional FETs.

The doping level of the p-type AQ, GaAs layer 45 is usually 1×10170−δ to lXIO20■ depending on the purpose.
-3 is often used.

In the above example, Ga As / A Q Ga
Although the case of the A s heterozygous system has been described, other binary/ternary heterozygous systems, such as G a A s / G
e.

AQGaAs/Ge, InAllAs/InGaAs
A two-dimensional carrier is also formed in a heterojunction such as +I n Ga As P / I n P. A similar effect can be obtained by replacing the conventional collector layer with a semiconductor heterojunction having a wide forbidden band as in the present invention.

Also, in the above embodiments, n-type and P-type are replaced (Si and B
(replace e) and two-dimensional hole gas (Two Dime
A similar invention can be carried out using the national Hole Ga5).

〔Effect of the invention〕

According to the present invention, the p-type collector layer can be made approximately 1/3 thinner than the conventional structure without deteriorating the base-collector breakdown voltage.
JT (gut-off frequency) approximately 3 times higher than pn-type HBT
I was able to realize this.

Furthermore, a pnp type 2DEG-HBT and a 2DEC-FET could be formed on the same substrate in a natural manner.

[Brief explanation of the drawing]

FIG. 1(a) is a cross-sectional structure diagram of a transistor according to a first embodiment of the present invention for explaining the present invention, FIG. 1(b) and (Q) are its energy band diagrams, and FIG. 2 is an embodiment of the present invention. 2
FIG. 2 is a cross-sectional structural diagram when a pnp type 2DEG-HBT and a 2DEG-FET are formed in the same substrate. 20.21... Source/drain electrode metal, 22.
...j-FET gate electrode metal, 22'... Schottky gate metal, 24... base electrode metal, 2
5... Emitter electrode metal, 26... Collector electrode metal, 40... Semi-insulating GaAs substrate, 41...
p + G a As , 42-undoped G a
As, 43-n A Q Ga As, 45
-pAQGaAs,50=-p-AQG
aAs, 50'-graded p-A 17.
GaAs, 59...2DEG. Figure 1Figure 1

Claims (1)

[Claims] 1. A semiconductor layer I with a wide energy gap, a semiconductor layer II with a narrower energy gap, a two-dimensional carrier formed at the heterojunction interface between the two, and the semiconductor layer
an electrode electrically connected to the semiconductor layer I, a semiconductor layer III having a wider energy gap than the semiconductor layer II and having a heterojunction with the semiconductor layer II, and the semiconductor layer formed in contact with the semiconductor layer I. A semiconductor layer IV of a conductivity type opposite to I,
A semiconductor device having electrodes electrically connected to the semiconductor layers III and IV, respectively.