JP2834172B2 - Field effect transistor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor in which a conductive type active layer and an opposite conductive type buried layer are formed by epitaxial growth.

[Conventional technology]

Compound semiconductor MES (Metal Semiconductor: M eta
l S emiconductor) FET (field Efuekuto transistors: Field in Effect Transistor), for improving the suppression and pinch-off characteristics of the short channel effect, as an example of providing a buried p layer below the n-type active layer, Technical Disclosure 81
-4352 and JP-A-60-27173.

[Problems to be Solved by the Invention] By the way, the active layer provided with the buried p-layer has a problem that the impurity density in the active layer increases and the carrier mobility decreases. This is due to the fact that, in addition to the donor impurity for generating a normal carrier, the active layer contains an acceptor impurity diffused from the buried p-layer into the active layer and a donor impurity added for compensating the acceptor impurity.

For example, undoped GaAs has an electron mobility of about 8500 at room temperature.
is a cm ² / V · S, about 4200cm ² / V · in the active layer of the FET
If S and a buried p-layer are provided, it is reduced to about 3300 cm ² / V · S.
Approximately 1500-2 for FETs with both active and buried p-layers thinned
It may drop to 500 cm ² / V · S.

A decrease in mobility is a problem because it hinders the speeding up of the FET. However, conventionally, even if the buried p-layer lowers the carrier mobility, the speed of the FET can be increased if the gate length can be reduced by the effect of suppressing the short channel effect by the buried p-layer. No measures have been taken.

That is, the buried p-layer has the effect of suppressing the short channel effect and shortening the gate length, and the shortening of the gate length speeds up the FET and lowers the mobility due to the buried p-layer. However, since the speed of the FET is generally increased, the decrease in the mobility has been conventionally ignored.

However, it is clear that higher mobility is preferable for speeding up the FET. An object of the present invention is to provide an FET in which the carrier mobility of an active layer provided with a buried p-layer is improved.

[Means for solving the problem]

In the present invention, an undoped layer (a layer that is not intentionally doped) is inserted between an active layer of one conductivity type and a buried layer of the opposite conductivity type in order to improve the mobility of the carrier.

[Action]

The operation of the present invention will be described with reference to an example in which the active layer is an n-type. Although the interface between the n-type active layer and the buried p-layer is depleted by the pn junction, since the p-layer acceptor and the n-layer donor are included, the impurity density is high and the carrier mobility is high. Low. Therefore, if an undoped layer having high mobility is used, the speed of the FET can be increased.

The pn junction generates a pn junction capacitance and acts as a parasitic capacitance to the FET. However, a structure in which an undoped layer is interposed can reduce the parasitic capacitance.

However, if the thickness of the undoped layer is small, the effect of the undoped layer is not obtained due to the diffusion of impurities from the active layer and the buried p-layer. Therefore, the thickness of the undoped layer is preferably 5 to 20 nm.

Operation in the ON state of the FET is divided into a linear region and a saturation region. In the linear region, most of the carriers flow in the active layer, and the present invention has no effect. In the saturation region, the current is limited to a substantially constant value by the depletion layer extended by the electric field between the gate and the drain, but the depletion layer extends to the bottom of the channel (the state where the gate voltage is slightly higher than the threshold voltage). Then, the effect of the present invention appears. The situation at this time is shown in FIG. (A) is a conventional FET, and (b) is a case of the present invention. Arrows indicate the flow of electrons. In (a), the electrons flowing from the source are pushed to the interface between the active layer and the p-layer and head toward the drain. In (b), the middle is an undoped layer, and electrons in the undoped layer can move at high speed.

FIG. 5 shows FET characteristics. The threshold voltage is about 0V.
(A) shows the relationship between the drain current and the drain voltage, (b) shows the relationship between the drain current and the gate voltage, and (c) shows the relationship between the conductance (gm) and the gate voltage. In each case, the broken line is the conventional FET, and the solid line is the F of the present invention.
ET.

(A) has the effect of increasing the saturation current in the region where the gate voltage is low, and (b) has the effect of increasing the rise and fall of the current near the threshold. FET performance is determined by its ability to supply current to the load,
According to the present invention, it is possible to improve the performance where the gate voltage is near the threshold. (C) shows the situation.

〔Example〕

Hereinafter, a GaAs MESFET will be described as an embodiment of the present invention with reference to FIG.

It is possible to use other compound semiconductors, MESFET
Besides, J (Jiyankushiyon: J unction) FET, DMT
(Doputochiyaneru metal Inshiyureta transistor: D oped-channel M etal Insulator T ransist
or), IG (in Shiyu Lethe each time gate: I nsulated
G ate) it is also applicable in FET or the like.

FIG. 1 shows an example in which the n + layer 5 is formed by ion implantation, and FIG. 2 shows an example in which the n + layer 5 is formed by epitaxial growth. In both cases, i-GaAs 3 is provided between the active layer 2 and the p-layer 4.
It is a feature of the present invention that is sandwiched by about 7 nm.

The reason why the thickness of i-GaAs3 is set to 7 nm is that n = 2 × 10 ¹⁸ cm ⁻³ .
This is because the thickness of the depletion layer extending toward the n-layer when the layer is in contact with the 3 × 10 ¹⁶ cm ⁻³ p-layer is about 7 nm. At this time, the thickness of the depletion layer extending to the p-layer side is about 25 nm. If the undoped layer is in contact with the n-layer, the depletion layer extending to the n-layer is of a negligible size.

The manufacturing process will be described with reference to FIG. 1 as an example.

MBE (Molecular Beam Epitaxy: Molecular Be
am Epitaxy) on a semi-insulating GaAs substrate.
Buffer layer 1 of about 700 nm and Be ions of about 3 × 10 ¹⁶ cm ⁻³
N-Ga doped with about 300 nm of doped p-GaAs4, about 7 nm of i-GaAs3, and doped with about 2 × 10 ¹⁸ cm ⁻³ of Si ions as an active layer.
As2 is grown to about 30 nm.

Except for the active layer of the FET, or the part that becomes the diode and the resistive layer, the other area is wet-etched with a mixed solution of hydrofluoric acid and hydrogen peroxide 1: 2 until the p-GaAs4 is completely exposed. .

On this, WSi as a heat-resistant gate is vapor-deposited with a sputter to a thickness of about 200 nm, and then the gate 6 is processed by lithography and dry etching. Other materials can be used for the gate 6, and a composite gate in which several materials are stacked can be used.

After about 150nm deposited SiO _2, only the side surface of the gate leaving a SiO ₂ to Si + ions SiO ₂ side as a mask 75 keV 5
The present invention is completed by implanting under the condition of × 10 ¹³ cm ⁻² and performing activation annealing at 800 ° C. for 15 minutes to form an ohmic electrode (AuGe / Ni) 7.

 Another embodiment of the present invention is shown in FIGS.

In FIG. ₂ , n +
-GaAs5 is selectively epitaxially formed by MOCVD (metal organic chemical vapor deposition) to form an n + layer, and then an ohmic electrode 7 is formed.

FIG. 3 shows another semiconductor 8 having a large energy forbidden band between the gate 6 and the active layer 2 in order to improve the shot key characteristics.
Is formed in a heterojunction structure. The manufacturing process will be described below.

Approximately 700 n of i-GaAs1 was grown on a semiconductor substrate by MBE growth.
m, Be-doped (3 × 10 ¹⁶ cm ⁻² ) p-GaAs4 at about 300 nm, i
About 7 nm of GaAs3, Si-doped (3 × 10 ¹⁸ cm ⁻³ ) n-GaAs2
About 15 nm, undoped AlGaAs 8 is grown to about 11 nm, the p-GaAs 4 is exposed by wet etching in the portions other than the active layer, the gate 6 is processed, and SiO _{2 is formed} to about 150 nm by normal pressure CVD (chemical vapor deposition). ). This SiO ₂ is removed by dry etching while leaving only the gate side surfaces, and undoped AlGaAs 8 is removed by using the SiO ₂ remaining on the gate side surfaces as a mask to expose n-GaAs 2 and to form n + -GaAs 5 by selective growth by MOCVD. Then, by attaching the ohmic electrode 7 and wiring, the FET according to the present invention in the case of a hetero junction is completed.

As the undoped AlGaAs 8, other semiconductors or insulators can be used, and the undoped AlGaAs 8 can be removed by using the gate 6 as a mask instead of SiO _{2 on the} side surface of the gate.

Undoped AlGaAs 8 may be a homojunction as i-GaAs 8. In this case, the i-GaAs 8 must be as thin as 1 to 3 nm, but has an effect of improving the gate's shot key characteristics and acting as a protective film of the active layer, so that the height of the active layer can be increased without deteriorating the gate's shot key characteristics. It is possible to reduce the concentration.

As another embodiment of the present invention, a p-channel GaAs MESFET having the same device structure as that of FIG. 2 and using p-GaAs for the active layer 2 and i-GaAs for the undoped layer 3 is exemplified.

Although hole mobility at room temperature of GaAs is about 420cm ² / V · S, Ge is 1900cm ² / V · S and more than four times faster. This FET is so-called because the channel is not an inversion type and does not use a two-dimensional electron (hole) gas, and the conductive layer 2 is not an electron (hole) supply layer to the channel but a channel. HEMT (high Electron Mobiritei transistor: H igh E lectron M obility T ransistor) , rather than a MESFET, a hole only operate in the saturation region improves the conductance through the high i-GaAs 3 medium mobility. In this case, the buffer layer 1 is composed of n-GaAs and a source. The drain 5 is formed as p + -GaAs.

〔The invention's effect〕

The operation of the FET in the saturation region is governed by the electron saturation speed. Electrons take a saturation velocity near the drain end of the gate, but the depletion layer from the gate extends most in this region, and electrons in this region pass through the interface between the active layer and the p-layer. The present invention has an effect of increasing the electron saturation speed by using this region as an undoped layer and improving the conductance of the FET.

In addition, the parasitic capacitance generated between the active layer and the buried p-layer has the effect of being reduced by the undoped layer. In addition, since another semiconductor having high mobility can be included in the undoped layer, the conductance can be further improved in this case.

[Brief description of the drawings]

1 to 3 are cross-sectional views of a GaAs MESFET according to an embodiment of the present invention, FIGS. 4a and 4b are cross-sectional views of an element for explaining the principle of the present invention, and FIG. FIG. 4 is a characteristic diagram of the MESFET to be described. 1. Semiconductor substrate or buffer layer 2. Active layer (n-
GaAs), 3 ... i-GaAs, 4 ... p-GaAs, 5 ... n + -GaAs
s, 6: gate electrode, 7: source. Drain electrode, 8 ... u
n-AlGaAs or insulator.

────────────────────────────────────────────────── ─── Continuation of front page (56) References JP-A-1-201914 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/337-21/338 H01L 27 / 095 H01L 27/098 H01L 29/775-29/778 H01L 29/80-29/812

Claims (2)

(57) [Claims] An active layer of one conductivity type, a gate electrode located on one surface side of the active layer, and a semiconductor layer of the opposite conductivity type located on the other surface side of the active layer. An undoped semiconductor layer formed between the opposite conductivity type layer and the active layer in contact with these layers, and the thickness of the active layer is
The portion facing the gate electrode is thinner, the source and drain portions on both sides of the portion facing the gate electrode are thicker, and the undoped layer is the gate electrode, the gate electrode in the source and the drain. Wherein the undoped layer has a thickness of 20 nm or less. 2. The field effect transistor according to claim 1, further comprising an undoped semiconductor layer formed between said active layer and said gate electrode.