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JPS6321855A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6321855A
JPS6321855A JP16712386A JP16712386A JPS6321855A JP S6321855 A JPS6321855 A JP S6321855A JP 16712386 A JP16712386 A JP 16712386A JP 16712386 A JP16712386 A JP 16712386A JP S6321855 A JPS6321855 A JP S6321855A
Authority
JP
Japan
Prior art keywords
contact hole
film
conductive material
semiconductor device
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16712386A
Other languages
Japanese (ja)
Inventor
Mitsuyoshi Nakamura
充善 中村
Isao Furuta
古田 勲
Hidefumi Kuroki
黒木 秀文
Hajime Arai
新井 肇
Masaaki Ikegami
雅明 池上
Eisuke Tanaka
英祐 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16712386A priority Critical patent/JPS6321855A/en
Publication of JPS6321855A publication Critical patent/JPS6321855A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To reduce the difference of the thickness between the electrode wirings out of a contact hole and the film thereby to improve the uniformity of the film thickness of the electrode wirings by increasing the thicknesses of the wirings to become equal on the side and the bottom of the hole. CONSTITUTION:A contact hole 6b is formed in an insulating film 3 on a semiconductor substrate 1, and a first conductive material 4e is buried to cover it. Then, it is so etched as to allow a conductive material 4h to remain in the bottom of the hole 6b. Then, a second conductive material 4c is so buried as to cover the hole 6b, and etched to so form electrode wirings 4d as to increase the thickness of the film in the hole 6b. Thus, the difference of the thickness between electrode wirings 4i and electrode wirings 4c is reduced to improve the uniformity of the thickness of the film of the whole wirings 4d.

Description

【発明の詳細な説明】 [産業上の利用分野コ この発明は半導体装置の製造方法に関し、特に、コンタ
クトホール内部での電極配線の膜厚を改良できるような
半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device that can improve the thickness of electrode wiring inside a contact hole.

[従来の技術] 第8図は従来の半導体装置のコンタクトホール部分にお
ける概略断面構造を示す図である。
[Prior Art] FIG. 8 is a diagram showing a schematic cross-sectional structure of a contact hole portion of a conventional semiconductor device.

第8図において、シリコン基板1上には、CVD法によ
り成長させたPSG膜3が形成され、フォトレジスト膜
を用いてPSG膜3を選択除去してコンタクトホール6
が形成されている。このコンタクトホール6を覆うよう
にスバンタ法によって金属アルミニウム膜を成長させ、
フォトレジスト膜を用いて金属アルミニウム膜を選択除
去することによって、電極配線4が形成されている。さ
らに、その上にレジスト膜5が形成される。
In FIG. 8, a PSG film 3 grown by the CVD method is formed on a silicon substrate 1, and a contact hole 6 is formed by selectively removing the PSG film 3 using a photoresist film.
is formed. A metal aluminum film is grown by the Svanta method so as to cover this contact hole 6,
The electrode wiring 4 is formed by selectively removing the metal aluminum film using a photoresist film. Furthermore, a resist film 5 is formed thereon.

[発明が解決しようとする問題点] 従来の半導体装置において、コンタクトホール6の内壁
部での電極配線4aの膜厚と、コンタクトホール6の外
部での電極配線4bの膜厚とを比較すると、電極配線4
aの膜厚が著しく薄くなっている。このため、電極配線
4に流れる電流が増大した場合、エレクトロマイグレー
ションなどにより、断線を生じ、半導体装置の動作の信
頼性が低下するなどの問題点があった。
[Problems to be Solved by the Invention] In a conventional semiconductor device, when comparing the thickness of the electrode wiring 4a on the inner wall of the contact hole 6 with the thickness of the electrode wiring 4b outside the contact hole 6, Electrode wiring 4
The film thickness of a is significantly thinner. For this reason, when the current flowing through the electrode wiring 4 increases, electromigration causes wire breakage, resulting in problems such as a decrease in the reliability of the operation of the semiconductor device.

それゆえに、この発明の主たる目的は、コンタクトホー
ル内部での電極配線の膜厚を厚膜化し得るような半導体
装置の製造方法を提供することである。
Therefore, a main object of the present invention is to provide a method of manufacturing a semiconductor device that can increase the thickness of electrode wiring inside a contact hole.

[問題点を解決するための手段] この発明は半導体装置の製造方法であって、第1のステ
ップにおいて、半導体基板上の絶縁膜にコンタクトホー
ルを形成し、このコンタクトホールを覆うように第1の
導電性材料を埋込む。第2のステップにおいて、コンタ
クトホールの底部にのみ第1の導電性材料が残るように
エツチングし、第3のステップにおいてコンタクトホー
ルを覆うように第2の導電性材料を埋込む。そして、第
4のステップにおいて、第1の導電性材料をエツチング
して、コンタクトホール内部での膜厚を厚膜化するよう
に電極配線を形成する。
[Means for Solving the Problems] The present invention is a method for manufacturing a semiconductor device, in which in a first step, a contact hole is formed in an insulating film on a semiconductor substrate, and a first film is formed so as to cover the contact hole. embed conductive material. In a second step, the first conductive material is etched so as to remain only at the bottom of the contact hole, and in a third step, a second conductive material is buried to cover the contact hole. Then, in a fourth step, the first conductive material is etched to form electrode wiring so as to increase the film thickness inside the contact hole.

[作用コ この発明に係る半導体装置の製造方法では、コンタクト
ホールの側面および底面における電極配線の膜厚が等し
くなるように厚膜化するようにしたので、コンタクトホ
ール外部の電極配線の膜厚との差を小さくでき、電極配
線の膜厚の均一性を向上できる。
[Function] In the method for manufacturing a semiconductor device according to the present invention, the thickness of the electrode wiring on the side surface and the bottom surface of the contact hole is increased so that it is equal in thickness, so that the thickness of the electrode wiring outside the contact hole is equal to the thickness of the electrode wiring on the outside of the contact hole. The difference in thickness can be reduced, and the uniformity of the film thickness of the electrode wiring can be improved.

[発明の実施例コ 第1図ないし第7図はこの発明による各製造工程におけ
る半導体装置の断面図である。
Embodiment of the Invention FIGS. 1 to 7 are cross-sectional views of a semiconductor device in each manufacturing process according to the invention.

まず、第2図に示すように、シリコン基板1の上に、C
VD法により成長されたPSG膜3を形成する。そして
、フォトレジストマスクを用いて、PSG膜3を選択除
去してコンタクトホール6bを形成する。このコンタク
トホール6bを覆うようにPSG膜3上に、スパッタ法
によってアルミ膜4eを成長させる。さらに、アルミ膜
4e上にレジスト膜5を形成する。
First, as shown in FIG.
A PSG film 3 grown by the VD method is formed. Then, using a photoresist mask, the PSG film 3 is selectively removed to form a contact hole 6b. An aluminum film 4e is grown by sputtering on the PSG film 3 so as to cover this contact hole 6b. Furthermore, a resist film 5 is formed on the aluminum film 4e.

次に、第3図に示すようにエッチバック法により、レジ
スト膜5をエツチングして、コンタクトホール6b内に
のみレジストパターン5aを形成する。次に、第4図に
示すように、レジストパターン5aをマスクにして、ア
ルミ膜4eを異方性エツチングしてアルミパターン4f
を形成する。
Next, as shown in FIG. 3, the resist film 5 is etched by an etch-back method to form a resist pattern 5a only in the contact hole 6b. Next, as shown in FIG. 4, using the resist pattern 5a as a mask, the aluminum film 4e is anisotropically etched to form an aluminum pattern 4f.
form.

さらに、第5図に示すように、レジストパターン5aを
除去し、アルミ膜4eの突起物4gを等方性エツチング
により除去し、第6図に示すようなアルミパターン4h
をコンタクトホール6bの底部にのみ形成する。さらに
、第7図に示すように、PSG膜3およびアルミパター
ン4h上に、スパッタ法によりアルミ膜4Cを形成し、
フォトレジストマスクを用いて、上述のアルミ膜4cを
選択除去することにより、第1図に示すような電極配線
4dを形成する。
Furthermore, as shown in FIG. 5, the resist pattern 5a is removed, and the protrusions 4g of the aluminum film 4e are removed by isotropic etching, resulting in an aluminum pattern 4h as shown in FIG.
is formed only at the bottom of contact hole 6b. Furthermore, as shown in FIG. 7, an aluminum film 4C is formed on the PSG film 3 and the aluminum pattern 4h by sputtering,
By selectively removing the aluminum film 4c using a photoresist mask, an electrode wiring 4d as shown in FIG. 1 is formed.

上述のごとく、コンタクトホール6bの底部に予めアル
ミパターン4hを埋込んモいるため、第1図においてコ
ンタクトホール6b内の電極配線41の膜厚が厚くなり
、コンタクトホール6b外の電極配線4cの膜厚との膜
厚差は、前述の第8図に示した電極配線4aと4bとの
膜厚差よりも小さくなり、電極配線全体の膜厚の均一性
が向上する。
As mentioned above, since the aluminum pattern 4h is buried in the bottom of the contact hole 6b in advance, the film thickness of the electrode wiring 41 inside the contact hole 6b becomes thicker in FIG. 1, and the film thickness of the electrode wiring 4c outside the contact hole 6b increases. The difference in film thickness between the electrode wirings 4a and 4b shown in FIG. 8 described above is smaller than that between the electrode wirings 4a and 4b, and the uniformity of the film thickness of the entire electrode wiring is improved.

なお、上述の実施例では、コンタクトホール6bの埋込
みを導電性材料および電極配線材料として、金属アルミ
ニウムを利用した場合について説明したが、これに限る
ことなくアルミニウム合金や金属ンリサイドを導電性材
料あるいは電極配線材料として使用することも可能であ
り、コンタクトホール6b内部の電極配線の膜厚の厚膜
化に対して同様の効果を奏することができる。
In addition, in the above-mentioned embodiment, a case was explained in which metal aluminum was used as a conductive material and an electrode wiring material to fill the contact hole 6b. It can also be used as a wiring material, and the same effect can be achieved for increasing the thickness of the electrode wiring inside the contact hole 6b.

[発明の効果] 以上のように、この発明によれば、コンタクトホールの
底部に予め導電性材料を埋込み、その上に電極配線を形
成するようにしたため、コンタクトホール内部での電極
配線の膜厚が厚くなり、コンタクトホール内部および外
部における電極配線の膜厚差を減少でき、電極配線の膜
厚が局所的に薄い場所が減少し、エレクトロマイグレー
ションなどによる電極配線の断線による半導体装置の動
作の信頼性の低下を防止できる。
[Effects of the Invention] As described above, according to the present invention, since the conductive material is buried in the bottom of the contact hole in advance and the electrode wiring is formed thereon, the film thickness of the electrode wiring inside the contact hole is reduced. This makes it possible to reduce the difference in the film thickness of the electrode wiring inside and outside the contact hole, reducing the number of locally thin areas of the electrode wiring, and reducing the reliability of semiconductor device operation due to disconnection of the electrode wiring due to electromigration, etc. It can prevent sexual deterioration.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図ないし第7図はこの発明による各製造工程におけ
る半導体装置の断面図である。第8図は従来の半導体装
置の断面図である。 図において、1はシリコン基板、2はポリシリコン、3
はPSG膜、4はアルミ配線、4dは電極配線、4eは
アルミ膜、4f、4hはアルミパターン、5はレジスト
膜、6bはコンタクトホールを示す。
1 to 7 are cross-sectional views of a semiconductor device in each manufacturing process according to the present invention. FIG. 8 is a sectional view of a conventional semiconductor device. In the figure, 1 is a silicon substrate, 2 is polysilicon, and 3 is a silicon substrate.
4 is a PSG film, 4 is an aluminum wiring, 4d is an electrode wiring, 4e is an aluminum film, 4f and 4h are aluminum patterns, 5 is a resist film, and 6b is a contact hole.

Claims (4)

【特許請求の範囲】[Claims] (1)半導体装置の製造方法であって、 半導体基板上の絶縁膜にコンタクトホールを形成し、該
コンタクトホールを覆うように第1の導電性材料を埋込
む第1のステップ、 前記コンタクトホールの底部にのみ前記導電性材料が残
るようにエッチングする第2のステップ、 前記コンタクトホールを覆うように第2の導電性材料を
埋込む第3のステップ、および 前記第1の導電性材料をエッチングして、前記コンタク
トホール内部での膜厚を厚膜化するように電極配線を形
成する第4のステップを含む、半導体装置の製造方法。
(1) A method for manufacturing a semiconductor device, comprising: forming a contact hole in an insulating film on a semiconductor substrate; and filling the contact hole with a first conductive material so as to cover the contact hole. a second step of etching so that the conductive material remains only at the bottom; a third step of burying a second conductive material so as to cover the contact hole; and a third step of etching the first conductive material. A method of manufacturing a semiconductor device, comprising a fourth step of forming an electrode wiring so as to increase the film thickness inside the contact hole.
(2)前記第1のステップは、前記第1の導電性材料の
上にレジスト膜を形成するステップを含み、 前記第2のステップは、前記コンタクトホール内にのみ
前記レジスト膜が残るようにエッチングした後、該残さ
れたレジスト膜をマスクにして、前記コンタクトホール
の底部にのみ前記第1の導電性材料が残るようにエッチ
ングし、該エッチング後に残されたレジスト膜を除去す
るステップを含む、特許請求の範囲第1項記載の半導体
装置の製造方法。
(2) The first step includes forming a resist film on the first conductive material, and the second step includes etching so that the resist film remains only in the contact hole. After that, using the remaining resist film as a mask, etching is performed so that the first conductive material remains only at the bottom of the contact hole, and removing the resist film left after the etching. A method for manufacturing a semiconductor device according to claim 1.
(3)前記第1の導電性材料は、アルミニウム、アルミ
ニウム合金および金属シリサイドのいずれかが用いられ
る、特許請求の範囲第1項または第2項記載の半導体装
置の製造方法。
(3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the first conductive material is aluminum, aluminum alloy, or metal silicide.
(4)前記第2の導電性材料は、アルミニウム、アルミ
ニウム合金および金属シリサイドのいずれかが用いられ
る、特許請求の範囲第1項記載の半導体装置の製造方法
(4) The method for manufacturing a semiconductor device according to claim 1, wherein the second conductive material is one of aluminum, aluminum alloy, and metal silicide.
JP16712386A 1986-07-15 1986-07-15 Manufacture of semiconductor device Pending JPS6321855A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16712386A JPS6321855A (en) 1986-07-15 1986-07-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16712386A JPS6321855A (en) 1986-07-15 1986-07-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6321855A true JPS6321855A (en) 1988-01-29

Family

ID=15843865

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16712386A Pending JPS6321855A (en) 1986-07-15 1986-07-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6321855A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01266718A (en) * 1988-04-19 1989-10-24 Fujitsu Ltd Production of semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157545A (en) * 1981-03-25 1982-09-29 Toshiba Corp Manufacture of semiconductor device
JPS57157544A (en) * 1981-03-25 1982-09-29 Toshiba Corp Manufacture of semiconductor device
JPS6194345A (en) * 1984-10-15 1986-05-13 Sumitomo Electric Ind Ltd Wiring method of integrated circuit
JPS61124154A (en) * 1984-11-20 1986-06-11 Nec Corp Manufacture of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57157545A (en) * 1981-03-25 1982-09-29 Toshiba Corp Manufacture of semiconductor device
JPS57157544A (en) * 1981-03-25 1982-09-29 Toshiba Corp Manufacture of semiconductor device
JPS6194345A (en) * 1984-10-15 1986-05-13 Sumitomo Electric Ind Ltd Wiring method of integrated circuit
JPS61124154A (en) * 1984-11-20 1986-06-11 Nec Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01266718A (en) * 1988-04-19 1989-10-24 Fujitsu Ltd Production of semiconductor device

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