JPS63164352A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS63164352A JPS63164352A JP30963786A JP30963786A JPS63164352A JP S63164352 A JPS63164352 A JP S63164352A JP 30963786 A JP30963786 A JP 30963786A JP 30963786 A JP30963786 A JP 30963786A JP S63164352 A JPS63164352 A JP S63164352A
- Authority
- JP
- Japan
- Prior art keywords
- capacitance
- terminal
- integrated circuit
- capacitance value
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 239000003990 capacitor Substances 0.000 abstract description 6
- 239000000758 substrate Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 238000001704 evaporation Methods 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000276 sedentary effect Effects 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔座業上の利用分野〕 不発明はデジタル信号により容量11!Lを制御する。[Detailed description of the invention] [Field of use in sedentary work] Uninvented capacity is 11 by digital signal! Control L.
可変容量ダイオードにおいて、それを構成する容量素子
の容量の電圧特性に関するものである。In a variable capacitance diode, it relates to the voltage characteristics of the capacitance of the capacitive element that constitutes the variable capacitance diode.
デジタル信号により容量値を制御する可変容量ダイオー
ドすなわちデジタルバラクタ−として、本発明者は第2
因に示す#成を提案した。すなわち信号入力端子21よ
り入り几デ“ジタル信号をデコーダ22で処理し、コン
トローラ23&−介してスイッチ24を制御して、複数
個ある例えばMOSコンデンサからなる容量素子25を
所望の容量値となる様に接続するものである。この場合
、端子17及び18を二端子素子として見た場合、端子
11に容量値を規定する為のコード信gk入力すること
により等動的な可変容量ダイオード、すなわちバラクタ
−ダイオード機能を有することになる。As a variable capacitance diode, that is, a digital varactor, whose capacitance value is controlled by a digital signal, the inventor has developed a second
We proposed the #structure shown in the above. That is, a digital signal input from a signal input terminal 21 is processed by a decoder 22, and a switch 24 is controlled via a controller 23 so that a plurality of capacitive elements 25, such as MOS capacitors, have a desired capacitance value. In this case, when terminals 17 and 18 are viewed as two-terminal elements, by inputting a code signal gk for specifying the capacitance value to terminal 11, an equidynamic variable capacitance diode, that is, a varactor, is connected. - It will have a diode function.
さらにま友、端子18を熾子11に接続し共通端子11
として扱えば2端子素子とすることができる。Furthermore, Mayu connects terminal 18 to Shiroko 11 and common terminal 11
If treated as , it can be made into a two-terminal element.
上述した発明の2端子としての例でに、この半導体集積
回路にさらに小型化ができるという利点がある0反面防
vI信号や雑音の問題を生じる。すなわち同調回路にチ
ェーニングバラクターダイオードとして用いた場合、目
的の周波数に・同調をとる為の容量1龜を規定する。デ
ジタル信号が印加されているときは、同調回路としては
1IIvIIA状態にあるとは云え、容量値t−m定す
るデジタル信号の電圧によりM OSコンデンサである
容量素子の容量が変化し、これによV高周波信号が変調
される。In the two-terminal example of the invention described above, although this semiconductor integrated circuit has the advantage of being able to be further miniaturized, it also causes problems with VI signals and noise. That is, when used as a chaining varactor diode in a tuning circuit, one capacitance is specified for tuning to the target frequency. When a digital signal is applied, although the tuned circuit is in the 1IIvIIA state, the capacitance of the capacitive element, which is an MOS capacitor, changes depending on the voltage of the digital signal that determines the capacitance value t-m. V high frequency signal is modulated.
これにより容量値を規定するデジタル信号が高周波信号
に対して防薔信号あるいは、雑音として作用することに
なる。周波数変調されたFM放送等の高周波信号ではも
ともと峻p4時に検波後ノイズが発生する為、これ金お
さえる目的でミ為−ティング回路を付加したものが多い
、しかし、振幅変調されたAM放送の場合は特に離調時
に検波後のノイズが発生することもないので、この場合
デジタル信号により高周波信号が変調され、検波後の音
声信号にノイズとなって現われS場合によっては耳ざわ
りになる。この原因に前述し九如く、容を値を規定する
デジタル信号の電圧により容量素子の容量値が変化し、
これが非線形素子として動作する為、目的とする高周波
信号が変調されるためである。As a result, the digital signal that defines the capacitance value acts as a protection signal or noise for the high frequency signal. Frequency-modulated high-frequency signals such as FM broadcasting originally generate noise after detection at steep p4, so in order to save money, many products have a metering circuit added to them.However, in the case of amplitude-modulated AM broadcasting, In this case, the high frequency signal is modulated by the digital signal and appears as noise in the detected audio signal, which may be harsh in some cases. As mentioned above, the reason for this is that the capacitance value of the capacitive element changes depending on the voltage of the digital signal that defines the capacitance value.
This is because the target high frequency signal is modulated because this operates as a nonlinear element.
不発8Aは上述の容量1[を規定するデジタル信号によ
り目的とする高周波信号が変調されることを防止する手
段を提供するものであり、本発明にかかわる半導体集積
回路を構成する容量素子の容量値が可変容量素子として
の全体の′4を値を規定するデジタル信号の電圧によV
、変化しない素子を用いることt−特徴としている。The misfire 8A provides a means for preventing the target high frequency signal from being modulated by the digital signal that defines the above-mentioned capacitance 1, and is the capacitance value of the capacitive element constituting the semiconductor integrated circuit according to the present invention. is V depending on the voltage of the digital signal that defines the value of the entire '4 as a variable capacitance element.
, it is characterized by the use of elements that do not change.
[実施例] 次に本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例金示す#成因である。FIG. 1 shows an embodiment of the present invention.
11は容量値を規定する為のコード信号を受ける入力端
子、12はそのコードを解読するデコーダ13は解読さ
れた情報をもとに複数のスイッチ14を制御するコント
ローラである。容量素子として容量値が電圧依存性をも
たないコンデンサ15が複数個並列ftc続される様に
なっており、どの容量素子を選択するかの切換をスイッ
チ14で行う。11 is an input terminal that receives a code signal for defining a capacitance value; 12 is a decoder 13 that decodes the code; and a controller that controls a plurality of switches 14 based on the decoded information. A plurality of capacitors 15 whose capacitance values do not depend on voltage are connected in parallel as capacitive elements, and a switch 14 is used to select which capacitive element to select.
並列接続された容量素子の一端を共通にしてカソード端
子17とし、他端をアノード端子18とするが、これa
コード信号を受ける入力端子1】に接続され、外部端子
はこの11と17である。ここで、それぞれの容量素子
はその容量値が電圧依存性をもたない構造のものを用い
る0本実施例では第3図に示す断面構造の容量素子を用
いる。半導体基板31上のS i Ox膜32上に蒸差
法により厚さ15μmのアルミニウム層33を設け、そ
の上KcVL)法に!り厚i5300OA(D S l
(h 11434を被層する。さらに又、蒸着法によ
り厚さL5μmのアルミニウム*35t−形成し、第1
のアルミニウム層を端子37、第2のアルミニウム層を
端子38とし、それぞれカソード、アノードとみなして
、第1図の端子17.スイッチ14へ接続される。この
構造はメタル−3lO!−メタル構造の容量素子となり
、容量値が電圧依存性をもつことはない。本発明による
1ロI変谷蓋ダイオ一ド機能を有する半導体集積回路を
チューニングバラクタ−ダイオードとして使用する場合
はチューニングを必要とする目的の高尚波信号に、同調
容量を規定するデジタル信号を重畳して端子17.18
に印加する。同調回路としては、端子17.18を通常
の可変容量ダイオードとみなして用いればよい。One end of the capacitive elements connected in parallel is used as a common cathode terminal 17, and the other end is used as an anode terminal 18.
The external terminals 11 and 17 are connected to the input terminal 1 which receives the code signal. Here, each capacitive element has a structure in which its capacitance value does not depend on voltage. In this embodiment, a capacitive element having a cross-sectional structure shown in FIG. 3 is used. An aluminum layer 33 with a thickness of 15 μm is provided on the S i Ox film 32 on the semiconductor substrate 31 by a vapor difference method, and then a KcVL) method is applied! Thickness i5300OA (D S l
(H 11434 is coated. Furthermore, aluminum *35t- is formed with a thickness of L5 μm by vapor deposition method, and the first
The second aluminum layer is used as a terminal 37, and the second aluminum layer is used as a terminal 38, which are regarded as a cathode and an anode, respectively, to form the terminal 17. Connected to switch 14. This structure is metal-3lO! - It is a capacitive element with a metal structure, and its capacitance value does not have voltage dependence. When using the semiconductor integrated circuit having the 1-rotation cap diode function according to the present invention as a tuning varactor diode, a digital signal that defines the tuning capacitance is superimposed on the high frequency signal that requires tuning. terminal 17.18
to be applied. As a tuning circuit, the terminals 17 and 18 may be used as ordinary variable capacitance diodes.
目的の周波数に同調させる為の容量git−規定するデ
ジタル信号が印加されているときは、この同調回路とし
ては離調状態にある。容量11を規定するデジタル信号
が容量素子の両端に印加されても容量素子自体は第3図
に示す断面構造のメタル−8tow−メタル構造である
為、容量値に電圧依存性はないので高周阪信号が変調さ
れることはない。When a digital signal defining the capacitance git for tuning to a target frequency is applied, this tuning circuit is in an out-of-tune state. Even if a digital signal defining the capacitance 11 is applied to both ends of the capacitor, the capacitor itself has a metal-8tow-metal structure with the cross-sectional structure shown in Figure 3, so the capacitance value has no voltage dependence, so high frequency The traffic signal is never modulated.
〔発明の効果〕
以上説明し次様に本発明に工れば容量値を規定するデジ
タル信号により高周波信号が変調さnることがなく、変
調後のノイズの発生とはならない。[Effects of the Invention] As explained above, if the present invention is implemented as follows, the high frequency signal will not be modulated by the digital signal that defines the capacitance value, and no noise will be generated after modulation.
第1図は本発明の一笑施例を示す構55を図で、11に
信号入力端子と可変容量素子としてのアノードを兼ね、
12はデコーダ、13はコントローラ。
14はスイッチ、15はメタル−3i01−メタルより
なる容量値が電圧依存性をもたない容量素子。
17はカソード、18はアノードであるが端子11に接
続されている。8g2図は従来の技術を説明する構成図
である。第3図は本発明に用い比容量素子の構造断面図
で、31は半導体基板、32及び34H8iO,,33
及び35はアルミニウムである。
37にカソード、38はアノード端子である。
6′
%、f1図FIG. 1 shows a structure 55 showing a simple embodiment of the present invention, in which 11 serves as a signal input terminal and an anode as a variable capacitance element;
12 is a decoder, and 13 is a controller. 14 is a switch, and 15 is a capacitive element made of metal-3i01-metal and whose capacitance value has no voltage dependence. A cathode 17 and an anode 18 are connected to the terminal 11. FIG. 8g2 is a configuration diagram illustrating a conventional technique. FIG. 3 is a cross-sectional view of the structure of the specific capacitance element used in the present invention, in which 31 is a semiconductor substrate, 32 and 34H8iO, 33
and 35 is aluminum. 37 is a cathode terminal, and 38 is an anode terminal. 6'%, f1 figure
Claims (1)
読するデコーダと、該情報をもとに複数の容量素子の接
続を制御するコントローラ及びスイッチ機能部を具備し
た可変容量ダイオードの、該可変容量を示す2つの端子
のいずれか一方の端子と容量値を規定する為のコード信
号を受ける端子とを共通にし、外部端子としては完全に
2端子とした半導体集積回路において、前記複数の容量
素子の容量値が電圧依存性をもたない素子であることを
特徴とする半導体集積回路。The variable capacitance diode is equipped with a decoder that receives a code signal for defining a capacitance value and decodes the code, and a controller and a switch function unit that controls the connection of a plurality of capacitive elements based on the information. In a semiconductor integrated circuit in which one terminal of two terminals indicating capacitance and a terminal receiving a code signal for specifying the capacitance value are used in common, and the external terminals are completely two terminals, the plurality of capacitive elements A semiconductor integrated circuit characterized in that the capacitance value of the semiconductor integrated circuit is an element having no voltage dependence.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30963786A JPS63164352A (en) | 1986-12-26 | 1986-12-26 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30963786A JPS63164352A (en) | 1986-12-26 | 1986-12-26 | Semiconductor integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63164352A true JPS63164352A (en) | 1988-07-07 |
JPH0556865B2 JPH0556865B2 (en) | 1993-08-20 |
Family
ID=17995434
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30963786A Granted JPS63164352A (en) | 1986-12-26 | 1986-12-26 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63164352A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011515832A (en) * | 2008-02-28 | 2011-05-19 | ペレグリン セミコンダクター コーポレーション | Method and apparatus for use in digitally tuning a capacitor in an integrated circuit element |
US9948281B2 (en) | 2016-09-02 | 2018-04-17 | Peregrine Semiconductor Corporation | Positive logic digitally tunable capacitor |
US10236872B1 (en) | 2018-03-28 | 2019-03-19 | Psemi Corporation | AC coupling modules for bias ladders |
US10505530B2 (en) | 2018-03-28 | 2019-12-10 | Psemi Corporation | Positive logic switch with selectable DC blocking circuit |
US10886911B2 (en) | 2018-03-28 | 2021-01-05 | Psemi Corporation | Stacked FET switch bias ladders |
US11476849B2 (en) | 2020-01-06 | 2022-10-18 | Psemi Corporation | High power positive logic switch |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60206161A (en) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | Semiconductor integrated circuit |
-
1986
- 1986-12-26 JP JP30963786A patent/JPS63164352A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60206161A (en) * | 1984-03-30 | 1985-10-17 | Toshiba Corp | Semiconductor integrated circuit |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011515832A (en) * | 2008-02-28 | 2011-05-19 | ペレグリン セミコンダクター コーポレーション | Method and apparatus for use in digitally tuning a capacitor in an integrated circuit element |
US8638159B2 (en) | 2008-02-28 | 2014-01-28 | Peregrine Semiconductor Corporation | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals |
US9496849B2 (en) | 2008-02-28 | 2016-11-15 | Peregrine Semiconductor Corporation | Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals |
US11258440B2 (en) | 2008-02-28 | 2022-02-22 | Psemi Corporation | Method and apparatus for use in digitally tuning a capacitor in an integrated circuit device |
US9948281B2 (en) | 2016-09-02 | 2018-04-17 | Peregrine Semiconductor Corporation | Positive logic digitally tunable capacitor |
US10236872B1 (en) | 2018-03-28 | 2019-03-19 | Psemi Corporation | AC coupling modules for bias ladders |
US10505530B2 (en) | 2018-03-28 | 2019-12-10 | Psemi Corporation | Positive logic switch with selectable DC blocking circuit |
US10862473B2 (en) | 2018-03-28 | 2020-12-08 | Psemi Corporation | Positive logic switch with selectable DC blocking circuit |
US10886911B2 (en) | 2018-03-28 | 2021-01-05 | Psemi Corporation | Stacked FET switch bias ladders |
US11018662B2 (en) | 2018-03-28 | 2021-05-25 | Psemi Corporation | AC coupling modules for bias ladders |
US11476849B2 (en) | 2020-01-06 | 2022-10-18 | Psemi Corporation | High power positive logic switch |
US12081211B2 (en) | 2020-01-06 | 2024-09-03 | Psemi Corporation | High power positive logic switch |
Also Published As
Publication number | Publication date |
---|---|
JPH0556865B2 (en) | 1993-08-20 |
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