JPS6231259A - Two-dimensional coding device for picture signal - Google Patents

Abstract

PURPOSE:To instantaneously generate a coding code at the time of determining the mode by supervising the mutual relation of the picture signal of a coding line and the picture signal of a referring line. CONSTITUTION:The data of a coding line 122 are successively written to the address designated by a memory address 135 in a line buffer memory A102. The data are a reading signal B shown by 124, selected by a selector 104 and come to be the data of a reference line 125. The condition of a symbol detecting circuit 201 and the condition of respective outputs of an A register 108, a B register 109, a C register 110 and a B' register 220 are simultaneously parallelly judged. Thus, the code of a P mode or a V mode and the code length are generated in one clock time instantaneously by giving the condition signal of the above-mentioned respective registers, etc., to a ROM table A204 as the input data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a two-dimensional encoding device for image signals used for facsimiles, image electronic files, and the like.

[Prior art]

Conventional facsimile Kasa image transmission devices and recent image file device Kasa using optical disks, magnetic disks, etc.
In this technology, image signals are encoded and handled to reduce the amount of data and to speed up and improve the efficiency of transmission or storage operations.

For example, in the field of facsimile, the Modified Huffman (MH) method is generally used for one-dimensional encoding, the Modified Read (MR) method is used for two-dimensional encoding, and the modified modified read (MMR) method is used for high-efficiency two-dimensional encoding. There is.

Regarding the mutual relationship between these MH, MR, and MMR methods, the MMR method includes methods that are very similar to the MH method, and the MMR method is a partially modified version of the MR method.

Furthermore, the images to be encoded and the rules of the encoding method are, in a nutshell, based on T4 and T6 recommended by the CCITT (Consultative Committee for International Telegraph and Telephone).

Furthermore, the above-mentioned encoding and method are highly recommended for the MMR method in the Recommended Communication Methods for Facsimile Group 4 Type Devices (Postal Service - Lookup) on page 52 and below of the Official Gazette (Extra Issue No. 29) dated March 22, 1985. The MH method is announced as a two-dimensional encoding method, and the MR method is a two-dimensional encoding method, both in accordance with Ministry of Posts and Telecommunications Notification No. 101 of 1982.
It is announced in No. 3.

Among the aforementioned encoding methods, two-dimensional encoding using the MR method or MMR method determines the correlation between the image signal of the line to be encoded and the image signal of the previous line, and generates an encoding code in a mode corresponding to this correlation. This is a configuration that generates. Therefore, after determining the correlation, the encoding operation of the corresponding mode is performed. For example, in order to represent a relatively long run length in horizontal mode, multiple encoding codes are required, and these are used for mode determination. If the image signal was formed and output later, the encoding operation could not keep up with the input of the image signal, and real-time encoding operation would have been difficult.

[Purpose] The present invention has been made in view of the above points.
Faster one-dimensional encoding of R, MMR, etc.

11, the purpose is to execute RF (RF) without delaying the input of the image signal to be encoded. means for counting the number of pixels between changing points of the image signal of the encoded line; and means for storing an encoded code representing the predetermined value when the counted value of the counting means reaches a predetermined value. , means for monitoring the correlation between the image signal of the encoded line and the image signal of the reference line, and means for determining whether or not the encoded code stored in the storage means is valid according to the correlation. An object of the present invention is to provide a two-dimensional encoding device for an image signal.

〔Example〕

Examples of the configuration of an encoding circuit to which the present invention is applied are shown in Figures 1 and 2.
The operation of the embodiment shown in the circuit block diagram in the figure will be explained using FIGS. 1, 2, 3 to 5, etc.

The signal indicated by 121 in FIG. 1 is an image signal to be encoded supplied from an external device such as an image scanner, an image file, or a combiator, and is "O" or "'1" (for example, "°0"'= It is given as serial data of a binary signal of white and (1°' = black pixel). Further, the signal indicated by 134 is a clock supplied from an external device in synchronization with the input of the image signal 121, and the signal indicated by 136 is a synchronous signal, which is one clock per pixel, and is one image signal. 121, several kinds of synchronization signals indicating horizontal sections, vertical sections, etc. are shown.

That is, in this embodiment, it is assumed that the image signal 121 to be encoded is provided as a scanning image signal, which is a serial image signal for each main scan, similar to a signal provided to a laser printer or the like.

Next, 101 is 2 forcibly changed so that the next pixel (=virtual pixel) after the last pixel of the real image on the coding line (one line in the main scanning direction of the image to be encoded) is always the change point. This is a circuit that generates points, and is called a "virtual change point generation circuit A." However, the above-mentioned "virtual change point generation circuit" has a structure in which no change is given to the actual image on the AU body co-coding line.

102 is a line buffer memory A, and 103 is a line buffer memory B, each of which is a RAM (random access memory) capable of independently writing or reading operations, and each of which has a coding capacity of 2 for one line. It has a capacity (number of main scanning pixels) that can store a value image.

Further, the line φ buffer memory AlO2 and the line buffer memory B103 are controlled so that when one is executing a write operation, the other one is executing a read operation. That is, these two line buffer memories constitute a set of double buffer memories.

111 is a memory address counter, which counts the clock 134 corresponding to the number of pixels of the coding φ line. The count value of the counter 111 is sent to the line as a memory address signal 135.
It is commonly given to both the buffer memory AIO2 and the line buffer memory B102. Furthermore, the memory address counter 111 returns to its initial value every codei>' grid line, and repeats the counting operation. Therefore, the binary image of each line written in the line buffer memory is read out for each pixel in correspondence with the pixel position of the image signal 121 of the newly input line.

104 is a selector, which is a line reference buffer memory A.
Of lO2 or line number buffer memory B103,
This circuit operates selectively in response to a select signal 901 in order to obtain read data from whichever one is executing the read operation.

The data selectively obtained by this selector 104 is given to the next stage as a reference line 125, that is, as reference data (image) of the coding line.

Reference numeral 105 is a circuit that forcibly creates a changing point so that the final pixel of the real image on the reference line and the next pixel (virtual pixel) become changing points, and is referred to as a "virtual changing point generation circuit B."

However, the virtual change point generating circuit B105 has a structure that does not give any change to the real image on the reference line.

Reference numeral 106 denotes a circuit that detects a pixel serving as a changing point on the real image and virtual pixel on the reference line, and is referred to as a "changing point detection circuit A."

Further, 107 is a circuit for detecting changing points on the real image and virtual pixels on the coding line, ``changing point detection circuit B''.
It is called.

108 is A register, 109 is B register, 110 is C
Each register is a 4-bit shift register. Also, the signals denoted by 126 are the signals representing the real image and virtual pixels on the reference line, and the signals denoted by 127 are the signals representing the real image and virtual pixels on the reference line. These are change point signals on real images and virtual pixels. A signal indicated by 128 is a change point signal on the real image and virtual pixel on the coding fist line.

A timing circuit 112 receives a clock 134 and a synchronization signal 136, and based on these, forms various timing signals 137 for timing the operation of each circuit block.

The operation of the circuit block of FIG. 1 described above will be explained using an example in which an actual image (image to be encoded) as shown in FIG. 4 is given and is encoded by the MMR method.

First, in order to simplify the explanation, the image shown in FIG. ) to create an extremely simple image that makes up one page.

In order to actually encode the first line 402 shown in FIG. 4, the virtual line 401 shown in FIG. Line.

When encoding the second line 403 in FIG. 4, the first line 402 in FIG. 4 is used as a reference line and the second line 403 is used as a coding line, as shown in FIG.

Below, it is assumed that one page consists of main scanning of 3 or more lines,
Even in the case where the third line, fourth line, -11, etc. are unified, if the relationship between the reference line and the coding line is sequentially lowered as described above, the encoding can be performed regardless of the number of sub-scanning lines. I can continue.

FIG. 3 is a timing chart when the image illustrated in FIG. 4 is applied to the circuit block illustrated in FIG. 1.

In FIG. 3, a vertical synchronizing signal 136-1 indicates an image section in the sub-scanning direction, that is, an input period of one page of images. 136-2 is a Mizuho synchronization signal, which is an image section in the main scanning direction;
That is, it shows the blank period of the l-line image. 134 is an image clock, 121 is a signal waveform representation of the image to be encoded illustrated in FIG. 4, and black pixel = "l" = "H"
"°, white pixel = "O" = It L +1. That is, among the images shown in the third figure, the image in the interval TI is the real image of the first line 402 shown in the fourth figure to be encoded. Yes, the image in section T2 is to be encoded in the second
This is an actual image of line 403.

Furthermore, in an image printed on an actual paper surface, the virtual line 401 shown in the fourth figure corresponds to a so-called margin at the upper part of the paper surface, or outside the paper surface, and in the MMR method, It is defined to be assumed to be a margin line (all pixels of the l line are white pixels). Therefore, the virtual line 401 shown in the fourth figure does not appear on the image signal 121 shown in the third figure.

FIG. 5 is a timing chart showing the encoding operation of the first line 4.02, and shows the relationship between the virtual line 401 serving as the reference line and the first line 402 serving as the coding.

First, when the image of the first line 402 shown in FIG. 5 is given to the virtual change point generation circuit AIO1, a virtual change point (virtual pixel) 302 is added as shown at 122 (kneading line) in FIG. The resulting image will be That is, in the interval T1, the real image remains unchanged, but as shown in the figure, the last pixel 301 of the first line and the next pixel 302 have contradictory colors (white → black), and the virtual change point (: virtual pixels) 30
Several virtual pixels following 2 are held as pixels of the same color as the virtual change point (virtual pixel) 302 so that they do not become change points for reasons described later.

Now, the coding-line signal 122 in FIG.
As shown in FIG.
The data is given to the buffer memory AlO2 and the line buffer memory B103 as write data.

On the other hand, the address e counter 111 counts the image clock 134 only in the interval T1 in FIG. 3, and outputs a count value as shown at 135 in FIG. AlO2
and is commonly given to the line stand buffer memory B103.

Furthermore, although not shown in the figure, assuming that the line buffer memory AlO2 is controlled to write mode and the line buffer memory E103 is controlled to read mode,
The data of the coding line 122 is sequentially written to the address indicated by the memory address 135 in the line buffer memory AlO2. Also, at this time, the line buffer memory B 103 is in the read mode as described above, so if all 0'' are written in the initial state, the line buffer memory B 103 will be read from the address specified by the memory address 135.
0'' are read out sequentially, and the readout signal B shown at 124 in FIG.
This is selected by the selector 104 and becomes the data of the reference line 125.

Reference numeral 125 in FIG. 3 shows the data signal waveform of the reference bone line, which is "O" in the section Tl. This means that the virtual line 401 is "completely white" as shown in FIG. This was obtained on the circuit as a reference line.

The kneading line 122 is also applied to the change point detection circuit B107 as described above. The detection circuit B107 detects a change point (:pixel) in the given data input, outputs the change point pixel as ``1p'', and outputs all pixels that are not a change point as 0. 128 in FIG. 1 is the output.

Virtual change point generation circuit B105 and change point detection circuit A10
6, as its name suggests, is the coding line 1 mentioned above.
Circuits 101 and 107 with the same name that operate on 22
The operation is read from the line buffer memory or performed on the farenne Φ line 125.

Eventually, the signal on the reference line 125 is converted by the virtual change point generating circuit B105 into a signal to which a virtual pixel of a color different from the last pixel is added next to the last pixel, as shown in 126 in FIG.

Signal 128 generated from change point detection circuit E107 is sequentially shifted into A register 108 by clock 134. Symbols A1 to A4 of the A register 108 each indicate a parallel 4-bit output of the register, which is always output. The output signal waveforms of the A register 108 are shown at 129-1 to 129-4 in FIG.

Therefore, the pixel of interest on the coding line is A register 1.
If it is shifted to output A4 of 08, output 1 indicates whether there is a change point in the data for 3 pixels following that pixel of interest.
This can be determined based on 29.

Similarly, 130-1 to 130-4 in Figure 3 and 1 in Figure 3
31-1 to 131-4 show the output signal waveforms of the B register 109 and the C register 11O. That is, B register 10
The change point signal and color signal of the pixel of the reference line corresponding to each pixel position stored in the A register 108 are stored in the 9 and C registers 110. Therefore, if the output A4 of the A register 108 is the pixel of interest on the coding line, the B register 109 and the C register 1
10, it is possible to determine whether there is a change point within the three pixels surrounding the pixel position of interest on the reference line and its color.

To encode the second line, the second line 403 in FIG.
When input as the image signal 121, the line buffer memory At02 is in the write mode, and the line buffer memory B103 is in the read mode.

That is, the first line 402, which was written in the line/rough memory B103 during the coding operation of the first line 402, becomes the reference line, and the newly input second line 403 becomes the coding line. And the first
An operation similar to that in the first line is performed.

Each signal waveform on the second line 403 is shown in section T2 in FIG.・The data of the first line 402 is read out.

The above is the specific operation of the circuit block shown in the first diagram.

Next, the circuit block shown in the second diagram will be explained.

201 is a symbol detection circuit, and as shown in the figure, a signal 129 is sent from the A, E, and C registers and nuts of the circuit block shown in the first figure.
, 130, 131, and detects necessary symbols aO+alla2, bl, b2, etc. in the MMR encoding method. The definitions of these symbols are as follows.

aQ=pixel on the coding line that is the starting point for encoding.

al=first change point (pixel) on the coding line to the right of aQ.

a2=first change point (pixel) on the coding line to the right of al.

b1 = A changing point (pixel) on the reference line to the right of a□, the opposite color to aQ, and the first changing point.

b2 = first change point (pixel) on the reference line to the right of bl.

However, the right here is the same as the relationship between the left and right of each pixel shown in FIG. 4, for example.

Next, 202 is a B° register, which uses the change point signal b1 shown as 222 in FIG. 2 as input data and clock 13.
This is a 3-bit shift e register that is sequentially shifted in by 4.

Therefore, the change point signal b detected by the symbol detection circuit 201
1 is held for three consecutive clock periods, and the position of the change point signal b1 relative to the pixel of interest can be determined.

203 is a run length counter, which usually corresponds to pixel a
It is a binary counter that counts the number of pixels (run length) from Q to pixel a1 or from pixel a1 to pixel a2, and has a 12-bit output, and the maximum is 2 in lO base.
This counter can count up to 559.

The signal indicated by 228 in FIG. 2 is the run length φ counter 2.
These are the lower 6 bits of the count value output of 03. or,
The signal shown at 227 in FIG.
These are the upper 6 bits of the count value output of 03.

204 is a ROM table A, which mainly contains codes for pass mode (P mode) and vertical mode (V mode).
A ROM (read only memory) that stores the codes and the number of bits (code length) of each code, and can output the codes and code lengths in parallel according to a given input.
It is.

Further, 205 is a ROM table B, which is a ROM that mainly stores the make-up code and code length for the horizontal mode (H mode), and the need and code to output the signal 227 as an address. The length is selectively output.

Reference numeral 206 denotes a ROM table C, which is a ROM in which the termination code and code length of the H mode are mainly marked, and the code and code length to be output are selectively output using the signal 228 as an address.

207 and 208 are latch circuits that temporarily store the make-up code and code length output from each of the ROMs. Further, 209 is a latch circuit that temporarily stores the terminating code and code length output from the ROM.

210 is a buffer memory for sequentially receiving the code and code length in the latch circuit C209 and temporarily storing it.

Here, the encoding rules of the MMR method will be explained a little more. In this encoding method, the symbol a defined as described above
Q, al, a2 are on the coding line, and
Similarly, symbols b1 and b2 are on the reference line. And each of these symbols ao, al, A2 (7
) group and bt.

Based on the relative position (distance) of the group b2, it is specified that the encoding mode is uniquely selected from the following three modes and encoding is performed.

(1) Pass mode (P mode) When b2 is to the left of al (there is only one generation code) (
2) Vertical mode (V mode) When la1b11≦3 (A total of 7 types of generation codes differ depending on the distance) (3) Horizontal mode (H mode) When other than (1) and (2) above (run/ (according to the length code table) Format: H+M(a□al)+M(ala2) where,
H is the code indicating H mode, M (aoal) is the run length code of white or black l aoax l, M (a1
a2) is a black or white 1ata21 run length code.

However, if two or more of the above (1), (2), and (3) are satisfied at the same time, (1) P%-mode > (2) V mode > (3) H mode Priority is given in order of rank.

The code determination circuit 21 controls this priority output operation.
2, and the code determination circuit 212 selects the latch.

Next, the operation of encoding the first line image 402 in FIG. 4 will be described.

First, in this embodiment, at time 1 ( 320 in FIG. 3),
, is the encoding start time.

That is, time 1 (, is the time when the first pixel of the reference line and the coding line appears at the C4 output of the C register 110 or the A4 output of the A register 108 in FIG. 2, respectively).

That is, at time 1 (,), each output of the C register 110, B register 109, and A register 108 is the reference signal.
The first pixel of the line and coding line and the states of three pixels are output in parallel to that first pixel. Also, aQ
is the initial value ' as shown in 221 AO (ao) in Figure 3.
“It is set to 0pa (white pixel = virtual).

The run range counter 203 changes from the initial value 0 to time 1 (
, the image clock 134 starts counting.

The count value output of the counter 203 at each time is
It is shown at 322 in the figure.

At time t□, the signal 129-4 in FIG.
is not set, that is, A shift register 1 in FIG.
There is no change point in the A4 output of 08, and similarly there is no change point in the B4 output of the B shift register 109.Therefore, there is no cause for generating a code, so just increment the count value of the run length counter by 1. Then, the process advances to the next time t1, but the state at time t1 is the same as that at time to.

Next, when proceeding to time t2, the signal 129-4 in FIG.
" is set. This means that the A register 10 in FIG.
The A4 output of 8 becomes 1, indicating that a change point exists at that position on the coding line. Since this change point is the first change point to the right of the current starting point aQ (corresponding to a later time), the symbol detection circuit 201 in FIG. 2 determines that it is the symbol a1.

Note that the detection state of this symbol a1 is stored as Fal.

At this time t2, 130-1 to 130- in FIG.
4, there is no 1'°, which means that there is no change point b1 within 3 times from time t2. Further, when the symbol detection circuit 201 detects bl, it shifts the bl into the B' shift number register 202 so that it does not disappear for three time periods.

The symbol detection circuit 201 also has a circuit for storing that bl has already been detected.

Due to these, in this case, there is no change point pixel b1 within three pixels on the left and right of change point pixel a1, and
Until then, it can be determined that there is no bl (therefore, there is no b2 either). Therefore, although al was detected at time t2, P
It is determined that the conditions of mode (b2 must already be detected) and V mode (lalbtl<3 is the condition) are not satisfied, so the mode becomes H mode.

At this time, the value of the run length reference counter 203 is as shown in FIG.
As shown in 22, the number of pixels from aO to al is shown, and “2
It's Pa. Also, the color of the run length is the initially set “O”.
= Remains white. Therefore, the run length counter 203
The run length value and color etc. are output by the output 228 etc. of RO.
The code is given to the M table C206, and the corresponding code and code length are outputted to the ROM206. In this case, the code of "white run 2" is output. That is, M (aoal)
= White 2.

At this time, it is determined that it is the first code of H mode, and the code “001” indicating H mode is changed to the code “001” of white run 2.
111'' at the same time, that is, in one clock.

Further, the code length is also output as a binary number or the like at the same time.

Next, the run length counter 203 is set to an initial value of 1 (O
(Note that this is not the case.) and moves on to counting from pixel a1 to pixel a2. However, pixel a1, that is, time t2
Then, only preparations for setting the initial value are made, and the initial value is set in the counter and the count is started from the next time t3. Furthermore, from this time t3, the color of AO is also inverted.

(Time t2=“0°゛→Time t3=゛°1°”) From then on, when time 1n advances, eventually at time t4, A register 1
08 A4 output shows "l" and a changing point appears. Since the symbol detecting circuit 201 remembers that the changing point a1 has already passed and is the detection method (Fa1=1), the symbol detecting circuit 201 determines that the changing point is a2. Note that this detection state of a2 is stored as Fa2. Now, at time t4, the value of the deep fist counter 203 is 2, and AO="'l"=black. Furthermore, since it has already been determined that the H mode is present at time t2, when a2 is detected, the reference line states 131-1 to 131-4 in FIG. 3 and 130 in FIG. References such as -1 to 130-4 are unnecessary and there is no single case, but bt, b
2nd grade, '+ (even if it exists, it is controlled to be ignored.

As a result of the above, M (a 1 . a 2) = black = "21 - code and code length are output in the same way as M (ao, ax). In this case, M (ao, al
), the code "001" indicating the H mode is controlled not to be added.

Next, after time t4, ie, at time t5, the run-length counter 203 is set to the initial value 1. or,
Ao (=ao) is inverted.

Then, the change point a2 at time t4 is the starting point aO of the next mode.
considered to be.

Through the above operations, the code generated by encoding the first line 402 becomes as shown at 501 in FIG.

Also, at time t30 in FIG. 3, the run length counter value is 9, and at this time, the symbol ft (=at) force is detected, but it is understood that there is a change point b1 two pixels later on the reference line. At time t30, the output 130-2 of the B register 109 and the output 131-2 of the C register 110 in FIG.
It is judged from etc. Therefore, since the condition 1alb11<3 is satisfied and it is not P mode (b2 is required), it is determined to be V mode by definition and vL (2) code (al is b
2 pixels to the left of l) is output.

At this time, the 4 players were in a state where the run length dispute 9 code of H mode could occur, but according to the definition of priority between each mode mentioned earlier, ■ mode became the valid code, and H Mode code is invalid. Run length counter 20 depending on the car that generated the V mode code.
The count value up to the corresponding time t 30 of 3 is cleared,
It is controlled so that it is newly preset to 1. or,
■After the mode code is generated, the color of the starting point aQ symbol is inverted. (However, the ■ mode code is generated at the same time as the detection of the change point of the a1 symbol (time t3O).) Also, although it has not been explained so far, when the symbol b1 is detected before the symbol a1, The detection signal of symbol b1 is shifted into the register as an input signal to the B register 202, and from then on, for 30 time periods, the output of the B register 202,
It shifts in the order of B5 → B6 → B7, and disappears after that. Further, when the symbol b1 has already passed the B4 output of the B register 109 but no code is generated yet, this fact is stored as shown by the output Fbl of the storage detection circuit 201.

Next, specific circuits of each functional block of the circuit block shown in the first diagram will be explained.

The virtual change point generation circuit Al0I and the virtual change point generation circuit B105 in FIG. 1 are circuits of the same type, and both are realized by the virtual change point generation circuit shown in FIG. In the figure, 702
is a flip-flop, 703 is an AND gate, 704 is an OR gate, and 705 is an inversion circuit (inverter).

The operation of the circuit shown in FIG. 7 is shown in the timing chart of FIG. That is, the numbers of each part in FIGS. 7 and 8 correspond to the numbers in FIGS. 1 and 3. However, Figures 7 and 8
The signal indicated by 701 in the figure is, for example, the position (timing) of the last pixel in one line obtained by decoding the count value of the memory address counter 111 shown in the first figure.
This is a signal indicating. That is, at the time when the signal 701 is generated, the flip-flop 702 is set to the same color as the last pixel of the coding line in synchronization with the clock 134, and after that time, that is, after the horizontal synchronization signal 136-2 is deenergized, the flip-flop 702 is The Q output of 122 is set as the 122 signal, and before that time, that is, while the horizontal synchronization signal 136-2 is being output, the image 121
is configured to output the signal as a 122 signal.

The selector 104 in FIG. 1 is realized by the circuit shown in FIG. In the figure, 902 is an AND gate, 903 is an OR gate, and 904 is an inverter. 123,1 in Figure 9
24 is the output 12 of the line buffer memories A and B in FIG.
3°124, but the signal 901 in FIG.
This is a select signal whose level is inverted for each line, and is generated by the horizontal synchronizing signal 136-2 in FIG. The output to signal 125 is switched by the select signal 901.

Change point detection circuit A106 and change point detection circuit B in Fig. 1
Reference numeral 107 designates a circuit of the same type, and FIG. 10 shows a typical configuration of the change point detection circuit B107. In the figure, 1002 is a flip-flop, 1003 is an exclusive OR gate, and 100
4 is an inverter.

That is, as shown in the timing chart of FIG.
), it is detected that the colors of adjacent pixels are different, and this is used as a change point signal.

Next, specific circuits of various functional blocks in the circuit block of FIG. 2 will be explained.

FIG. 11 is a circuit for detecting the symbol a1 or a2 on the above-mentioned coding contest input and the Fa1 signal indicating that the above-mentioned al is a detection flow, and the symbol detection circuit 2 shown in the second diagram.
It is within 01. In the figure, 1102 is a flip-flop, 1
104 is an AND gate, and 1105 is an in/hater.

The numbers of each part in FIG. 11 correspond to the numbers in FIG. 1, etc. The signal shown at 1101 in FIG. 11 returns the flip-flop 1102 to its initial state (i.e., Q output =
This is a control signal that prohibits the Q output from being set to "0'°) or Q output = "l'°, and is normally at the level of "1'".

The same applies to the RESET signal 1103. Here, when the change point A4 (129-4 signal) arrives first, A4
= “1”. In this case, the flip-flop 1102
Q output = “1” and control signal 1101 = “
1°', al="1'° is output and the symbol a1 is detected. This a1 detection signal sets the flip-flop 1102, and the Q output becomes '1', and a
Remember that l has already been detected (i.e. Q output = F
a 1 = “1”), and in this state, next A4 =
``When the signal becomes 1, a2=1'', and the symbol a2 is detected.

Next, a circuit for detecting symbols bl etc. is shown in FIG. In the figure, 1201 is an exclusive OR gate, 1202.12
03 is a flip-flop, l204 is an AND gate,
1205 is an inverter. The number of each part is the first
This is the same as in Figure 1. However, bl can be a
Exclusive or gate 1201 due to the condition that the color is opposite to Q.
This circuit uses a signal obtained by taking the exclusive OR of the change in the reference line and the aO times signal. still,
The circuit shown in FIG. 12 is included in the symbol detection circuit 201 of FIG.

The specific configuration of the run length counter 203 in FIG. 2 is shown in FIG. (decimal) to 25
60-1 (2559 in decimal), and the counter 203 has a preset function, a clear function, etc.
C, type name 74F163, etc.

Furthermore, the count value output of the counter 203 is decimal number 2.
559 and generates the MKI signal.
301 and the value obtained by decoding the lower 6 bits of the output is 1
A circuit 1302 is provided which detects that the decimal number is "63'°" and generates an MK2 signal.

Furthermore, “o” is set as a value using the preset function.
The structure is such that it can be selectively preset to (io base) or "1" (decimal base).

The operation of the run-length counter 203 will be explained. First, preset (or clear) each coding line to the initial value ゛0'° at a position outside the left edge of the image.
In the zero-order image area, the count is sequentially advanced pixel by pixel, but in the following values or three states, the counter 203
is returned to "l°" by the preset function.

That is, (1) when the change point a1 or a2 is detected, (2) when the count value reaches 2559, (3) when a P-mode code or V-mode code is generated, provided that the encoding method According to the rule, if the change point a1 is set to A2 on a virtual pixel outside the rightmost end of the coding line, the counter value is returned to "O" when al is detected.

Next, the configuration of the ROM table A204 in FIG. 2 will be described. The ROM table A204 is used to generate a total of eight types of codes, P mode and V mode, and the code lengths. As is clear from the configuration principle of this embodiment and the above explanation, the configuration described here is based on the relative relationship between the changing point positions of the coding line and the reference line, and especially when the changing point b2 on the reference line is in the B register 109. or when the change point a1 on the coding line appears as the A4 output of the A register 108, the state of the symbol detection circuit 201 and the A register 108, B register 109, C The configuration is such that the status of each output of the register 110 and the B register 220 can be determined simultaneously and in parallel. Therefore, the combination of the states of the above-mentioned request forces is naturally finite, and at the time when the judgment is to be made, it can be treated as a stationary state. Therefore, since the P mode or V mode code and code length to be output for each combination can be determined, it can be configured as the ROM table.

The specific contents of the ROM table are too redundant here, so as an example, FIG. Inside, 1409 is Ia/<
1410 is a timing circuit, 1411 is a Nant gate, and 1412 is a NOR gate. That is, the signal indicated by 1401 in FIG. 14 is a signal indicating that the change point b2 has been detected on the reference line in the symbol detection circuit 201 of FIG.

That is, this means that the B4 output of the B register 109 in FIG. 1 has a changing point as b2. Similarly, the a1 signal indicated by 1402 in FIG. 14 is the a1 change point as the A4 output of the A register 108 in FIG. Furthermore, the FAL signal shown at 1403 in Fig. 14 has reached the second level by the current time.
This is a signal indicating that the change point al in the graphic symbol detection circuit 201 is the detection method.

The logic circuit shown in FIG. 14 means that at the time when b2 is detected, the P mode is determined because the al or Fal signal is not "true". That is, it means that there is no a1 change point after the starting point aO until the time when b2 is detected. That is, on the image, there is no a1 change point between the starting point aQ and directly below the b2 change point.

Therefore, by definition, it is in P mode. 140 in Figure 14
4 is a P mode detection signal, l 405 is a specific code of P mode, and 1406 is a binary number representing the code length of the P mode code. Further, 1407 is a signal indicating that a P mode code has been generated. The above is the determination method for P mode, but the same method can also be applied to ■mode. The ROM table A204 is configured by this method.

After all, the code and code length of the P mode or V mode are determined by applying the status signals of each register etc. as input data to the ROM table A204 in FIG. 2 based on the above method at the time when the b2 or a1 symbol is detected. Depending on the event, the signal is generated immediately in one clock time.

ROM table B2O5 and ROM table C in Figure 2
Since 206 has a similar structure, the ROM table C 206 will be explained with reference to FIGS. 15 and 16 as a representative.

First, 206 is a ROM with at least 11 bits of address input and 21 bits of parallel output;
The human power corresponds to the 228 signal in FIG. That is, they are the lower 6 bits of the run length counter 203 in FIG. Further, 1502 manual input in FIG. 15 is a signal specifying the color of the run length, and in this example, white; O1 black=1.

Also, 1503 human power is a code indicating H mode (=OO1)
This is a signal that specifies whether to add or not. In this example, required = 1
, Unnecessary - 〇. That is, if 1503 manpower is 1, H
The code (001) added to the first run length code of the mode code is output in one clock.

A chip enable signal 1504 controls whether the output of the ROM 206 is enabled or disabled. 150
7 manpower is EOL<1507 manpower is EOL+ 1.150
8 are address inputs that control the reading of each of EOL+O, and by inputting pulses to these inputs, the delimiter code of the corresponding line is read. Also, 1
505 is the code output of the address specified by the input and is 15
Similarly, 06 is the code length of the code.

FIG. 16 is a diagram showing the correspondence between the addresses AO to A10 in FIG. 15 and the stored contents (data).

The code determination circuit 212 of FIG. 2 is specifically explained with reference to FIG. 17. In FIG. 17, 1706 is an AND gate;
is an inverter.

As can be seen from the principle of the code generation method in this example,
ROM table 204 and 205 or 206 shown in the second diagram
etc., P mode.

In the stage before each mode and H mode code is finally determined as the code to be generated, two or more codes may be output from the ROM table at the same time. However, the priority of two or more codes is defined as described above.

FIG. 17 shows a circuit for determining the code to be uniquely generated according to the definition.

That is, if the codes of P mode, ■mode, and H mode can occur simultaneously, the code of the mode that has acquired priority will finally be generated according to the order of P mode>■mode>H mode as described above. The code in other modes is invalid and cannot be used as the generation code.

Note that the signal 1708 is a mode signal for selecting whether to use this encoding circuit for the MH method, that is, -dimensional encoding, or for two-dimensional encoding of MMR or MR, and executes -dimensional encoding. When performing two-dimensional encoding, the level is L. On the other hand, when two-dimensional encoding is performed, the level is H.

Therefore, when performing -dimensional encoding, generation of P mode codes and ■ mode codes is prevented, and only H mode codes, that is, codes representing run length are always valid.

Next, the roles m such as latch A 207 and latch B 208 in FIG. 2 will be described. Latch A207 and latch B2
O3 is a circuit for temporarily storing the H mode make-up code and the code length that are generated during =-ding until it is determined whether the H mode is valid or invalid. If it is determined that the H mode is valid, the contents of the latch are transferred to the next stage circuit.

The functions of the latches A207 and B2O3 in FIG. 2 will be explained by taking as an example a case where the run length where the make-up need occurs is long (1, for example, run length=2972). At this time, according to the encoding regulations, the code is divided into a total of three run-length codes, two make-up codes and one terminating code, and output as follows.

That is, (]1) Make-up code 1 = Run-length 2560 code (common to white and black) (:2) Make-up code 2 = Run-length 384 code (white or black) Terminating code = Run-length 28 code (white) In this way, when one run length is represented by multiple codes such as 2560+384+28=2972, the count value of the run length counter 203 in FIG. 2 is 63+64XN (N=0.1.2・・・・・・
If the A4 output of the A register is not at the a1 change point at that point, it is predicted that a make-up value will occur next, and the value of the upper 6 bits of the counter 203 (:N is a positive integer). R
The OM table B2O5 is also output and temporarily stored (:latched) in the latch B2O3. Next, the previous value count value is 6
Every time 4 advances (], that is, in the formula of s3+64xN mentioned above, N
The contents of the latch B2O3 are updated each time the value advances by 1).

Then, the value of the run length counter 203 is 2559.
If the change point a1 is not detected at the time when (: 63 + 64 The code and code length of run length 2560 are read from table B2O5 and temporarily stored in latch A207. At the same time, latch B
Temporarily invalidate the mnemonic contents of 2O3. Further, the count value of the run length counter 203 is returned to the initial value l.

Then, as the count progresses, the above-mentioned 63+64X
Storage of the makeup code, etc. to the latch B2O3 is restarted in the same way for every N expressions.

When the change point a1 is detected, the competitive relationship with other P mode or V mode is determined, and when the H mode is determined, the run length counter 2 at the time of the change point a1 is determined.
The termination code and code length of the run length indicated by the value of the lower six bits of 03 (0 to maximum 63) are temporarily stored in latch C209. Furthermore, as already described above, the contents of latch A207 and latch B2O3 also become valid.

However, if V mode etc. occurs at the time of change point a1, H mode itself will not occur, and naturally latch A20
7 and the contents of latch B2O3 are invalidated, and the contents of latch C
209 instead of the above-mentioned terminating code.
Mode code is latched as valid code.

Makeup code 1 and makeup code 2 above
FIG. 18 shows a circuit for controlling the generation and storage of the data, etc., and this circuit is included in the timing circuit 112. Timing chart of this circuit (: run length is as described above)
2972) in Figure 19, 18
01.1802 is a flip-flop, 1803 is an AND gate, and 1804 is an inverter.

MKI and MK2 are signals output from the 2559 detection circuit 1301 and the 63 detection circuit 1302, respectively, of the run length counter 203 shown in FIG. The flip-flop '1802 is set by the input of the MK2 signal and generates the MK2 signal, and the flip-flop '1802
01 is set by the input of the MKI signal to generate the MKI presence signal. Note that the flip-flop 1802 is reset by inputting the MKI signal.

With the above configuration, the run length counter 203
When the count value becomes 64 or more, the MK2 signal becomes high level, and when the count value becomes 2560 or more, the MK2 signal becomes high level.
Only the KI presence signal or both the MK2 presence signal and the MK2 presence signal become high level. Depending on the level and level of the MKI presence signal and MK2 signal, it is possible to determine whether the code representing the run length is only a termination code or a combination of a termination code and a makeup code, and whether the number of makeup codes is 1 or not. It can be determined whether there is one or two. Therefore,
When generating a code in H mode, the levels of the MKI present signal and MK2 present signal are controlled by the backing circuit 211.
is determined, a valid one is selected from among the three latches A, B, and C, and the latch data is fetched.

In this way, when the make-up code is generated, by predicting the generation of the code at least one time in advance and sending the code to the temporary memory circuit (latches A and B), the change point a1 is reached. This has the effect of preventing an increase in the number of output codes and the number of bits that must be processed at the same time.
Extremely effective.

That is, the latch A207 and the latch B2O3 range counter 203 count before deciding on the H mode, and temporarily store the necessary make-up code and code length, so that when the H mode is decided, the terminal Since only the counting code and code length need be processed, all the H mode codes to be output at the time of al detection are available, and the subsequent encoding operation can be executed without delay.

207, 208, 209 latches A, B.

The order in which the contents of C are sent to the next stage circuit is latch A207>
It is controlled so as not to disturb the order of latch B2O3>latch C209 (: 210 buffers) (: omitted or ignored when the contents are invalid).

The reason why the contents of latch C209 are temporarily stored in buffer memory 210 is because the next encoding operation starts from the time after the encoding mode is determined, and the next encoded data is stored in latch C209 from the ROM table for several clocks (minimum 1 clock). Therefore, after the mode is determined, the contents of the latch C209 are sent to the buffer memory 210 so that the next encoded data can be latched, and then output from the buffer memory 210 to the subsequent stage with proper timing.

Next, a special case in which the change point a1 and the change point a2 are set on the same pixel according to the encoding method will be described.

FIG. 20 illustrates the above case. That is,
In Figure 20, 2001 is the reference line, 2
002 is a coding line. Also, 2003 is the final pixel of the coding line, and 2004 is the virtual change point (
pixels).

Now, in Fig. 20, if we assume that the starting point aQ is at the position shown in the figure as a result of encoding from the left, the next code to be generated is as shown in Fig. 21: [H mode code + white 12 terminator code + black 0 terminate:-do]. here.

The code in FIG. 21 (1) can be treated as one code at the time of change point a1 by the above-mentioned means, and there is no problem.
However, the code in FIG. 21(2) is a need that should originally occur at the time of the change point a2, when the change point a2 comes at a different time from the change point a1. However, in this case, it is clearly not detected as the change point a2 by the symbol detection circuit 201 and the like.

Therefore, in this case, the following processing is performed by the circuit shown in FIG. 22 provided in the symbol detection circuit 201. FIG. 23 is a timing chart of the operation of this circuit. In FIG. 22, 2201 is a signal indicating that the image has entered the virtual area (
2202 is an a1 change point detection signal, and 2203 is a signal indicating up to the generation of the first termination code in H mode. The signals 2201 to 2 are monitored by the AND gate 2207.
The state shown in FIG. 20 is detected by taking the AND of the 203 signals, and the 2204-1 signal is created (that is, the time is
), first output the code in FIG. 20 (:1) using the method described above. Next, the run length counter is cleared to 0, etc., and the 2204-1 signal in Fig. 22 is converted to D.
The black 0 in FIG.
generates the termination code.

The backing circuit 211 in FIG. 2 receives as input the code and code length obtained by the method described above, and the length of each code (the number of bits of the code) generated by this division is not constant, however, the longest one is H Even if a mode code (=001) is added, the number of bits is 16 bits), and the circuit is sequentially grouped into 16-bit units, and in this embodiment, each 16-bit bit is transferred to the next external circuit in parallel. It is something.

The signal 238 in FIG. 2 is a code compiled into 16 bits by the backing circuit 211, and the signal 239 is a signal for reporting this fact to the next stage external circuit. Note that the backing circuit 211 is a code length addition circuit and a bit shifter.

This can be easily realized by combining well-known circuits such as multiplexers and latches.

RTC (', Re t u
rn To Control) signal. In the case of the MMR method, RTC code=EOL code×2 times. That is, the RTC signal is (000000000001)
X2=00000000ooot, 00000000
It is expressed as 0001. Furthermore, in the unembodied embodiment, the structure is such that up to 16-bit code can be output in one clock time, as described above. Therefore, in order to output the RTC signal, the end of one page is detected by monitoring the vertical synchronization signal 136-1 shown in FIG. (1st
By giving it as the address signal 1507 of the ROM table C206 (shown in Figure 5), the EOL code and code length are written in the corresponding address of the ROM table.
If output is performed, the RTC code can be obtained following the code for the above-mentioned image.

Next, the differences between the three encoding methods described above are listed in Table 1.

Therefore, the encoding method of the MH method is almost the same as the case where the H mode of the MMR method described above is repeated, but differs in the following points.

That is, (1) H mode code (001) is not required in the MH method (2) It is not necessary to pair white runs and black runs in the MH method (3) Inserting an EOL code for each line in the MH method (4) Differences in RTC and in the case of the MR method: (1) One-dimensional lines are the same as the MH method (2) Two-dimensional lines are the same as the MMR method (3) Line separation is EOL + 1 = 0000000000011 or EOL + 0 = 0000000000010 (4) RTC
Difference (:5) Due to the K parameter, one-dimensional lines and two-dimensional lines coexist.

After all, switching between the three encoding methods can be easily realized by controlling the operation of the circuit for the MMR method described above using a method selection signal for the MR method or the MH method.

First, Figure 24 shows an example of a circuit that controls the differences between lines, delimiters, and codes. In Figure 24, 2407 is a line counter;
408 is Nantes Gate, 2409 is And Gate, 24
10 is an inverter. That is, 2401 in FIG. 24 is a pulse signal at time t=1 shown in 320 in FIG. 3, which is repeated for each coding line. At time t-1, a code is generated due to image encoding No, this pulse signal at time t-1 changes the value of address counter 111:-
Obtained by Further, 2402 and 2403 are encoding method selection signals from outside the circuit of this embodiment, such as a CPU, which specifies the encoding method. Also, the 136-2 signal is 13 in Figure 3.
Therefore, the forward counter 2407 counts the signal 136-2 and monitors the progress of the variable meter in the MR method as a line counter.

Signals 2404 to 2406 obtained by the logic in FIG.
were used as address inputs for the ROM table C206 in Figure 2 (1507 to 1508 in Figure 15), each specifying a specific address, and the code and code length required for the specific address were stored. By outputting something, you can obtain the desired line/separation number need.

Furthermore, the one-dimensional line encoding method of the MH method is described in the 17th
The selection signal 1708 may be used to control the mode determination circuit of the MMR method shown in the figure so that the H mode can always be given priority.

Further, in the MH method, control is performed so that the H mode code (001) is always unnecessary, and this is also achieved by setting the address signal A7 of the ROM table C206 to 0.

Also, the difference in the number of EOLs in RTC is ROM table C.
This is achieved by varying the number of pulses applied to 206 depending on the mode.

In this embodiment, as shown in FIG. 3, etc., the operation is synchronized with the (image) clock 134, but it is not related to the interval (period) of the clock, so as shown in FIG.
A pause period between images or lines can be easily created by masking the clock 134 with an image gate signal.
l can be provided.

That is, in FIG. 25, 2501 is the image gate signal "O".
” This is a signal indicating that the operation is to be halted during this level.

Further, 2502 is the gate signal 2501 and the clock 134.
If this clock 2502 is sent to the actual internal circuit of this embodiment in place of the aforementioned clock 134, the state of this embodiment can be changed only by the clock signal. Therefore, the shaded area in FIG. 25 is clearly in the rest state.

With this pause control, for example, the output speed of the image signal from the source of the image signal to be encoded is not limited by the operation of the encoding circuit. Conversely, even if one page of image signals is output intermittently, for example in the case where the image source is an image file with a disk, the encoding circuit will not be able to synchronize with the intermittent output. Encoding operations can be performed intermittently. Therefore, the image signal from the output source can be sequentially encoded without requiring a large buffer memory for time adjustment between the image signal output source and the encoding circuit.

Next, a method of supplying images to be encoded to the circuit of this embodiment in a parallel format will be described with reference to FIGS. 26 and 27. That is, 2601 in FIG. 26 is a parallel-to-serial change shift register that can input 8-bit parallel data and output it to 2602 as 1-bit serial data.

As shown in FIG. 27, after loading the image signal to be encoded into the register 2602 as 8-bit parallel data,
The signal is serially shifted by a clock, and a serial image signal 2602 as shown in FIG. 27 is obtained. At the same time, the number of clocks during the serial shift is counted to generate a gate signal 2702 indicating the section of the actual data, and a clock 2702 corresponding to the actual data can also be obtained in the same way.

As described above, the signals as shown in FIG. 27 are in a format that can be encoded as described above in this embodiment by the pause method described in FIG. 25. The operation for parallel input of this image is Cp
This is extremely effective when an image is provided by u, etc.

In the above embodiments, MH, MR, and MMR encoding was explained, but it goes without saying that other encoding methods are also applicable. The present invention has been described based on a preferred embodiment. However, it goes without saying that the present invention is not limited to this configuration, and that various modifications and changes can be made within the scope of the claims.

Table 1 [Effects] As explained above, according to the present invention, in two-dimensional encoding that encodes in multiple modes, the generation of encoded codes becomes available immediately when the mode is determined, and it is possible to generate encoded codes at high speed and in real time. It is possible to achieve a good encoding operation.

[Brief explanation of drawings]

Figures 1 and 2 are block diagrams showing the configuration of an encoding device to which the present invention is applied, Figure 3 is a timing chart showing the encoding operation, and Figures 4, 5, and 6 are references. A diagram showing the relationship between lines and coding lines, FIG. 7 is a diagram showing a configuration example of a virtual change point generation circuit, FIG. 8 is a timing chart diagram showing the operation of the circuit shown in FIG. 7, and FIG. 9 is a configuration of a selector. FIG. 10 is a diagram showing a configuration example of a change point detection circuit, FIGS. 11 and 12 are diagrams showing a partial configuration example of a symbol detection circuit, and FIG. 13 is a configuration example of a run length counter. 14 is a diagram showing an example of the configuration of an equivalent circuit of ROM table A, and FIG. 15 is a diagram showing an example of the structure of ROM table C.
FIG. 16 is a diagram showing an example of the contents of ROM table C, FIG. 17 is a diagram showing an example of the configuration of the code determination circuit, and FIG. 18 is a configuration example of the make-up code generation and storage circuit. 19 is a timing chart showing the operation of the circuit shown in FIG. 18, FIG. 20 is a diagram showing the relationship between the beam farenne line and the coding line, and FIG.
Figure 22 is a diagram showing a configuration example of a delay circuit at a virtual change point, Figure 23 is a timing chart diagram showing the operation of the circuit shown in Figure 22, and Figure 24 is a diagram showing control of generation of line separation codes. Diagram 25 showing an example of the configuration of a circuit for
26 is a timing chart showing a pause control operation of the encoding operation, FIG. 26 is a diagram showing a configuration example of a circuit that serially outputs parallel input of an image signal, and FIG. 27 is a timing chart showing the output state of the circuit shown in FIG. 26. It is a chart diagram, and 10
1 and 105 are virtual change point generation circuits, 106 and 107
is a change point detection circuit, 108 to 110 are registers 7, 111
is an address counter, 201 is a symbol detection circuit, 203 is a run length counter, and 207 to 209 are latches. Applicant: Canon Co., Ltd. 7th figure; I8th figure, 52th figure, 5tO figure, 77th figure, 7215J, 75th figure, Kō7/OtsuH No. 4 Tsugu VEN body stop pause

Claims (1)

[Claims] means for serially capturing the image signal of the reference line in synchronization with the serial input of the image signal of the encoded line; means for counting the number of pixels between changing points of the image signal of the encoded line;
means for storing an encoded code representing the predetermined value when the count value of the counting means reaches a predetermined value; means for monitoring the correlation between the image signal of the encoded line and the image signal of the reference line; A two-dimensional encoding device for an image signal, comprising means for determining whether the encoding code stored in the storage means is valid according to a relationship.