JPS6235776A - Decoding device for image code - Google Patents

Abstract

PURPOSE:To perform fast decoding operation by starting the decoding operation after fetching the image signal of a reference line for by as much as picture elements necessary for the decoding of an image code. CONSTITUTION:A 16-bit code read out of a storage circuit 101 in parallel is passed through a multiplexer 102 and stored in a register C103, but the code data is so controlled as to move in the register C102 successively in one direction by the specified number of bits by a shift control circuit 108 by controlling the relation between the input and output of the multiplexer 102 by a shift control circuit 108. A code detection logic part 104 and a code table ROM 106 inputs the code at a specific position in the register C103 to decide the contents of the code. Consequently, the decoding operation is started after the image signal of the reference line is fetched by as much as the picture elements necessary for the decoding of the image code.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an image code decoding device, and in particular, to a two-dimensional image code decoding device such as modified read (MR) encoding and modified modified read (MMR) encoding. The present invention relates to a Nri image code decoding device that decodes encoded image codes.

[Prior art]

In image transmission devices such as facsimiles and image file devices using optical disks, magnetic disks, etc., image data is compressed and handled to reduce the amount of data and to speed up and improve the efficiency of transmission or storage operations.

Compression techniques for such image data include the two-dimensional encoding method (Ministry of Posts and Telecommunications Notification No. 1013 of 1980) or the high-efficiency two-dimensional encoding method (Ministry of Posts and Telecommunications Notification No. 197 of 1985).
MR shown by et al.

MMR and the like are generally known.

Two-dimensional encoding such as MR and MMR encoding expresses the correlation between the image of the previous line and the image signal of the line to be encoded using a code. Therefore, decoding a two-dimensionally encoded image code requires six complex processes, such as determining the relationship between the already decoded image signal of the previous line and the human image code. In the case of Kasa, which prints an image by decoding such a two-dimensional encoded coat, the decoding process is very fast! , IJ Renaku Il,
It is preferable that the process be executed in two steps.

〔the purpose〕

The present invention has been made in view of the above points, and an object of the present invention is to decode a two-dimensionally encoded image code at high speed without delaying the output device. One stage for capturing the image signal of the reference line used for decoding the code, means for sequentially determining the input image code, and the image signal of the reference line captured by the first stage for capturing the discrimination result of the discrimination means and the L record. and a means for forming an image signal based on the relationship between the image code and the image code, and starts the decoding operation after capturing the image signal of the reference line for the number of pixels necessary for decoding the image code by one stage of L notation capture. The purpose is to provide equipment.

〔Example〕

Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram of a decoding circuit according to an embodiment of the present invention. The main points of operation will be explained with reference to FIG. In this example, decoding of an MMR encoded image code will be explained as an example, but the present invention can also be applied to other two-dimensional encoding such as MR encoding.

101 is a storage circuit, which stores the code (
(hereinafter referred to as a code) is stored in the memory circuit 10.
As shown in Fig. 2 (A), the data recording format of No. 1 is, for example, a series of codes received serially from a communication line,
As shown in Figure (B), 6-bit medium parallel data is
71, and is not concerned with the delimitation of each code. This fertile circuit 101 can be constructed from a RAM (random access memory) or a latch circuit.

The memory circuit 101 responds to a request signal 201 from the outside.
It has a structure in which the parallel output data BO-815 can be updated in sequence.

In FIG. 1, 102 is a multiplexer, 103 is a register C, and the multiplexer 102 and register ClO3 work together to form one bit shifter. That is, the 16-bit codes read out in parallel from the fertilizer circuit 101 are sent to the register ClO3 via the multiplexer 102, but at this time, the input and output of the multiplexer 102 are changed by the shift control circuit lo8. By controlling the relationship, the need data is controlled to move by the number of bits specified by the shift control circuit 108 in the 1lf1 order dinutator ClO3 in the - direction.

104 is a code detection logic, 106 is a code table ROM, and the code detection logic 104 and the code table ROM 1o6 manually determine the contents of the code at a predetermined position in the register ClO3. This is a circuit that does this. 11U, the ROM 106 stores the run length and code length (=bit l &) i in consideration of the input code in the case of water-F (I () mode I).
By accessing this table, the corresponding data is output. And ROM10
The run length value output from 6 is input to a run length count circuit 107.

When the run length count circuit 107 has counted the number stored in the ROM 106, it outputs a count end pulse and sends it to the image reproduction circuit 110, etc.

On the other hand, among the outputs of the ROM 106, the code length is sent to the shift control circuit 108. Shift control circuit 10
8 operates the multiplexer 102 to move the code data in the register ClO3 by the number of bits of the code length just determined. In other words, the determined code is stored in register ClO.
3 and moves the next code to a predetermined position in register ClO3 so that 1106RO etc. can judge it. At this time, the shift control circuit 108
integrates the movement characteristics of the designated coat to the multiplexer 102, and a new code is sent to the multiplexer 11 from the 16-bit memory circuit 101, so that the calculated value corresponds to a shift of 16 bits. 102 to register ClO3. Further, the coat detection logic 104 performs a detection function when the code in the register ClO3 is a specific coat as described below, and notifies the PV verification circuit tost of the detection result. At the same time, the code length of the specific code detected by the code detection logic 104 is sent to the shift control circuit 108. The role of this 114F soft control circuit 108 is the same as in the case described above.

112 and 113 are line buffer memories A;

The buffer memory Al12 and the buffer memory B113 each have a capacity capable of storing image data for one line of an image, and are composed of RAM or the like. Address counter A111 and address counter B117 are connected to buffer memory Al12 and buffer memory B113.
This is a counter that specifies each of the 11 input or read addresses. The buffer memory A 112 and the buffer memory B 113 have a double buffer structure so that one is in the write mode 111f and the other is in the read mode. Also, buffer memory A112 and buffer memory B1
Reference numeral 13 is for storing an image of a reference line for decoding a code based on a two-dimensional encoding method.

118 is a control circuit that generates a control signal to control the operation of each circuit block shown in the first diagram, and each circuit block receives the clock generated from the control circuit 118 at a common timing to synchronize each part. It works fine.

Next, the functions of each part of the circuit block 14 shown in the first diagram will be specifically described. Multiplexer 102 and register ClO3
constitutes a bit shift as described in +ii7, and an example of its configuration is shown in 3rd U;4.

That is, as shown in FIG. 2(B), the code data which has been tα described above in the tα circuit 101 is first read from the first word = 16 hits + - (B0 to B15) to the third word.
It passes through the illustrated multiplexer B1021 and into the shift register ClO3. Subsequently, the output of the register ClO3 is connected to the register ClO3 via the multiflexer A1022.
to use human power. The first bit of the code is register C.
When the output of 1O3 CO is reached, -1L stops [-. This state is the state 7i' in which preparation for starting decoding is completed.

The subsequent movement of the coat data is controlled by the signals Σl to Σ4 from the shift control circuit 108 in FIG. C
R, STI to ST8 code detection lock 104 signal;
Perform according to 5o-S3. In addition, the multiplexer 102 in FIG. 3 and the register ClO3 have the function of performing a 1σ Sorial shift and a jump shift that shifts multiple bits of 1 to 9 bits to -I. It is. Further, the register ClO3 is a 31-hit parallel-in/parallel-out register in this embodiment. Further, the direction of shift is only one direction as shown by the arrow in FIG. Further, the code shown in the register ClO3 is an example of the state in which the code in the memory circuit 101 of FIG. 2(b) is at the decoding start preparation completion position in the register ClO3.

Next, the structure of the code φ table ROM106 shown in FIG. 1 is shown in FIG. 401 and 402 are ordinary ROMs (read-only memory) each having 13-bit address input (AO to A12), 1-bit chip enable input (σT), and 12-bit data output (01 to 012). ). ROMA401 is a table for the white coat, and ROMB4O2 is a table for the black code, and either one is selected by the signal to the chip/r enable input σT.

Since the configurations of ROMA401 and ROMB4O2 are similar, the storage contents of ROMA401 will be described. ROMA
The C3 output signal of the register ClO3 shown in the third diagram is input to MSB=A12 of the address 401. The outputs 03 to C15 of the register ClO3 are input in parallel to the subsequent addresses A11-AO in the order shown in the fourth figure. Also, ROMA401's clove force has a code black/
The white color signal (B/W) is manually input. Further, the C3 output is the MSB bit of each code other than the H mode code (o o i) constituting the H mode. The run length (RL5~RLO) and code length (CL4~RLO) of the code from the address specified by the code input to ROMA401
CLO) and a signal (M/T) for distinguishing whether the code is a make-up code or a terminating coat are output in parallel.

Furthermore, since the run-length code is determined based on the 03 to C15 outputs of the register ClO3, the subsequent run-length code can be determined without discharging the 3-bit H code indicating the water mode from the register, and high-speed decoding can be achieved. .

The input example in Figure 4 is the code for white run 18 (0100111
) is a human output of 11ν and has a run length of 18, but is output in binary 2's complement form (101110). The run length can originally be expressed in 12 bits, but in the case of a terminating code, only the lower 6 bits are output, and the first 6 bits are always all the bits, so they are not output. Also, 1. If the obtained code is a makeup code, only the upper 6 bits are output, and the lower 6 bits are always all O's, so they are not output. Also, in the input example shown in Figure 4, the code length of the white run 18 code is 7, so , an output example shows that when the binary number (00111) is output to CL4 to CLO, the M/T output outputs O, indicating that the input code is a terminating code (M/T). T
= 1 is the makeup code).

Also, since the code is short for address input, the ROM is set so that addresses without input are treated as Don't Care.
In A401, addresses are assigned to each code input and the memory contents are written. As mentioned above, the usage code is defined as "Don't Care" so as not to be confused.

Next, the basic circuit structure of the code detection logic 104 shown in FIG. 1 is shown in FIG.
Each code shown in the table is converted into a NAND circuit 510. OR circuit 511
, the detected signal of each code and the code length of the detected code (So-54
), run length (RLO to RL5), etc.

The JCD signal indicated by 501 is the first signal according to the logic shown in FIG.
Indicates that the code in Table and Table 2 has been detected. Since the data in the register ClO3 is given in parallel to the ROM shown in FIG. 4 and the logic shown in FIG. 5, decoded data may be output from both. For such cases, when a code is detected using the logic shown in Figure 5, JCD
The output of the ROM shown in FIG. 4 is disabled by the signal.

Figure 5 shows the P code (of the codes in Tables 1 and 2).
0001), VL (1) code (010), W4
Although the detection of the code (1011) is illustrated, other codes are similarly detected. In addition, for the code groups shown in Table 1 and Table ff12, when the length of each code is equal to or longer than the run length indicated by the code, the number of inputs required to form image data from the code is 1 bit. If the code is shifted in increments, the beginning of the next code cannot be set to the next image output special.

In Tables 1 and 2, each code in group l in Table 1 has the MSB bit of the code in register Cl shown in Figure 3.
The predetermined position to be detected is when it is in CO of O3. Further, each code in Group 2 of Table 2 has a predetermined position when the MSB bit of the code is in C3 of register ClO3. The codes shown in Tables 1 and 2 will be collectively referred to as "jump codes °'. It goes without saying that the jump codes may include codes other than these.

Next, a specific circuit of the run length count circuit 107 shown in FIG. 1 is shown in FIG.

In FIG. 6, 601 is a demultiplexer, and RL5 to R, which are the outputs of the code table ROM shown in FIG.
Convert the LO run length signal (2's complement) to the run length signal.
It is input as load (preset) data to the counter 602. At this time, the output ten-length (RL5 to RLO) from the ROM shown in Figure 4 is only 6 bits as described above, and depending on whether the input code is a make-up code or a terminating code, the lower or lower run-length signal is The upper 6 bits are 1 from multiplexer 601.
is supplemented. The input M/T signal to the multiplexer 601 outputs the input run length signals RL5 to RLO.
This is a select signal for outputting to Y1 or Y2. Run length counter 602 is a 12-hit binary counter. After presetting the initial value of the minute TT multiplied signal run length counter 602 (loading the output of the multiplexer 601) shown at 606, the CNTEN shown at 605
When the counter is enabled by the signal, the run length counter 602 sequentially counts up. Then, the counter output (QO-Ql 1) is all
, that is, when the value reaches -1>, the output of the gate) 603 becomes 0, and the inversion circuit 607 outputs the count end pulse HCRO6.
04 is output and the counting operation is also stopped.

Next, in FIG. 7, address counter A1 shown in FIG.
1l, line buffer memory A112.11 under the control of address counter B117. Line buffer memory B113
The processing of image No. 0 read out will be explained. 7th
In the figure, 114 is an image conversion circuit, and the selector 11
41, virtual change point generation circuit 1142, change point detection circuit 1
Consists of 143. The selector circuit 1141 is shown in FIG. In FIG. 8, 801 is an AND circuit, 802 is an OR circuit, and 803 is an inversion circuit, which switches the read data 901 of the line buffer memory A 112 and the read data 902 of the line buffer memory B 113 to image 1 line σ, and uses a signal 903 to convert the reference image. signal 9
This circuit is selected as 04.

Next, the virtual change point generation circuit 1142 is shown in FIG. That is, in FIG. 9, 804 is an AND circuit, 805 is an inversion circuit, 806 is an OR circuit, and 807 is a flip-flop. The color of the last pixel of the line image signal 904 is latched into the flip-flop 807, and the color of the next pixel (virtual pixel) is set as a contradictory color so that the horizontal synchronization signal indicates the valid section of each line. This circuit selects the Q output of the flip-flop 807 according to the falling edge of the signal 906.

Next, the change point detection circuit 1143 is shown in FIG. i.e. i
In the lo diagram, 1001 is a flip-flop, 100
2 is an exclusive OR circuit, and 1003 is an inverting circuit. As shown in the figure, the output 907 of the virtual change point generation circuit 1142 is input to the flip 70 tube 1001 and the exclusive OR circuit 1002, and the exclusive OR circuit 1002 calculates the exclusive OR of the Q output of the flip flop 1001 and the input signal 907. Detects the change in color of adjacent pixels by
This circuit outputs a change point detection signal 909.

Circuits 1142 and 1143 shown in FIGS. 9 and 10
FIG. 11 shows an operation timing chart.

In FIG. 1, 115 is a shift register A consisting of a 4-bit shift register, and the circuit is shown at 115 in FIG.

That is, the reference line image data 908 input from the change point detection circuit 1143 to the SI is stored in the register A115.
The signals are sequentially shifted in the direction from Q1 to Q4 by a clock. Also, the contents of the 4 bits of register A115 are always 9.
10 in parallel (CI-C4). Therefore, individual color information for four consecutive pixels on the reference line is output in parallel from the shift register A115.

The shift register B116 shown in FIG. 1 is also a 4-bit shift register, and the circuit is shown at 116 in FIG. is sequentially shifted in the direction of Q1→Q4 in the register B116 by the clock as data. Further, the contents are always output in parallel as 911 (Bl-84).

Therefore, information indicating the presence or absence of a change point in four consecutive pixels on the reference line and the position of the change point is output in parallel from the shift register B116.

Next, the Pv matching circuit 105 shown in FIG. 1 is shown in FIG.
In FIG. 12, 1201 and 703 are exclusive OR circuits, 1202 and 704 are AND circuits, 1203 and 705 are NAND circuits, and 1205 is an inverting circuit. 301
is an 8-bit latch and the code detection logic 1 shown in Figure 5.
04 detects that the code stored in register CI '03 is a P code or V code, the bits corresponding to each detected code are set to "I II" and the others are set to "°O'°. Receives and stores data. The stored data is used for verification during decoding in P mode or ■ mode. The signal Bl-B4 in FIG. 12 is the signal 911 from the register Bl 16 shown in FIG.
1 to C4 are signals 91 from the register A115 shown in the seventh figure.
It is 0. The aQ signal in FIG. 12 is a symbol aO (hereinafter referred to as aQ, the same applies to other symbols) in the two-dimensional encoding method, and indicates the color of the starting pixel at each decoding time point.

In FIG. 12, the exclusive OR circuit 703 and the AND circuit 704 are represented by a symbol b1, which is a shift register A11 shown in FIG.
This is a circuit that detects that the 12th
The illustrated flip-flop 303 is a circuit that stores that the symbol b1 has already been detected at the above position. Further, 302 is a 3-bit shift register, which is a circuit that outputs the symbol b1 detected by the AND circuit 704 from SI, and then stores it while shifting it from Q1 to Q2 to Q3 for 3 clocks. Shift register B11e
If there is a change point b1 within the three pixels connected to the B4 output of , the output of the AND circuit 1202 corresponding to that position becomes 1,
Furthermore, if there is a change point b1 within three pixels before the B4 output, the output of the shift register 302 corresponding to that position is 1. The other circuits in FIG. 12 are the P or V decoding information held by the latch 301 and the flip-flop 30.
3. Shift register 302. This is a circuit that compares the reference line information obtained from the AND circuit 704, etc., and if 19 conditions are met, the PVHiT shown in 701 or 702
For example, when VR(2) is latched in latch 301, when the output of shift register 302 becomes 1, VL(2) is latched in latch 301. In this case, when the output of the AND gate 1202 becomes 1, the respective VHiT
Output.

Note that PVHiT indicates the end of decoding of the V mode code and P code, and the mode determination of the primary code is executed by this PVHiT.

The shift control circuit 108 shown in FIG. 1 is illustrated in FIG. That is, 1301 is a 4-bit binary full adder, and 1302 is a 4-bit latch. full adda 13
01 and the latch 1302 constitute a 4-bit binary accumulator. Input to full adder 1301 SO~S
3 signals are code detection logic 104 or code detection logic 104 in FIG.
Obtained from table ROM 1 '06. Register C
Corresponds to the required movement amount in one clock of the code in lO3. Note that the required movement amount obtained from the ROM 106 is always 1.

In the end, the accumulator by the full adder 1301 and the latch 1302 is accumulating the number of empty bits in register C resulting from the course of the movement of data in register ClO3. Also, the output CR (carry) of the full adder 1301, Σ
1 to Σ4 indicate the number of empty bits in the register ClO3 that can be created by executing the move currently input to 5o-S3 of the full adder 1301. When CR (=16) is being output at this point, an update request signal 201 (FIG. 2) is output to the memory circuit 101 shown in the first diagram, and new data (16 bits BO to B15) is sent from the memory circuit 101 to the register Cl.
Add to O3.

Signals 5o-53 are O-9 (as shown in Tables 1 and 2).
For example, if the latch 1302 indicates 15 (decimal) and 5o-S3 indicates 9, the integrated value will be 9+15=24. At this time, executing a 9-bit jump shift in register ClO3 creates 24 empty bits, so a new code is added from the storage circuit 101 shown in the first diagram, but register C
Since lO3 has a 31-bit configuration, 3l-24=7 bits of output CO to C6 (moved from 09 to C15 in Figure 3) are valid bits, and 07 to C30 are empty bits (
= invalid code). At this time, the new code (16 bits) read out in parallel by the upper storage circuit 101 is stored in the register ClO3 so that the code in the register ClO3 is not interrupted.
The storage location of zero or more newly added codes added to the positions C7 to C22 of O3 is controlled by the circuit 130 in FIG.
3 outputs signals STI to ST8 to the multiplexer A1022 shown in FIG. 3 to cause the multiplexer to perform a selective operation. That is, control is performed so that a valid code always exists in the 16 bits C7 to C22 of register ClO3.

Next, the image reproduction circuit 110 of FIG. 1 is shown in FIG. 14. In FIG. 14, 1407 is an OR circuit, 1408 is an inversion circuit, 1409 is a NAND circuit, and 1410 is an AND circuit. That is, Q output of flip-flop 1401 = 14
02 is an image resulting from decoding which is the purpose of the decoding operation, and as shown in FIG. 1, it can be sent to a printer such as a laser beam printer and the actual image output can be printed on recording paper. Also, the flip-flop 1401 receives the VHiT signal 701 (Fig. 1.2) indicating that the V mode code is matched with the symbol b1 on the reference line, or the run length counter 602 shown in Fig. 6 is the terminating code. TE ND signal 140 based on the HCRO signal indicating that the run length value indicated by has been counted has been completed.
(output) is inverted by 4. Further, the flip 70 knob 1403 is a circuit that stores that the run length counter 602 shown in the sixth figure is currently counting the run length indicated by the terminating code. That is, due to the Q output of this flip-flop 1403, the flip-flop 1401 is not inverted and the color of the image is not changed by the HCRO signal 604 at the end of the make-up run length count.

Furthermore, the flip-flop 1401 does not perform an inverting operation due to the P-mode verification method signal PVHIT.

Next, as an example, a specific operation will be explained when this embodiment reproduces (decodes) an image as shown in FIG. 15 as a decoding result. In Fig. 15, 1501 is a virtual line and is not an actual image, and 1502 and 1503 are the first line and second line, respectively, which are actual images, and in this example, each line is made up of 16 pixels. shall be.

Furthermore, each pixel 1504, 1505, and 1506 shown in FIG. 15 is a virtual pixel generated by the virtual change point generation circuit 1142 (FIG. 7), and is not an actual image.

In other words, it is assumed that the image shown in FIG. 15 in this example constitutes one page with two lines, and each line has 16 pixels. Therefore, the code information shown in FIG. 16 obtained by encoding the image shown in FIG. 15 is stored in the storage circuit 101 (FIG. 1).
An example of how the image shown in FIG. 15 is reproduced will be described below. Furthermore, prior to decoding, the number of pixels per image line is constant within one page and has already been made clear to the decoding circuit according to the regulations of the encoding method.

Figure i17 shows the relationship between the reference line and each symbol when decoding the first line. Moreover, FIG. 18 shows the state when the second line is decoded.

Further, FIG. 19 is a timing chart of the decoding operation. As is clear from the timing chart of FIG. 19, this decoding operation is executed in accordance with the image clock indicated by 1915.

The H3YNC signal indicated by 120 in FIG. 19 is a horizontal synchronization signal synchronized with the printing operation for each line, for example, which is given from the outside of the printer 119 in FIG. After all, the horizontal synchronization signal 120 is decoded one line at a time in synchronization with the
is used as a trigger signal to start decoding one line at a time.

Signals 1901 and 1902 in FIG. 19 are signals CNTENI and CNTEN2 for permitting the counting operations of address counters A11l and B117 shown in FIG. 7, respectively.

1903 in FIG. 19 indicates the output value of the address counter A11l which starts counting in response to the above-mentioned CNTENI signal, and this count value is given as a memory address to the line buffer memory A112 shown in FIG. 7 as described above. Also, 1904 in FIG. 19 is the output 190
3, the memory address for the line buffer memory 2 shown in FIG. 7 is shown.

908 and 910 in Figure 19, 909 and 911 are the 7th
Each input/output signal of the illustrated shift register A and shift register B is shown, and each waveform of the illustrated signal is the first
This corresponds to the image in Figure 5.

In addition, the backup memory A and the buffer memory B shown in FIG. 7 alternately read/write to each other as shown in FIG. 19, and the read side always precedes the write side by 5 hours. controlled. This is because the code data decoding operation can only be executed when the change point information and color information regarding the first pixel of the reference line reach the output Q4 of the shift registers B and A shown in FIG. Note that this number of clocks may be other than 5 depending on the number of bits of the shift register and the number of latches for timing alignment of decoding operations.

FIG. 20 shows the movement of the code in the register ClO3 shown in FIG. 3 during decoding of the first line (1502 in FIG. 15). In FIG. Backup memory A starts a read operation. At this time, buffer memory A
The data read out is a reference line, but due to the encoding method regulations, a virtual margin line is read out as a reference line for decoding the first line (in other words, the contents of buffer memory A are cleared in the initial state (all 0)).

Now, as described above, it is assumed that the code data in the register ClO3 (hereinafter abbreviated as register C) shown in the third figure is in a state where preparation for starting decoding is completed, that is, in the state shown in FIG. 20(A). Now, at time t-1 in FIG. 20, the H mode code and the W1 code are simultaneously detected from the outputs CO to C8 of the register C by the code detection logic 104 shown in FIG. As a result, it is determined that the code is input in horizontal mode, and the two's complement of the run length value 1 of Wl -1> is the sixth
is loaded into the ANF input of the illustrated run length counter 602. Note that 1 is loaded into GM of the run length counter 602, respectively. Also, at this time, the fact that the first terminating code of H mode (i.e., Wl in this case) has been detected is stored in the flip-flop etc. (1913 signal in Fig. 19), and the code length of Wl is stored. is 6
Moreover, since Wl is a jump code as described above, a 6-bit shift (ie, a 6-bit jump) is executed to register C in one time. Also, since Wl is a terminating code, at the same time as the run length value is loaded, the flip-flop 1403 in FIG. (Fig. 19 1908
).

Eventually, at time 1 (, register C is in the state shown in FIG. 20 (B) (
State 8 after performing a 6-bit shift from the state at time t-1
). Also, the TEND signal 1404 in FIG. 14 is output, and the output of the flip-flop 1401 is inverted, resulting in one time after time t□=tl), and the color of the image changes from white to black as shown at 1910 in FIG. .

Further, the BIH code is detected again from the outputs of the registers C103C3 to C6 in the state shown in FIG. 20(B) (because this is the second terminating code in the H mode) by the TEND signal at time t□t'HcRo. Bl)
(The code has a run length value l Cm!=<-1>) and has a code length of 3, and since the Bl)l code is a jump code, the run length counter 602 is loaded with -1> again. Upon detection of this B11 (code), the decoding of the H mode code is completed, and the next code is decoded. In this case, the first bit of the next code is transferred to the register Cl.
03(7) Register C10 to set CO high output position
3 (7) The data is jump-moved by 6 bits, which is the BIH code length 3 plus the H code code length 3.
The state will be as shown in Figure 0 (C). Eventually, the flip-flop 1404 shown in FIG. 14 is inverted at HCRO at time t1 (
The result is L2).

At time t1, register ClO in fpJ20 diagram (C) state
3 to detect the H mode code and W4 code. Thereafter, the operation is the same as in the state shown in FIG. 20(A).

Next, at time t5, the register ClO3 in the state shown in FIG.
Detects the B6 code. Since the code length of the B6 code is 4 and it is not a jump code, first, the register ClO3 moves 1 bit at a time every 4 times (4 clocks) from time t5, and reaches the state shown in FIG. 20(E) at t9. or,
At this time, B6 was detected as the second terminating code in H mode, and in this case, control is performed to perform an additional 3-bit jump in order to position the beginning of the next code at the CO high output position of register ClO3. (t9
), and the result is output at t10), and eventually the register ClO
3 is ti.

CF) in Figure 20.

Then, when HCRO is output at t11, the flip-flop 1401 in FIG. 14 is inverted and the register ClO is again
3 to detect the V(0) code, but this time it is the V mode φ code, so the V(0) code of the latch 301 shown in FIG.
O) Set the bit to ``1'' (Others are °゛0°°
). Also, since it is not the H mode, the run length counter 602 in FIG. 6 is not activated (HCRO is not output after all). The V (O) bit in the latch 301 is compared in the NAND circuit 705 with the symbol b1 from the AND circuit 704 to which the output of the shift register B116 shown in FIG. 7 is input in FIG.
VH4T by NAND circuit 705 and OR circuit 1202
Wait until the signal is output, flip-flop 14 in Figure 14
Invert 01. In the end, the reproduced image is 19 in Figure 19.
It will be like 10. The valid section of the reproduced image at this time is the first
This is indicated by the 1914 signal in FIG. In addition, the image indicated by 1910 is output from the printer 119 and is also sent to the line buffer B, which is executing a writing operation in parallel to be used as a reference line for decoding the next second line.
113. The reproduced image is also used as the symbol aQ. In this way, images can be reproduced (decoded).

As is clear from the above description, a common image clock is supplied to each block of the circuit of this embodiment from the control circuit 118 (FIG. 1), and the decoding operation is executed in synchronization with this image clock. , the decoding operation is performed at a speed corresponding to the clock interval (period). Further, if the supply of this clock is stopped, the decoding operation is also stopped during the stop period. Therefore, the speed of the decoding operation can be controlled by changing the interval of the clock commonly supplied to each block of the decoding circuit.

Due to this speed and pause control, the data processing speed of printers, computers, etc. that accept decoded images is not limited by the decoding speed, and conversely, the processing of subsequent printers, etc. that process decoded images If a clock matched to the speed is used as a reference for the decoding operation, the decoding operation will be performed in accordance with the processing speed of the subsequent stage, so that, for example, a common decoding circuit can be used for a plurality of printers with different processing speeds. In addition, even if the subsequent processing device is a device such as a computer that intermittently captures a predetermined amount of data, a clock is supplied to the decoding circuit according to the capture period, and the clock supply is stopped during other periods. Then, the decoding operation can be executed in accordance with the intermittent processing of a computer or the like.

The decoding method described above can provide the following effects. That is, (1) One image can be reproduced (decoded) without interruption in synchronization with continuous clocks for one line, and each line can also be reproduced continuously and synchronously. If the reproduced image is output to a laser printer or the like, an image output can be obtained immediately (ie, real-time decoding).

(2) High-speed decoding is always guaranteed regardless of the complexity of the image and the compression code. (In actual measurements, both main and sub-scanning densities were 16 pel/25.4 mm (F)
A3 size images can always be processed in 1.5 seconds. (3) In the case of high-speed image output, it is possible to directly reproduce and output an image from the compressed code without preparing a certain amount of decoded images in advance in memory, as is usually done, so memory and the like can be saved.

In addition, in the above explanation, the decoding process of two-dimensional encoded data using the relationship with the reference line was explained, but MMR
It is applicable not only to encoding, but also to MR encoding, etc. in which -dimensional encoding and two-dimensional encoding coexist. Note that the data to be decoded may be output from a computer, data transmitted by facsimile, or the like.゛Table 1 Table 2 (ff) The * mark indicates the case of the second terminating code in H mode [Effect] As explained above, according to the present invention, the reference line for the pixels necessary for decoding the image code is Since the decoding operation is started after capturing the image signal, the decoding operation can be executed accurately and can be achieved at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a decoding circuit to which the present invention is applied;
Figures 2 (A) and (B) are diagrams representing codes to be decoded;
FIG. 3 is a diagram showing an example of the configuration of a bit shifter, FIG. 4 is a diagram showing an example of the configuration of the code table ROM, FIG. 5 is a diagram showing an example of the configuration of the code detection logic, and FIG. 6 is the configuration of the run length count circuit. 7 is a diagram showing an example of the configuration of a reference line image signal processing circuit, FIG. 8 is a diagram showing an example of the configuration of a selector circuit, and FIG. 9 is a diagram showing an example of the configuration of a virtual change point detection circuit. 10 shows an example of the configuration of the change point detection circuit, FIG. 11 is a timing chart showing the operation of FIGS. 9 and 10, and FIG. 12 shows an example of the configuration of the PV matching circuit. , FIG. 13 is a diagram showing an example of the configuration of a shift control circuit, FIG. 14 is a diagram showing an example of the configuration of an image reproduction circuit, FIG. 15 is a diagram showing an example of a decoded image signal, and FIG. 16 is a diagram showing an example of a decoded image signal. 17 and 18 are diagrams showing the decoding operation of the first line and the second line, FIG. 19 is a timing chart diagram showing the decoding operation, and FIG. 20 is a diagram showing the register shift operation. This is a diagram showing 101 is a recording circuit, 102 is a multiplex reflex sensor, 103 is a register C1, 104 is a code detection logic, 105 is a pv matching circuit, 106 is a code table ROM, 107 is a run length count circuit, 112, 113 is a line buffer memory, 114 is a ° image It is a conversion circuit. (,4)

Claims (1)

[Claims] means for capturing image signals of reference lines used for decoding input image codes; means for sequentially discriminating input image codes; discrimination results of the discriminating means and image signals of reference lines captured by the capturing means; and means for forming an image signal based on the relationship between the image code and the image code, and the decoding operation is started after the capturing means captures the image signal of the reference line for the number of pixels necessary for decoding the image code. Code decoding device.