JPS62281162A - Disk motor control circuit for disk recording and reproducing device - Google Patents

Abstract

PURPOSE:To stabilize the line velocity constant state of a disk rotation at the additional recording by changing a digital code signal sequentially after the reproducing state is switched into the recording state so as to change the rotating speed of a disk motor and correcting a digital code at recording by information from a rotating speed detector and a recording position detector. CONSTITUTION:In applying the additional recording in succession to the recorded part already, if an RF signal is lost, an output of an AND gate 181 goes to '0' and a clock frequency switching circuit 19 switches a counter clock CK1 into a low frequency to activate a clock generator 20. On the other hand, the clock CK1 is fed to a down control terminal D of a counter 187, an output voltage level of a D/A converter 188 is lowered gradually and the rotating speed of the disk motor 23 slows down as the recording is progressed. The rotation is detected by a rotation detector 24, fed to the clock generator 20 and compared with a frequency signal F26 corresponding to the position and the number of revolutions of the disk motor 23 is corrected so as to correspond to the write position of a transducer at all times.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) This invention relates to a disc recording and reproducing device that records information signals on a disc and reproduces the information signals from the disc. In particular, the present invention relates to something that allows additional recording to be performed following the already recorded green portion.

(Prior Art) Recently, the development of a disk recording and reproducing apparatus that records information signals on, for example, an optical disk and reproduces the signals has been progressing. Various recording methods have been considered for this device, but in any case, it is necessary to enable additional recording. In this case, in order to effectively utilize the recording capacity of the disc, it is desirable to be able to detect the end of the recorded green portion and record new information following the recorded edge information.

However, in the above-mentioned disk recording and reproducing apparatus, in order to obtain a constant S/N ratio from the inner circumferential side to the outer circumferential side of the disk, recording and reproducing are generally performed by rotating the disk at a constant linear velocity. Therefore, when additional recording is performed, the information for controlling the rotation of the disk cannot be obtained at the time of switching from reproduction to recording, or the information is switched to other information, resulting in disordered rotation of the disk.

For this reason, the synchronization cycle breaks down at the boundary of additional recording, so in the past, it was necessary to either leave a sufficient gap between the previously recorded green area and the additionally recorded area, or record unnecessary data until the disk rotation stabilized. I am taking a method. However, this is not preferable because the recording capacity of the disk is substantially reduced.

(Problems to be Solved by the Invention) This invention improves the problem that in conventional devices, the rotation of the disk is disordered when switching from playback to recording. Another object of the present invention is to provide a disk motor control circuit for a disk recording and reproducing apparatus that can stabilize the constant linear velocity of disk rotation and increase the substantial storage capacity as a result.

[Configuration of the Invention (Means for Solving Problems) That is, the disc motor control circuit of the disc recording and reproducing apparatus according to the present invention is used in a disc recording and reproducing apparatus that records and reproduces information signals on a recordable disc. , which extracts a synchronous signal from the information signal recorded on the disk, generates an automatic frequency control signal and an automatic phase control signal from the synchronous frequency and synchronous phase, and controls the rotational speed of the disk motor based on these control signals. a digital encoding means for synthesizing the automatic frequency control signal and the automatic phase control signal and converting the signal into a digital code; and a first circuit for driving the disk motor based on the code signal converted by the digital encoding means. a driving means;
digital code variable means for sequentially changing the code signal in accordance with a synchronization signal of the recording signal during recording; a second driving means for driving the disk motor based on the code signal changed by the digital code variable means; a rotational speed detector that detects the rotational speed of the disk motor; a position detector that detects the position of a recorder that records information signals on the disk; and each information obtained by the rotational speed detector and the position detector. and a digital code correction means for correcting the digital code at the time of recording based on the FiFi.

(Function) In other words, in the playback state, the disk motor control circuit of the disk recording and playback device with the above configuration converts the automatic frequency control signal and the automatic surface control signal into a digital code, and converts it into a digital code based on the code signal. After driving the disc motor and switching from the playback state to the recording state, the digital code signal is sequentially changed to change the rotational speed of the disc motor, and each information from the rotational speed detector and the recorder position detector is By correcting the digital code during recording based on this, the rotation of the disc is prevented from being disturbed even when switching from the playback state to the recording state.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Here, we will discuss the case of an optical disc recording and reproducing device.The optical disc has a tracking guide groove formed in a spiral shape from the inner circumference to the outer circumference, and the recording and reproducing device moves along the guide groove of the disk. The information signal is recorded and reproduced by forming or detecting pits corresponding to the information signal (data) by irradiating the information signal with a light beam.

FIG. 1 shows its configuration, and the RF signal (frequency signal corresponding to data created in a predetermined recording format) obtained by reproducing a disc (not shown) is an RF signal detection circuit! 1, it is supplied to a frequency detection circuit 12, a phase detection circuit 13, and a sample pulse generation circuit 14. The RF signal detection circuit 11 outputs a signal of "1" or "0°" depending on the presence or absence of the RF multiplied signal.The frequency detection circuit 12 detects the frequency fluctuation of the synchronization signal in the RF signal. The detection signal is output as an AFC (automatic frequency control) signal.The phase detection circuit 13
It also detects the phase change of the synchronization signal in the signal.

Therefore, the detection output is output as an APC (automatic phase control) signal. The sample pulse generation circuit 14 detects a synchronization signal from the RF multiplied signal in the synchronization signal detection circuit 141, and sets the count operation timing of the synchronization cycle generation counter 142 at the detection timing to obtain a signal that matches the synchronization cycle. This synchronization period signal is then input to the pulse generation circuit 143 to generate a sample pulse SP corresponding to the synchronization period.

On the other hand, both the AFC signal and the APC signal are sent to the adder 15.
After being added to the level comparator (COMP) 7 via the amplifier CAMP) 1B, the group ! It is compared with the f1 voltage VTI+. The comparison result of the level comparator 17 is supplied to the drive signal setting circuit 18 together with the output of the RF signal detection circuit 11.

The level comparator [
7 and the output of the RF signal detection circuit 11 are A.
The signal is supplied to the ND gate 181. This AND gate 18
1 is supplied to one input terminal of the first NAND gate 1g2, and is also supplied to the second NAND gate 1g2 via the inverter 183.
It is supplied to one input terminal of AND gate 174. 1st
A counter clock CKL from a clock generation counter (not shown) is input to the other input terminals of the second NAND gates 182 and 184, respectively, to the clock frequency switching circuit 1.
9. This clock frequency switching circuit 1
9 sets the clock frequency high during reproduction and low during recording. First NAND gate 18
The output of the second NAND gate 185 is supplied to one input terminal of the third NAND gate 185, and the output of the second NAND gate 184 is supplied to the fourth
is supplied to one input terminal of a NAND gate 186.

The other input terminals of the third and fourth NAND gates 185 and 186 are respectively supplied with clocks CK2 and CK3 from a clock generator 20, which will be described later.

The output of the fourth NAND gate 186 is used as the amplifier signal U, and the output of the third NAND gate 185 is used as the down signal.
supplied to This up/down counter 187 has a count value set to an initial value by a preset pulse PP, and increases or decreases the count value according to the human power of the up signal and down signal U, and the count value is
(digital to analog) converter 188.

This D/A converter 188 outputs a voltage signal V18 corresponding to the input count value, and this voltage signal VL8 is supplied to the sample hold (S/H) circuit 18.

This sample and hold circuit 21 samples and holds the voltage signal from the D/A converter 188 every time the sample pulse SP generated by the sample pulse generation circuit 14 is input, and the voltage held here is based on the above-mentioned standard. It is supplied to the level comparator 17 as the voltage VTI+, and also supplied to the disk motor 23 via the amplifier 22 as a drive signal.

This disk motor 23 is provided with a rotation detector 24 that outputs a frequency signal F24 corresponding to its rotation speed, and the output F24 of this rotation detector 24 is transmitted to the waveform shaping circuit 2.
5 (F25), and then supplied to the clock generator 20. The clock generator 20 is also supplied with a frequency signal F2G from the position detection circuit 26. This position detection circuit 2G detects the position of a write transducer (not shown) that records signals on the disk, and outputs a frequency signal (or DC level signal) corresponding to that position as transducer position information. It is something. The clock generator 20 generates a clock pulse CK2°C when the output of the RF signal detection circuit 11 is “O”.
K3 is generated, and this clock pulse CK2°CK3 is selectively supplied to the third and fourth NAND gates 185 and 188 of the drive signal setting circuit 18 according to the frequency phase difference (or DC level difference) between the two inputs. It is something to do.

The operation of the above configuration will be described below with reference to FIG.

First, in the disc playback state, since an RF multiplied signal is supplied, the RF signal detection circuit 11 detects this and as shown in FIG.
) outputs a signal of “1”. This RF detection signal is supplied to the AND gate 181 and also to the clock frequency switching circuit 19 and the clock generator 20. At this time, the clock frequency switching circuit 19 switches the count clock CKI to a high frequency as shown in FIG. 2(b), and the clock generator 20 stops operating as shown in FIG. 2(c) and (d). clock CK2゜CK3
is in the “1” level state.

On the other hand, in the frequency detection circuit 12 and the phase detection circuit 13, R
An AFC signal and an APC signal are generated from the F-fold signal. After these AFC signals and APC signals are added by an adder 15, the voltage VTI currently driving the disk motor 23 is
Compared to I. Here, if the AFC+APC signal is greater than VTH, the output of the level comparator 17 becomes "1", so the output of the AND gate 181 becomes "1". At this time, the clock CKI is applied to the first and third NAND gates 1
It is supplied to the up control terminal U of the counter 187 via 82 and 185. Therefore, the count value of counter 187 increases, and the output voltage of D/A converter 188 increases. Conversely, if the AFC+APC signal is smaller than VTI+, the output of the level comparator 17 will be O", so the AND gate
.

- The output of port 181 becomes "0". At this time, the clock CKI is connected to the second and fourth NAND gates 184°186
is supplied to the down control terminal of the counter 187 via the counter 187. Therefore, the count value of the counter 187 decreases,
The output voltage of D/A converter 188 also decreases. Through the above control, the disk motor 23 is controlled to rotate in synchronization with the reproduction signal, that is, at a constant linear velocity.

Next, when additional recording is to be performed following the previously recorded portion, the disc is first reproduced to detect the end of the recorded portion. This can be detected by detecting the presence or absence of the RF multiplication signal. In other words, when the RF multiplied signal disappears, the output of the RF signal detection circuit 11 becomes "0", which causes the output of the AND gate 181 to become "0" as shown in FIG. 2(a), regardless of the output of the level comparator 17. ”. Also, at this time, the clock frequency switching circuit 19 selects the counter clock C.
KI is switched to a low frequency as shown in FIG. 2(b), and the clock generator 20 becomes operational.

On the other hand, in the drive signal setting circuit 18, the 18
Since the output of the clock frequency switching circuit 19 is "O', the clock CKI output from the clock frequency switching circuit 19 is "O'".
It passes through the NAND gate 184 and is supplied to the down control terminal of the counter 187. Since the counter 187 decreases the count value each time the clock is input, the D/
The output voltage level of A converter 188 gradually decreases (
. Therefore, the rotation of the disk motor 23 becomes slower as recording progresses.

Here, the rotation of the disk motor 23 is detected by the rotation detector 2.
4, the frequency signal (
or DC level signal) Waveform shaping circuit 25 as F24
sent to. The frequency signal F24 input to the waveform shaping circuit 25 is waveform-shaped as shown in FIG. 3(b) and sent to the clock generator S20. Also, during recording, the position of the write transducer that records signals on the disk is detected by the position detection circuit 26, and the frequency signal (or DC level signal) F26 corresponding to that position is generated as the position information of the transducer. clock generator 2
Sent to ゜. At this time, the clock generator 20 receives the internal input signal F25. Compare F2B, and if F2O is lower than the frequency of F25 (or smaller in terms of DC), NA
A lock CK2 is sent to the down control terminal of the counter 187 via the ND gate 185 as shown in FIG. A lock CK3 is sent to the up control terminal U of the counter 187 via the gate 18G as shown in FIG. 2(d). Therefore, counter 1
The count value of 87, ie, the rotational speed of the disk motor 23, is always corrected to correspond to the writing position of the transducer. Therefore, even during recording, the rotation of the disk motor 23 is controlled so that the linear velocity is constant. Note that if the switching from the reproduction state to the recording state is performed at a position half a cycle of the synchronizing signal part, there is no fear that the data part will be corrupted.

Here, the above operation is for the case of additional recording following the already recorded part, but when recording on an unused disc, the RF multiplied signal cannot be obtained during playback, so the count value of the counter 187 is set to a predetermined value by the preset pulse PP. and set the rotation speed of the disk motor 23 at the recording start point to an appropriate value. At this time, as described above, the clock generator 20 becomes operational, and the rotation speed of the motor 23 is corrected and controlled. Also, at the start of reproduction, the count value of the counter 187 is preset using the preset pulse PP to set the initial state. In the above configuration, using the clock frequency switching circuit 19, the counter clock C
The KI frequency is switched between reproduction and recording, and this is done in order to increase the responsiveness to the synchronization signal by increasing the counter clock frequency during reproduction.

Therefore, when performing additional recording, the disk motor control circuit with the above configuration can perform additional recording between the previously recorded part and the additionally recorded part without any gaps and without breaking synchronization. There's no chance of things going out of sync or going out of sync.

Note that this invention is not limited to the above embodiments,
For example, a microcomputer 27 may be used as shown in FIG. In FIG. 4, the same parts as in FIG. 1 are designated by the same reference numerals. That is, in this circuit, when the power is turned on (step a), the microcomputer 27 gives a constant value to the D/A converter 188 (step b), as shown in FIG. Rotate at a specified speed. Here, when a reproduction operation or a recording operation is performed, a start signal St is supplied to the microcomputer 27. When the microcomputer 27 inputs the start signal St (step c)
Step d): Determine whether or not an information signal is recorded on the disc based on the information from the RF detection circuit 11. If so, input the determination value of the level comparator 17. Step e): Record the RF multiplied signal. If not, the frequency signal F 2 from the waveform shaping circuit 25 and the position detection circuit 26
5. Enter F2B.

(Steps f, g). Then, each count value at the time of reproduction or recording is generated from each input information, and the D/A converter 188
(step h), and the output value of disc motor 2 is changed (step h).
3 is driven and controlled so that the linear velocity is constant. When the start signal St disappears (step i), the microcomputer 27 sets the count value sent to the D/A converter 188 to zero, stops driving the motor 23 (step j), and ends its operation ( Step Ic). In this way, various modifications can be made without departing from the spirit of the invention.

[Effects of the Invention] As described in detail above, according to the present invention, when additional recording is performed following an already recorded portion, it is possible to stabilize the constant linear velocity of the disk rotation, resulting in substantial improvement. It is possible to provide a disk motor control circuit for a disk recording and reproducing device that can increase storage capacity.

[Brief explanation of drawings]

FIG. 1 is a block circuit configuration diagram showing an embodiment of a disc motor control circuit of a disc recording/reproducing apparatus according to the present invention, and FIGS. 2 and 3 are timing diagrams for explaining the operation of the embodiment, respectively. FIG. 4 is a block circuit configuration diagram showing another embodiment of the present invention, and FIG. 5 is a flowchart for explaining the operation flow of the circuit shown in FIG. 4. DESCRIPTION OF SYMBOLS 11... RF signal detection circuit, 12... Frequency detection circuit, 13... Phase detection circuit, 14... Sample pulse generation circuit, 141... Synchronization signal detection circuit, 142
...Synchronization period generation counter, 143...Pulse generation circuit, 15...Adder, 17...Level comparator, 1
8... Drive signal setting circuit, 187... Up/down counter, 188... D/A converter, 19... Clock frequency switching circuit, 20... Clock generator, 21
...Sample hold circuit, 23...Disk motor, 24...Rotation detector, 25...Waveform shaping circuit, 2
B...Position detection circuit, 27...Microcomputer. Applicant's agent Patent attorney Takehiko Suzue Figure 2 Figure 3

Claims (1)

[Claims] Used in disc recording and reproducing devices that record and reproduce information signals on recordable discs, extracts synchronization signals from the information signals recorded on the disc, and generates automatic frequency control signals and automatic phase control signals from the synchronization frequency and synchronization phase. Then, in a disk motor control circuit of a disk recording/reproducing device that controls the rotational speed of a disk motor based on these control signals, digital coding is performed in which the automatic frequency control signal and the automatic phase control signal are synthesized and converted into a digital code. means, first driving means for driving the disk motor based on the code signal converted by the digital encoding means, and a variable digital code for sequentially changing the code signal in accordance with the synchronization signal of the recording signal during recording. a second means for driving the disc motor based on the code signal changed by the digital code changing means;
a rotational speed detector for detecting the rotational speed of the disk motor, a position detector for detecting the position of a recorder for recording information signals on the disk, and the rotational speed detector and the position detector. A disc motor control circuit for a disc recording/reproducing apparatus, comprising: digital code correction means for correcting the digital code at the time of recording based on each piece of information obtained.