JPS62219367A - Disk motor control circuit for disk recording and reproducing device - Google Patents

Abstract

PURPOSE:To continuously execute recording without disturbing the synchronization, and to substantially increase the recording capacity, by holding a code signal converted at the time point when a reproducing state is switched to a recording state, and varying successively the code signal held after recording is started. CONSTITUTION:In a reproducing state, an automatic frequency control signal AFC and an automatic phase control signal APC are added by an adder 15 and converted to a digital code, and based on its code signal, a disk motor 21 is driven. In this state, at the time point when the reproducing state is switched to the recording state, the code signal is held temporarily, and by varying successively the code signal held after recording is started, the rotational speed of the disk motor 21 is varied. In this way, when the reproducing state is switched to the recording state, the synchronization is not disturbed between an already recorded information signal and a postscript recording information signal.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a disc recording and reproducing device that records information signals on a disc and reproduces the information signals from the disc, and particularly relates to Concerning what can be followed by additional recording.

(Prior Art) Recently, development of disk recording and reproducing apparatuses for recording information signals on, for example, optical disks and reproducing them has been progressing. Various recording methods have been considered for this device, but in any case, it is necessary to enable additional recording. In this case, in order to effectively utilize the recording capacity of the disc, it is desirable to be able to detect the end of the previously recorded portion and record new information following the previously recorded information.

However, in the above-mentioned disk recording and reproducing apparatus, in order to obtain a constant S/N ratio from the inner circumferential side to the outer circumferential side of the disk, recording and reproducing are generally performed by rotating the disk at a constant linear velocity. Therefore, when additional recording is performed, the information for controlling the rotation of the disk cannot be obtained at the time of switching from reproduction to recording, or the information is switched to other information, resulting in disordered rotation of the disk.

For this reason, the synchronization cycle breaks down at the boundary of additional recording, so conventional methods have been taken such as creating an interval between the already recorded portion and the additional recording portion, or recording unnecessary data. However, this is not preferable because the recording capacity of the disk is substantially reduced.

(Problems to be Solved by the Invention) This invention improves the problem that in conventional devices, the rotation of the disk is disordered when switching from playback to recording. , a disk for a disk recording/playback device that can record continuously without creating blank areas or writing unnecessary data, and without disrupting synchronization, thereby substantially increasing storage capacity. The purpose is to provide a motor control circuit.

[Structure of the Invention] (Means for Solving the Problems) That is, the disk motor control circuit of the disk recording and reproducing device according to the present invention adds an automatic frequency control signal and an automatic phase control signal and converts the sum into a digital code. digital encoding means; first driving means for driving the disc motor based on the code signal converted by the digital encoding means; and converting by the digital encoding means at the time of switching from the playback state to the recording state. digital code holding means for holding the code signal held by the digital code holding means; digital code changing means for sequentially changing the code signal held by the digital code holding means after the start of recording; and based on the code signal changed by the digital code changing means. and a second drive means for driving the disk motor.

(Function) In other words, in the playback state, the automatic frequency control signal and the automatic phase control signal are added and converted into a digital code, and the disc motor is driven based on the code signal, and the playback state is changed to the recording state. By temporarily holding the code signal at the time of switching from the playback state to the recording state, and changing the rotational speed of the disc motor by sequentially changing the code signal held after recording starts, the previously recorded information signal and the additional information are generated when switching from the playback state to the recording state. This prevents synchronization between recording information signals from being disturbed.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. Here, we will discuss the case of an optical disc recording and reproducing device.The optical disc has a tracking guide groove formed in a spiral shape from the inner circumference to the outer circumference, and the recording and reproducing device moves along the guide groove of the disk. The information signal is recorded and reproduced by forming or detecting pits corresponding to the information signal (data) by irradiating the information signal with a light beam.

Fig. 1 shows its configuration; an RF multiplied signal obtained by playing a disk (not shown); a frequency signal corresponding to data created in a predetermined recording format)
is supplied to an RF signal detection circuit 11, a frequency detection circuit 12, a phase detection circuit 13, and a sample pulse generation circuit 14. The RF signal detection circuit 11 detects “
It outputs a 1'' or 0'' signal. The frequency structure/output circuit 12 detects the frequency variation of the synchronizing signal in the RF signal, and the detected signal is output as an AFC (automatic frequency control) signal. The phase detection circuit 13 detects the phase change of the synchronization signal in the RF signal, and its detection output is output as an APC (automatic phase control) signal. The sample pulse generation circuit 14 detects a synchronization signal from the RF multiplied signal in the synchronization signal detection circuit 141, and sets the count operation timing of the synchronization cycle generation counter 142 at the detection timing to obtain a signal that matches the synchronization cycle. Then, this synchronization period signal is input to the pulse generation circuit 143 to generate a sample pulse S corresponding to the synchronization period.
It generates P.

On the other hand, both the AFC signal and the APC signal are sent to the adder 15.
After being supplied to the level comparator 1G and compared with the reference voltage VTH. This level comparator 1
The comparison result of No. 6 is supplied to the first AND gate 171 of the drive signal setting circuit 17 together with the output of the RF signal detection circuit 16. The output of this first AND gate 171 is
and a third AND gate 174 via an inverter 173. A counter clock CK from a clock generation counter (not shown) is supplied to the second and third AND gates 172 and 174, respectively. Second AND gate 172
The output of the third AND gate 174 is supplied as an up control signal U, and the output of the third AND gate 174 is supplied as a down control signal to an up/down counter 175. This up/down counter 175 has a count value set to an initial value by a preset pulse P1, and increases/decreases the count value according to input of an up control signal and a down control signal.
The count value is supplied to a D/A (digital-to-analog) converter 176. This D/A converter 176 outputs a voltage signal V17 corresponding to the input count value.
is supplied to circuit 18.

This sample hold circuit 18 is the pulse generating circuit 1
D every time the sample pulse SP generated in 43 is input.
The voltage signal V17 from the /A converter 17B is sampled and held, and the voltage held here is supplied to the level comparator 16 as the reference voltage VTH, as well as to the low pass filter (LPF) 19. This low-pass filter 19 removes unnecessary high frequency components from the input signal, and its output signal is supplied as a drive signal to the disk motor 21 via the amplifier 2°.

FIG. 2 shows a specific circuit configuration of the sample-and-hold circuit I8 and the low-pass filter 19. That is, the sample hold circuit 18 receives the sample pulse SP.
The FETL is turned on at the time of input, and the voltage signal V17 from the drive signal setting circuit 17 is held in the capacitor C1. Also, low pass filter 1
Reference numeral 9 denotes a simple feedback type integrating circuit composed of an operational amplifier OP, capacitors C2 and C3, and the like.

The operation of the above configuration will be explained below with reference to FIG.

First, when recording on an unrecorded disc, at the start of recording, the counter value of the counter 175 is set to an initial value by a preset pulse P1, and the output voltage of the D/A converter 17B is set to a predetermined voltage. That is, the disk motor 21 at the recording start point is set to an appropriate rotational speed. Then, when recording starts, the drive signal setting circuit 17
The clock CK is given to the At this time, since the RF multiplied signal is not obtained, the output of the AND gate 171 is "0".
It is. Therefore, the clock CK is the AND gate 17
4 to the down control terminal of the counter 175. Since the counter 175 sequentially decreases the count value each time the clock CK is input, the output voltage of the D/A converter 176 gradually decreases. Therefore, the rotation of the disk motor 21 becomes slower as recording progresses. Note that during recording, a half-period bone of the synchronization signal is added to the end of the recording.

Next, in the reproduction state, since the RF signal is supplied, the RF
The signal detection circuit 11 detects this and the AND gate 171
Sends a “1” signal to. In addition, the frequency detection circuit 12 and the phase detection circuit 13 output the AFC signal and the AP signal from the RF multiplied signal.
Generate C signal. After these AFC signals and APC signals are added by an adder 15, they are compared with the voltage VT11 currently driving the disk motor 21. AFC here
+If the APC signal is greater than VTll, level comparator 1
6 becomes 1", the output of the AND gate 171 becomes "1". Therefore, the clock CK is supplied to the up control terminal U of the counter 175 via the AND gate 172. Therefore, the output of the counter 175 becomes "1". The count value of D/A converter 176 increases, and the output voltage of D/A converter 176 increases.

Conversely, if the AFC+APC signal is smaller than VTH, the output of the level comparator IB becomes "θ', so the AND gate 1
The output of 71 becomes "O". Therefore, the clock CK is supplied to the down control terminal of the counter 175 via the AND gate 174. Therefore, the count value of counter 175 decreases, and the output voltage of D/A converter 176 also decreases. Due to the above-mentioned control i, the disk motor 21 is controlled in accordance with the synchronization in the reproduction signal, that is, to keep the linear velocity constant.

Furthermore, when performing additional recording, the disc is first reproduced to obtain a reproduced signal as shown in FIG. 3(a). At this time, in the sample pulse generation circuit 14, the synchronization signal detection circuit 141 detects the synchronization signal and synchronizes the generation timing of the synchronization period generation counter 142 with the detection timing. Therefore, the output SP of the pulse generation circuit 143 becomes low level at the first bit of the synchronization signal, as shown in FIG. On the other hand, when there is no reproduction signal, that is, when the RF multiplied signal cannot be obtained, the state is immediately switched to the recording state. At this time, the output of the RF signal detection circuit 11 is as shown in the figure (
As shown in C), the output of the AND gate 171 becomes "0" at the time of switching to the recording state. Therefore, the clock CK is supplied to the down control terminal of the counter 175 via the AND gate 174.

Thereafter, as in normal recording, the count value at the time of switching is decremented each time the clock CK is input. The drive is controlled by still,
Since the switching from the reproduction state to the recording state is performed at a position half a cycle of the synchronizing signal part, there is no worry that the data part will be corrupted.

Therefore, when performing additional recording, the disk motor control circuit with the above configuration can perform additional recording between the previously recorded part and the additionally recorded part without any gaps and without breaking synchronization. There's no chance of things going out of sync or going out of sync. This substantially increases the recording capacity.

Note that this invention is not limited to the above embodiments,
For example, it may be configured as shown in FIG. That is,
In this circuit, a data latch circuit 177 is interposed between the up/down counter 175 and the D/A converter 176 instead of the sample and hold circuit shown in FIG. This is done using pulse SP. In this case, since the hold voltage can be determined at a digital stage, a component can be used for the D/A converter 176.

Alternatively, it may be configured as shown in FIG. That is,
This circuit includes first and second switches SWI and SW2 in place of the sample and hold circuit shown in FIG. 1, and these switches SWt.

Switching of SW2 is controlled by a reproduction/recording switching signal P1. Then, during playback, the first switch SWI is closed, the second switch SW2 is opened, and the AFC+AP
The drive of the disk motor 21 is directly controlled by the C signal, while the output of the D/A converter 17B is made to follow the AFC+APC signal by the level comparator 18 and the drive signal setting circuit 17, and the first switch SW1 is opened at the time of recording. , the second switch SW2 is closed, and the output of one D/A converter (S) drives and controls the disk motor z1.

In this case, the circuit configuration is simple because only two switches are added without using a sample-and-hold circuit. In addition, various modifications can be made without departing from the gist of this invention.

[Effects of the Invention] As detailed above, according to the present invention, when performing additional recording following an already recorded part, it is possible to avoid creating a blank part or writing unnecessary data, and also to disturb the synchronization. It is possible to provide a disk motor control circuit for a disk recording and reproducing apparatus that can perform continuous recording without any problems, thereby substantially increasing storage capacity.

[Brief explanation of drawings]

FIG. 1 is a block circuit configuration diagram showing an embodiment of a disc motor control circuit of a disc recording/reproducing apparatus according to the present invention, and FIG. 2 shows a specific configuration of a sample hold circuit and a low-pass filter used in the embodiment. A circuit diagram showing,
FIG. 3 is a diagram for explaining the additional recording operation of the same embodiment;
FIGS. 4 and 5 are block circuit diagrams showing other embodiments of the present invention, respectively. DESCRIPTION OF SYMBOLS 11... RF signal detection circuit, 12... Frequency detection circuit, 13... Phase detection circuit, 14... Sample pulse generation circuit, 141... Synchronization signal detection circuit, 142...
...Synchronization period generation counter, 143...Pulse generation circuit, 15...Adder, 16...Level comparator, 17
... Drive signal setting circuit, 175... Up/down counter, 176... D/A converter, 177... Data latch circuit, 18... Sample hold circuit, 19
...Low pass filter, 20...Amplifier, 21...
・Disc motor.

Claims (1)

[Claims] Used in disc recording and reproducing devices that record and reproduce information signals on recordable discs, extracts synchronization signals from the information signals recorded on the disc, and generates automatic frequency control signals and automatic phase control signals from the synchronization frequency and synchronization phase. In a disk motor control circuit of a disk recording and reproducing device that controls the rotational speed of a disk motor based on these control signals, digital coding is performed in which the automatic frequency control signal and the automatic phase control signal are added and converted into a digital code. means, first driving means for driving the disk motor based on the code signal converted by the digital encoding means, and a code converted by the digital encoding means at the time of switching from the reproduction state to the recording state. digital code holding means for holding a signal; digital code changing means for sequentially changing the code signal held by the digital code holding means after the start of recording; and digital code changing means for sequentially changing the code signal held by the digital code holding means; 1. A disc motor control circuit for a disc recording/reproducing apparatus, comprising: a second driving means for driving a motor.