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JPS62268147A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62268147A
JPS62268147A JP11083186A JP11083186A JPS62268147A JP S62268147 A JPS62268147 A JP S62268147A JP 11083186 A JP11083186 A JP 11083186A JP 11083186 A JP11083186 A JP 11083186A JP S62268147 A JPS62268147 A JP S62268147A
Authority
JP
Japan
Prior art keywords
plating
via hole
electrode
substrate
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11083186A
Other languages
Japanese (ja)
Inventor
Masanori Ishii
正典 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11083186A priority Critical patent/JPS62268147A/en
Publication of JPS62268147A publication Critical patent/JPS62268147A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

PURPOSE:To prevent the generation of a cavity in brazing by filling only a via hole with a conductive material through plating utilizing an upper electrode formed to a substrate and shaping a heat sink through plating. CONSTITUTION:A via hole is formed to a compound semiconductor substrate 11, to which an element is shaped, through etching, and the via hole is filled with a conductive material such as gold plating 22 through plating by employing an upper electrode (a source electrode) 12. A conductive film consisting of Ti-Au is shaped through evaporation, and a resist pattern 23 for forming PHS 14 is patterned. When PHS 14 is plated with gold, the resist pattern is removed and a wafer is diced into chips, the GaAs substrate 11 is brazed to a package by using a solder material. Accordingly, there is no cavity, heat is made to escape efficiently, and a current path is also equalized, thus acquiring stable RF characteristics.

Description

【発明の詳細な説明】 〔概要〕 バイアホール電極形成において、先ずホール部のみにメ
ッキを行って平坦化した後にヒートシンク用電極を形成
する。[Detailed Description of the Invention] [Summary] In forming a via hole electrode, first, only the hole portion is plated and flattened, and then a heat sink electrode is formed.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法に関するもので、さらに
詳しく言えば、ＧａＡｓＦＥＴ、　ＧａＡｓＭＭＩＣ，
ＧａＡｓＩＣ等におけるバイアホールのメッキ・ヒート
シンク（ｐｌａｔｅｄ　ｈｅａｔ　５ｉｎｋ、　ＰＨ５
）構造を作成する方法に関するものである。The present invention relates to a method for manufacturing a semiconductor device, and more specifically, the present invention relates to a method for manufacturing a semiconductor device, and more specifically, a method for manufacturing a semiconductor device.
Plated heat sink for via holes in GaAsIC, etc. (plated heat 5ink, PH5
) is about how to create a structure.

〔従来の技術〕[Conventional technology]

第２図に示されるＧａＡｓ　ＦＥＴ（７）　ＰＨ５構造
は知られたものであり、同図において、１１は電界効果
トランジスタ（ＦＥＴ　）の形成されたＧａＡｓ基板、
１２ばＧａＡｓ基板上に形成された金／ニッケル／金・
ゲルマニウム（Ａｕ／　Ｎｉ／　Ａｕ−Ｇｅ）の上部電
極（ソース電極）、１３はＧａＡｓ基板１１に発注した
熱を速やかに逃すためのバイアホール（ｖｉａ　ｈｏｌ
ｅ、穴）、１４は金をメンキして作ったＰＨ３，１５は
ＰＨ３の金メッキのために設けたＴｉ　−Ａｕの通電膜
、１６はろう材、１７はパッケージである。The GaAs FET (7) PH5 structure shown in FIG. 2 is a known one, and in the same figure, 11 is a GaAs substrate on which a field effect transistor (FET) is formed;
12 Gold/nickel/gold formed on a GaAs substrate.
germanium (Au/Ni/Au-Ge) upper electrode (source electrode);
(e, hole), 14 is a PH3 made by plating gold, 15 is a Ti-Au conductive film provided for gold plating of PH3, 16 is a brazing material, and 17 is a package.

バイアホール１３はＧａＡｓ基板１１を貫通して形成さ
れ、それによって接地用の電照をとるもので、シリコン
基板に形成した素子においては基板自体が導電性である
ので、基板背面をコレクタ電極とし、そのまま例えばパ
ッケージに組み立てて接地をとることができるのである
が、ＧａＡｓは半絶縁性材料であるので、接地をとるに
は例えばワイヤを用いなければならない。ワイヤを用い
るとそれに発生するインダクタンスがきいてきて、Ｇａ
Ａｓ素子がＫ［ｌバンドとか１０　Ｇ）Ｉｚ以上の高周
波用のものである場合には、前記したインダクタンスの
発生を防止するためにＧａＡｓ基板１１にバイアホール
１３をあけて接地電極をとるのである。Ｐ）Ｉｓ　１４
は接地用接続電極と放熱用電極とを兼ねるもので、それ
は同時にメッキにより形成され、ヒートシンクおよび接
地用電極として二重の働きをする。The via hole 13 is formed penetrating the GaAs substrate 11, and is used to provide electrical illumination for grounding.In an element formed on a silicon substrate, the substrate itself is conductive, so the back surface of the substrate is used as a collector electrode. For example, it can be assembled into a package as it is and grounded, but since GaAs is a semi-insulating material, it is necessary to use, for example, a wire for grounding. When a wire is used, the inductance generated in it becomes noticeable, and Ga
If the As element is for high frequencies of K[l band or 10 G) Iz or higher, a via hole 13 is made in the GaAs substrate 11 and a ground electrode is provided to prevent the generation of the above-mentioned inductance. . P)Is 14
serves as both a grounding connection electrode and a heat dissipation electrode, which is formed by plating at the same time, and has dual functions as a heat sink and a grounding electrode.

第３図は第２図の素子の構造を示す平面図で、同図にお
いて、１８はメサエッチングまたは不純物のイオン注入
によって作られた活性層（Ｎ層）、１９はドレイン電極
、２０はゲート電極であり、ソース電極１２の下に点線
で示す如くバイアホール１３が形成され、またソース電
極（接地用電極）は素子のすべてに共通化されてウェハ
エツジまで延在し、前記したＰＨ５１４形成のための金
メッキを可能にする。FIG. 3 is a plan view showing the structure of the device shown in FIG. 2, in which 18 is an active layer (N layer) made by mesa etching or impurity ion implantation, 19 is a drain electrode, and 20 is a gate electrode. A via hole 13 is formed below the source electrode 12 as shown by the dotted line, and the source electrode (grounding electrode) is shared by all elements and extends to the wafer edge. Enables gold plating.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第２図のデバイスをろう材１６を用いてパンケージ１７
にろう付けした場合に、バイアホール１３の部分で空洞
２１が作られる。もともと、Ｐｌ（Ｓ　１４を金メッキ
するときに、バイアホール１３の部分ではメッキが均一
につかず、第２図の如くメッキされることは難しいが、
その場合でも、図に矢印で示す電流通路（ｃｕｒｒｅｎ
ｔ　ｐａｔｈ）が均一でなく、それが素子の高周波（Ｒ
Ｆ）特性に影響する問題、空気は熱伝導度がよくないの
でバイアホールの部分で熱逃げが悪く、デバイスの信頼
性に影響する問題がある。The device shown in FIG.
When soldering is performed, a cavity 21 is created at the via hole 13. Originally, when plating Pl(S 14) with gold, the via hole 13 was not plated uniformly, and it was difficult to plate it as shown in Figure 2.
Even in that case, the current path shown by the arrow in the figure
t path) is not uniform, which causes the high frequency (R
F) Problems Affecting Characteristics: Since air has poor thermal conductivity, it is difficult for heat to escape in via holes, which causes problems that affect device reliability.

ＰＨ３の金メッキにおいて、実際には第２図の如くにメ
ッキされることは理想的な場合で、現実には第４図に示
される如く、バイアホールの部分のメッキ厚は、ＰＩ（
Ｓの平坦部分の１／２〜１／３と薄くなっていて、メッ
キの薄い部分では抵抗をもつ問題がある。In PH3 gold plating, the actual plating as shown in Figure 2 is an ideal case, but in reality, as shown in Figure 4, the plating thickness at the via hole portion is PI (
It is 1/2 to 1/3 thinner than the flat part of S, and there is a problem in that the thin plated part has resistance.

本発明はこのような点に鑑みて創作されたもので、従来
のバイアホールＰＨ３構造において、ろう付けの空洞２
１の発生を防止する方法を提供することを目的とする。The present invention was created in view of these points, and in the conventional via hole PH3 structure, the brazing cavity 2
The purpose of this study is to provide a method for preventing the occurrence of 1.

ｃ問題点を解決するための手段〕 第１図ｆａ）ないしｆｄｌは本発明実施例断面図である
。c. Means for Solving the Problem] FIGS. 1 fa) to fdl are cross-sectional views of an embodiment of the present invention.

本発明においては、化合物半導体基板例えば、ＧａＡｓ
基板１１のためのヒートシンク兼接地用電極すなわちＰ
Ｈ５１４を形成するに際し、上部電極（ソース電極）１
２を利用したメッキによってＧａＡｓ基板１１に設けた
バイアホール１３を導電材料例えば金メ・７・キ２２で
埋込み、次いで通電電極１５を蒸着し、しがる後に　Ｐ
Ｈ５１４をメッキする。In the present invention, a compound semiconductor substrate such as GaAs
A heat sink/grounding electrode for the substrate 11, that is, P
When forming H514, upper electrode (source electrode) 1
The via hole 13 provided in the GaAs substrate 11 is filled with a conductive material such as gold plating 22 by plating using P2.
Plate H514.

〔作用〕[Effect]

前記した如く上部電極（ソース電極）１２はウェハエツ
ジまで延在しているので、それを用いるメッキよってバ
イアホール１３内に金メッキ２２を作ってバイアホール
１３を埋込み、平坦になったＧａＡｓ基板１１の背面上
にＰＨ５１４をメッキするので、従来例の空／１ｉ１２
１がなくなり、前記した問題点が解決されるのである。As mentioned above, since the upper electrode (source electrode) 12 extends to the wafer edge, the upper electrode (source electrode) 12 is used to form a gold plating 22 in the via hole 13 and bury the via hole 13. Since PH514 is plated on the top, the conventional empty/1i12
1 is eliminated, and the above-mentioned problem is solved.

〔実施例〕〔Example〕

以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.

第１図（ａｌないしくｄ＋に本発明方法を実施する工程
における半導体装置要部が断面で示される。FIG. 1 (al to d+) shows a cross section of the main part of a semiconductor device in the process of carrying out the method of the present invention.

第１図（ａｌ参照； 素子が形成された化合物半導体基板例えばＧａＡｓ基板
１１に従来例の場合と同様にエツチングによってバイア
ホール１３を形成し、次いで上部電極（ソース電極）１
２を用いるメッキによってバイアホール１３を導電材料
例えば金メッキ２２で埋め込む。第３図を参照して説明
したように、ウェハに形成されたすべての上部（ソース
）電極１２は共通化されウェハエツジまで延在するので
、通電膜などを設けることな（通常のメッキによってハ
イアホール１３を金メッキで埋めることができる。FIG. 1 (see al.) A via hole 13 is formed by etching in a compound semiconductor substrate, for example, a GaAs substrate 11 on which an element is formed, as in the conventional example, and then an upper electrode (source electrode) 1 is formed.
The via hole 13 is filled with a conductive material, such as gold plating 22, by plating using 22. As explained with reference to FIG. 3, all the upper (source) electrodes 12 formed on the wafer are shared and extend to the wafer edge, so there is no need to provide a conductive film or the like (the higher holes 12 are formed by ordinary plating). can be filled with gold plating.

第１図（ｂｌ参照： 次に、Ｔｉ　−Ａｕの通電膜１５を蒸着によって形成す
る。この通電膜形成は従来例と同様になすが、バイアホ
ール１３はＡｕメフキ２２で埋め込まれているので、通
電膜１５はほぼ平坦に形成される。しかる後に、ＰＨ３
１４を形成するためのレジストパターン２３をパターニ
ングする。FIG. 1 (see BL: Next, a Ti-Au current-carrying film 15 is formed by vapor deposition. This current-carrying film is formed in the same manner as in the conventional example, but since the via hole 13 is filled with an Au foil 22, The current-carrying film 15 is formed substantially flat.After that, PH3
A resist pattern 23 for forming a resist pattern 14 is patterned.

第１図（Ｃ１参照： 次いで、従来例と同じ方法でＰＨ５１４を３０μｍの厚
さに金メッキする。FIG. 1 (see C1) Next, PH514 is plated with gold to a thickness of 30 μm using the same method as in the conventional example.

第１図（ｄ）参照ニ レジストパターンを除去し、通常の技術でウェハをチッ
プ化すると、ＧａＡｓ基板１１はパッケージにろう材１
６を用いてろう付けされうる。ろう付けした後において
、従来例の如く空洞２１が存在しないので、熱逃がしが
効率良く行われ、また電流通路も均一になるので、安定
したＲＦ特性が得られる。When the resist pattern shown in FIG. 1(d) is removed and the wafer is made into chips using a normal technique, the GaAs substrate 11 is attached to the package with the brazing material 1.
6 can be used for brazing. After brazing, since there is no cavity 21 as in the conventional example, heat is efficiently dissipated, and the current path is also uniform, so stable RF characteristics can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上性べてきたように本発明によれば、ＧａＡｓ素子の
実装において、安定したＲＦ特性が得られ、熱逃がしく
ヒートシンク）も効率良くなされデバイスの信頼性向上
に有効である。なお、以上はＧａＡｓ基板を例に説明し
たが、本発明の通用範囲はその場合に限定されるもので
はなく、その他の化合物半導体基板のＰＨ５構造の場合
にも及ぶものである。As described above, according to the present invention, when mounting a GaAs element, stable RF characteristics can be obtained, heat can be efficiently dissipated (heat sink), and the reliability of the device can be improved. Although the above description has been made using a GaAs substrate as an example, the scope of the present invention is not limited to that case, but also extends to the case of a PH5 structure of other compound semiconductor substrates.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａｌないしくｄｌは本発明実施例の断面図、第
２図は従来例ＧａＡｓ素子の断面図、第３図は従来例Ｇ
ａＡｓ素子の平面図、第４図は従来例の問題点を示す断
面図である。 第１図ないし第４図において、 １１はＧａＡｓ基板、 １２は上部（ソース）電極、 １３はバイアホール、 １４はＰＨ３。 １５は通電膜、 １６はろう材、 １７はパッケージ、 １８は活性層、 １９はトレイン電極、 ２０はゲート電極、 ２１は空洞、 ２２は金メッキ、 ２３はレジストパターンである。 代理人　　弁理士　　久木元　　　彰 復代理人　弁理士　　大　菅　義　之 ゝ−−−−４ｚノ・キ２２ ’−ＰＨ５１４ 本を朗突゛地Δ？１断韻正 第１図 タ乏東Ａ列断叫諷 第２図 るｌ、ＬＡ列早動記 第３図 疫紹りＩＩ−阻題７弘をオイ因 第４図Figure 1 (al and dl are cross-sectional views of the embodiments of the present invention, Figure 2 is a cross-sectional view of a conventional GaAs element, and Figure 3 is a cross-sectional view of a conventional example G).
The plan view of the aAs element and FIG. 4 are cross-sectional views showing problems in the conventional example. 1 to 4, 11 is a GaAs substrate, 12 is an upper (source) electrode, 13 is a via hole, and 14 is a PH3. 15 is a conductive film, 16 is a brazing material, 17 is a package, 18 is an active layer, 19 is a train electrode, 20 is a gate electrode, 21 is a cavity, 22 is gold plating, and 23 is a resist pattern. Agent: Gen Kuki, Akifuku Agent: Yoshio Osuga, Patent Attorney ---4z No. 22'-PH514 Where can I read this book? 1 Dansyoku Seiji Figure 1 Tabo East A row Danshoku Rhythm 2nd Figure ru l, LA row Hayadoki 3rd picture Epidemic Introduction II-Hiboshi 7 Hiroshi oiin Figure 4

Claims (1)

【特許請求の範囲】 化合物半導体基板（１１）にバイアホール（１３）を形
成し、このバイアホール（１３）を通って熱逃がしを兼
ねた接地電極となるメッキヒートシンク（１４）を形成
する方法において、 前記基板（１１）に形成した上部電極（１２）を利用す
るメッキによりバイアホール（１３）内部のみを導電材
料（２２）で埋め込み、 しかる後にヒートシンク（１４）をメッキ形成すること
を特徴とする半導体装置の製造方法。[Claims] In a method of forming a via hole (13) in a compound semiconductor substrate (11) and forming a plating heat sink (14) that serves as a ground electrode that also serves as a heat dissipation through the via hole (13). , Filling only the inside of the via hole (13) with a conductive material (22) by plating using the upper electrode (12) formed on the substrate (11), and then forming the heat sink (14) by plating. A method for manufacturing a semiconductor device.
JP11083186A 1986-05-16 1986-05-16 Manufacture of semiconductor device Pending JPS62268147A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11083186A JPS62268147A (en) 1986-05-16 1986-05-16 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11083186A JPS62268147A (en) 1986-05-16 1986-05-16 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62268147A true JPS62268147A (en) 1987-11-20

Family

ID=14545768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11083186A Pending JPS62268147A (en) 1986-05-16 1986-05-16 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62268147A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4970578A (en) * 1987-05-01 1990-11-13 Raytheon Company Selective backside plating of GaAs monolithic microwave integrated circuits
US5051811A (en) * 1987-08-31 1991-09-24 Texas Instruments Incorporated Solder or brazing barrier
JPH04311069A (en) * 1991-04-08 1992-11-02 Mitsubishi Electric Corp Semiconductor device
JPH11243307A (en) * 1997-11-26 1999-09-07 Trw Inc Millimetric wave ltcc package
US6284567B1 (en) * 1999-06-15 2001-09-04 Samsung Electro-Mechanics Co., Ltd. Microsensor, and packaging method therefor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4970578A (en) * 1987-05-01 1990-11-13 Raytheon Company Selective backside plating of GaAs monolithic microwave integrated circuits
US5051811A (en) * 1987-08-31 1991-09-24 Texas Instruments Incorporated Solder or brazing barrier
JPH04311069A (en) * 1991-04-08 1992-11-02 Mitsubishi Electric Corp Semiconductor device
JPH11243307A (en) * 1997-11-26 1999-09-07 Trw Inc Millimetric wave ltcc package
US6284567B1 (en) * 1999-06-15 2001-09-04 Samsung Electro-Mechanics Co., Ltd. Microsensor, and packaging method therefor

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