JP3260414B2 - Semiconductor device with bump and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having bumps and a method of manufacturing the same. More particularly, the present invention relates to a semiconductor device with bumps provided on a semiconductor device for electrically and thermally connecting to external terminals, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, as one form of mounting a semiconductor element in a semiconductor device, as shown in FIG. 9, a bump is formed on an electrode on the surface of a semiconductor substrate, and the semiconductor substrate is turned toward the mounting substrate. There is a method of connecting the electrode on the side and the mounting substrate electrode by a bump, which is called a flip chip method. In recent years, the flip-chip method has been considered as an effective method for LSIs and the like, which tend to increase the number of input / output terminals and to be miniaturized, since high-density mounting is possible. Further, in a power transistor, a bump is utilized not only as an electrode but also as a heat radiating path for heat generated in an element.

Conventional bumps provided on the semiconductor device have a straight wall type shown in FIG. 8A and a mushroom type shown in FIG. 8B. A conventional general process in the bump manufacturing process is shown below.
(1) An insulating film is formed on a semiconductor substrate so as to expose a portion corresponding to a bump forming portion of an electrode provided on the semiconductor substrate, and (2) a plating process is performed on the entire substrate so as to cover the exposed electrode. Forming a conductive metal layer, (3) forming a photoresist layer with a patterned bump, (4) forming a bump by plating along the photoresist pattern, (5) removing the photoresist layer,
(6) The conductive metal layer for plating is further removed. It is.

[0004]

When the bump on the semiconductor device is considered not only as an electrode but also as a heat radiating path for heat generated from the element during operation, the larger the cross-sectional area of the bump, the more heat flows. The heat dissipation effect is improved due to the increase. However, since the size of the contact surface between the electrode on the semiconductor substrate and the bump is determined by the layout of the wiring, the cross-sectional area of the bump cannot be increased arbitrarily.

When the heat dissipation effect is considered among the conventional bump shapes, the mushroom type has an umbrella portion as shown in FIG. Some advantage for heat dissipation. However, the mushroom type bump has a flat top at the top of the bump due to the manufacturing process, and the area of the top is equal to the cross-sectional area of the straight portion. Since the amount of heat passing through the bump is proportional to the cross-sectional area of the bump, even if much heat is passed through the umbrella, the cross-sectional area decreases toward the top of the bump. Is limited. Therefore, even if the top of the bump is slightly crushed due to the connection with the mounting substrate and the connection area with the electrode on the mounting substrate is slightly increased, as described above, it is only somewhat advantageous as compared with the straight wall type.

Further, when the interval (pitch) between the bumps is small, even if the umbrella portion is enlarged to improve the heat radiation effect, the umbrella portions of the adjacent bumps come into contact with each other,
Since an electrical short occurs between the bumps, even during the manufacturing process, if the umbrella of the mushroom touches the bump during the bump growth by the plating during the manufacturing process, the umbrella causes the photoresist layer or the conductive metal layer for plating. Is enclosed, so that the photoresist layer and the conductive metal layer for plating cannot be removed by a lift-off or etching operation. Further, even when the pitch between the bumps is large, there is a limitation that the size of the bump cannot be increased as much as possible due to the limitation of the area of the contact portion with the bump on the mounting substrate connected to the semiconductor device with bumps.

[0007]

Means for Solving the Problems Thus, according to this invention, the bump is provided on the electrode of the semiconductor substrate surface, the shape of the bump larger area of the parietal than the area of the lower, opposite Te <br/> supermarkets Type, and the cap portion protruding from the electrode
A semiconductor device with bumps , wherein the bumps are for connection between an electrode on the surface of the semiconductor substrate and a mounting substrate electrode. The bump of the present invention is shown in FIG.
As shown in FIG. 1B, the shape of the bump has a larger area at the top than the area at the bottom, and has a reverse tapered shape, so that the heat of the bump can be conducted as compared with the conventional bump. Since the effective cross-sectional area is large (the cross-sectional area of the mushroom type at the rate-limiting portion of heat radiation), a sufficient heat radiation effect can be expected. Further, since the inverted tapered bump has no umbrella portion and the bump does not protrude outside the electrode portion, it is not necessary to consider contact with the adjacent bump as in the mushroom type.

Further, in order to form the above-mentioned inverted tapered bump, a photoresist is applied on a semiconductor substrate, and in order to pattern the bump, a multiple exposure is performed when exposing the photoresist layer. A method for manufacturing a semiconductor device with bumps is provided, wherein the area of the top of the head is larger than the area of the lower part, and exposure is performed so as to form a reverse taper, and further, bumps are formed in the photoresist pattern. .

The semiconductor substrate used in the present invention is not particularly limited, and for example, a Si substrate can be used. Known photoresists can be used as the photoresist to be used. For example, PMER P-AR900 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) is preferable. In addition, examples of the material for forming the bump include Au, Cu, and Ni.

Next, a method of manufacturing a reverse taper type bump is as follows.
First, the photoresist layer is patterned in a reverse taper type by multiple exposure of the photoresist layer. This multiple exposure is performed by exposing the photoresist having the remaining film ratio as shown in FIG. 2 to the exposure pattern shown in FIG.
3 is developed as shown in FIG. 4A at the exposure amount of, but the -section of FIG. 3 is developed as shown in FIG. 4-B at the exposure amount of Y in FIG. This is because the residual film ratio is 0 at the exposure amount X, so that the portions A, B, and C in FIG. 3 are completely developed, and the shape shown in FIG. In the case of the amount Y, the remaining film amount is 50%. Therefore, in the portions A and C in FIG.
This is because the portion is exposed twice, so that the photoresist is completely developed to have a shape as shown in FIG. 4-B.

Therefore, by arbitrarily selecting the number of overlapping patterns and the shape of the exposure pattern, it is possible to manufacture the reverse tapered bump into an arbitrary shape. Furthermore,
As a method for forming the metal for bumps on the photoresist layer patterned in the reverse taper type, a plating method is exemplified, and an electroplating method is preferable.

[0012]

EXAMPLE An inverted tapered bump of the present invention was manufactured based on FIG. An electrode 8 is formed on the Si substrate 1 with a thickness of 8000 ° by a sputtering method, an insulating film 3 made of SiO ₂ is formed with a thickness of 2000 ° by a CVD method, and a region for forming a reverse tapered bump is dry-etched. To expose the electrode 8 (FIG. 5-A).

A conductive metal film for plating 4 made of Au (in order to ensure good plating properties when plating the bumps) is formed to a thickness of 2000 mm by a vacuum evaporation method so as to cover the Si substrate 1. A photoresist layer 5 for a bump pattern was applied to a thickness of 20 μm (see FIG. 5).
B). This photoresist layer 5 has the property of the residual film rate curve shown in FIG.

Next, by exposing at a dose of 150 mj / cm ³ with the quadruple exposure pattern shown in FIG. 7, developing, and removing the resist, the pattern 6 of the reverse tapered bump was patterned into a photoresist ( Fig. 5-
C). Au was electroplated to form bumps 7 according to the pattern 6 (FIG. 5D). Further, the photoresist layer 5 was dissolved and removed, and the conductive metal layer 4 for plating was removed by ion etching. Was formed (FIG. 5-E).

The formed reverse tapered bump 7 has a low area of 500 μm ² and a top area of 1500 μm.
m ² , and the height was 20 μm.

[0016]

According to the present invention, since the electrode surface on the semiconductor substrate and the electrode surface on the mounting substrate can all be used for bump connection by the reverse tapered bump, the heat radiation effect of the bump can be maximized. it can.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of an inverted tapered bump of the present invention.

FIG. 2 is a schematic diagram showing a remaining film curve of a photoresist.

FIG. 3 is a schematic view showing an example of an exposure pattern according to the present invention.

FIG. 4 is a schematic sectional view of a photoresist layer developed by a conventional method and a method of the present invention.

FIG. 5 is a schematic explanatory view of a manufacturing method in the present invention.

FIG. 6 is a schematic view showing a remaining film rate curve of a photoresist used in an example of the present invention.

FIG. 7 is a schematic view of an exposure pattern performed in an example of the present invention.

FIG. 8 is a schematic sectional view showing the shape of a conventional bump.

FIG. 9 is a schematic cross-sectional view illustrating connection between a semiconductor substrate and a mounting substrate using bumps.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 Si substrate (semiconductor substrate) 2 bump forming portion 3 insulating film 4 conductive metal layer for plating 5 photoresist layer 6 resist pattern of reverse taper type bump 7 reverse taper type bump 8 electrode 11 mounting substrate 12 semiconductor substrate 13 reverse taper type bump 14 electrode 21 mounting substrate 22 semiconductor substrate 23 bump

Continuation of front page (56) References JP-A-3-185731 (JP, A) JP-A-2-98951 (JP, A) JP-A-47-24766 (JP, A) JP-A-63-160364 (JP) JP-A-3-248528 (JP, A) JP-A-4-324681 (JP, A) JP-A-5-251448 (JP, A) JP-A-63-156343 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/60

Claims (2)

(57) [Claims] 1. A bump is provided on an electrode on the surface of a semiconductor substrate, the shape of the bump is larger at the top of the head than at the bottom, is a reverse taper type, and protrudes from the electrode.
A semiconductor device with bumps, wherein the semiconductor device has a shape without a cap, and the bumps are used for connection between electrodes on the surface of the semiconductor substrate and electrodes on the mounting substrate. 2. A method of applying a photoresist on a semiconductor substrate and performing multiple exposure when exposing the photoresist layer to pattern the bump, so that the area of the top of the bump is smaller than the area of the bottom of the bump. Large and inverted
A method for manufacturing a semiconductor device with bumps, comprising exposing to a pattern and forming a bump in the photoresist pattern.