JPS62194731A - Ecl output circuit - Google Patents
Ecl output circuitInfo
- Publication number
- JPS62194731A JPS62194731A JP61035136A JP3513686A JPS62194731A JP S62194731 A JPS62194731 A JP S62194731A JP 61035136 A JP61035136 A JP 61035136A JP 3513686 A JP3513686 A JP 3513686A JP S62194731 A JPS62194731 A JP S62194731A
- Authority
- JP
- Japan
- Prior art keywords
- output
- level
- ecl
- resistor
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000003472 neutralizing effect Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、符号変換回路に係り、特にＣＭＯＳレベルを
ＥＣＬレベルに変換する低消費電力の出力インター７エ
イスに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a code conversion circuit, and more particularly to a low power consumption output interface for converting a CMOS level to an ECL level.
従来のＥＣＬ出力回路は、昭和６０年度 １子通信学会
総合全国大会講演論文集（ｓａｓ）「Ｅｃｔ。The conventional ECL output circuit is described in the 1985 Single Child Communication Society General Conference Proceedings (SAS) "Ect.
コンハチプルＣＭＯ８ＳＲＡＭにおける出方インタフェ
イス回路」に記載のように、バイポーラトランジスタと
ＭＯＳトランジスタを複合し、低消費電力化を図ったも
のがあるが、出方レベルの規格値合致及びスイッチング
動作向上の点については特に配慮さ、ｔｔていなかった
。As described in ``Output interface circuit for convertible CMO8 SRAM'', there are some that combine bipolar transistors and MOS transistors to reduce power consumption, but there are issues with meeting the standard value of output level and improving switching operation. There was no particular consideration, tt.
上記従来例では、出力レベルとスイッチング動作向−Ｈ
の点についての配慮がされておらず、出方レベルがＥＣ
Ｌ標準規格に合致しないことや、出力レベルの切換時間
が長くなるといっ＋ｍ念があった。In the conventional example above, the output level and switching operation direction -H
There is no consideration given to this point, and the level of output is EC.
I was worried that it would not comply with the L standard and that it would take a long time to change the output level.
本発明は、低消費電力で出力レベルがＥＣＬレベルの標
準規格に合致し、かつスイッチング動作スピードを向上
したＥｃＬ出方回路を提供することを目的と°する。SUMMARY OF THE INVENTION An object of the present invention is to provide an ECL output circuit with low power consumption, an output level that meets the ECL level standard, and an improved switching operation speed.
２γ問題点を解決するための手段〕
上記目的は、バイポーラトランジスタとＭＯＳトランジ
スタとによりＥＣＬ出方回路を構成し、出力段バイポー
ラトランジスタのペースをダイオードとレベルシフト抵
抗の直列回路でクランプし、かつ電流制御抵抗とスピー
ド・アンプコンデンサの並列回路を、初段インバータを
構成するＮＭＯＳのソースとグランドの間に挿入するこ
とにより達成される。[Means for solving the 2γ problem] The above purpose is to configure an ECL output circuit using bipolar transistors and MOS transistors, clamp the pace of the output stage bipolar transistor with a series circuit of a diode and a level shift resistor, and This is achieved by inserting a parallel circuit of a control resistor and a speed amplifier capacitor between the source of the NMOS forming the first stage inverter and the ground.
レベルシフト抵抗は、ＥＣＬ出力回路が低レベルを出力
する際の電圧降下によりＥＣＬ低レベルをＥＣＬ標準規
格に合致させるものである。The level shift resistor causes the ECL low level to meet the ECL standard by dropping the voltage when the ECL output circuit outputs the low level.
スピード・アップコンデンサは、出力段トランジスタの
ペースの蓄積電荷を中和して蓄積時間を短くし、応答の
遅れを小さくするものである。これによりスイッチング
動作スピードの向上が図られる。The speed-up capacitor neutralizes the accumulated charge of the output stage transistor, shortens the accumulation time, and reduces the delay in response. This improves the switching operation speed.
以下、本発明の一実施例を図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.
本発明のＥＣＬ出力回路は、しきい値を設定した′・初
段インバータ（Ｍｔ ： ＰＭＯＳ，Ｍ２： ＮＭＯＳ
） 。The ECL output circuit of the present invention includes a first-stage inverter (Mt: PMOS, M2: NMOS) with a set threshold value.
).
電流制御抵抗Ｒ＋＋スピード・アップコンデンサＣＩ＋
クランプダイオードＤＩ＋ レベルシフト抵抗Ｒ２＋出
力段トランジスタＱ＋及び負荷抵抗Ｒ３より成る。Current control resistor R++ Speed up capacitor CI+
Clamp diode DI+ Consists of level shift resistor R2, output stage transistor Q+, and load resistor R3.
ＣＭＯＳレベル信号は、ｉｖｌ ＯＳのゲート幅により
しきい値が入力側でＣＩＶＩ ＯＳレベル中心、出力側
でＥＣＬレベル中心に設定した初段インバータ（Ｍｌ。The CMOS level signal is sent to the first stage inverter (Ml.
Ｍ２）！こ入力される。この出力はダイオードＤＩによ
りクランプされ、出力段トランジスタＱ１により′電源
■ＴＴでバイアスされ１ヒ負荷抵抗Ｒ３ｔこＥＣＬ出力
として出力される。M2)! This is input. This output is clamped by the diode DI, biased by the power supply TT by the output stage transistor Q1, and outputted from the load resistor R3t as an ECL output.
ＥＣＬ出力の高ンベルは、Ｐ Ｍ ＯＳ Ｍｔがオン。When the ECL output is high, PMOS Mt is on.
Ｎ ＭＯＳ Ｍ２がオフ、クランプダイオードＤ１がオ
フ状態での出力段トランジスタＱｔのペース・エミッタ
間電圧により決まる。また低レベルは、ＰＭＯＳＭ＋が
オフ、ＮＭＯＳＭ２がオン、クランプダイオードＤ＋が
動作状態の時の、クランプダイオードＤＩ及びレベルシ
フト抵抗Ｒ２による電圧降下に出力段トランジスタＱｓ
のペース・エミッタ間電圧を加えたものとなる。本回路
では低レベルを設定する際、クランプダイオードＤ１を
微少電流で動作させることと、ＭＯＳトランジスタによ
るスイッチング動作により低消費電力化が可能となる。It is determined by the pace-emitter voltage of the output stage transistor Qt when the NMOS M2 is off and the clamp diode D1 is off. Also, the low level is caused by the voltage drop caused by the clamp diode DI and level shift resistor R2 when PMOSM+ is off, NMOSM2 is on, and clamp diode D+ is in operation.
is the sum of the pace-emitter voltage. In this circuit, when setting a low level, it is possible to reduce power consumption by operating the clamp diode D1 with a small current and by switching operation using a MOS transistor.
抵抗Ｒ２は、低レベル出力時にクランプダイオードＤ１
に流れる電流が微少であるため、クランプダイオードＤ
１と直列に付加し、出力段トランジスタＱｌのペース′
成圧を降下させ、出力レベルをＥＣＬ標準規格に合致さ
せるものである。またスピード・アップコンデンサＣ１
の値を、抵抗Ｒ１＋ コンデンサＣｔの並列回路１の時
定数より決まる周波数が出力回路の動作周波数とほぼ等
しくなるようにすることにより、出力段トランジスタＱ
ｌのペースの蓄積電荷を中和して蓄積時間を短くシ、応
答の遅れを小さくする。これにより高速動作が可９しで
ある。Resistor R2 connects to clamp diode D1 during low level output.
Since the current flowing through the clamp diode D is very small,
1 in series with the output stage transistor Ql'
This lowers the forming pressure and brings the output level into compliance with the ECL standard. Also speed up capacitor C1
The output stage transistor Q
By neutralizing the accumulated charge at a pace of 1, the accumulation time is shortened, and the response delay is reduced. This allows high-speed operation.
図面に示した実施例は、正相出力回路であるが、初段に
インバータを付加することにより逆相出力回路が構成可
能であり、正相出力回路と同様の効果が得られる。The embodiment shown in the drawings is a positive phase output circuit, but by adding an inverter to the first stage, a negative phase output circuit can be constructed, and the same effects as the positive phase output circuit can be obtained.
本実施例は、ＩＣの出力インターフェイスｆｃ ４応用
され、ＩＣの低消費電力化、尚運動作に効果的である。This embodiment is applied to an IC output interface fc4, and is effective for reducing IC power consumption and for motor operation.
本発明によれば、低消費″電力で出力レベルが、ＥＣＬ
標準規格に合致し、かつスイッチング動作の速いＥＣＬ
出力回路を形成することが可能でろる。According to the present invention, the output level can be adjusted to ECL with low power consumption.
ECL that meets standards and has fast switching operation
It would be possible to form an output circuit.
図面は本発明番こよるＥＣＬ田力回路の一実施例回路図
である。
Ｍｌ・・初段インバータＰＭＯＳ
Ｍ２・・・初段インバータＮＭＯＳ
Ｒ＋・・・電流”ｉｌｉ：Ｊ碑抵抗
Ｃ１・・・スピードアップコンデンサ
Ｄ１・・・クランプダイオード
Ｒ２・・・レベルシフト抵抗
Ｑｌ・・・出力段トランジスタ
Ｒ３・・・負荷抵抗
、／−゛The drawing is a circuit diagram of an embodiment of the ECL circuit according to the present invention. Ml...First stage inverter PMOS M2...First stage inverter NMOS R+...Current "ili: J monument resistance C1...Speed up capacitor D1...Clamp diode R2...Level shift resistor Ql...Output stage Transistor R3...Load resistance, /-゛
Claims (1)
イポーラトランジスタ出力段とより構成されるＣＭＯＳ
レベル−ＥＣＬレベル変換回路において、抵抗とコンデ
ンサの並列回路をインバータを構成するＮＭＯＳのソー
スとグランドの間に挿入するとともに、上記インバータ
の出力と接続される出力段バイポーラトランジスタのベ
ースをダイオードと抵抗の直列回路を介して電源に接続
したことを特徴とするＥＣＬ出力回路。1. CMOS consisting of a first stage inverter consisting of PMOS and NMOS and a bipolar transistor output stage
In the level-ECL level conversion circuit, a parallel circuit of a resistor and a capacitor is inserted between the source of the NMOS constituting the inverter and the ground, and the base of the output stage bipolar transistor connected to the output of the inverter is connected to the base of the diode and the resistor. An ECL output circuit characterized by being connected to a power supply via a series circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61035136A JPS62194731A (en) | 1986-02-21 | 1986-02-21 | Ecl output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61035136A JPS62194731A (en) | 1986-02-21 | 1986-02-21 | Ecl output circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62194731A true JPS62194731A (en) | 1987-08-27 |
Family
ID=12433501
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61035136A Pending JPS62194731A (en) | 1986-02-21 | 1986-02-21 | Ecl output circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62194731A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03278615A (en) * | 1990-03-28 | 1991-12-10 | Nec Corp | Level conversion circuit |
| EP0980144A2 (en) * | 1998-08-11 | 2000-02-16 | Fairchild Semiconductor Corporation | Transceiver driver with programmable edge rate control independent of fabrication process, supply voltage and temperature |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5838033A (en) * | 1981-08-28 | 1983-03-05 | Toshiba Corp | Exclusive or circuit |
| JPS5967728A (en) * | 1982-10-12 | 1984-04-17 | Hitachi Ltd | Cmos integrated circuit device |
-
1986
- 1986-02-21 JP JP61035136A patent/JPS62194731A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5838033A (en) * | 1981-08-28 | 1983-03-05 | Toshiba Corp | Exclusive or circuit |
| JPS5967728A (en) * | 1982-10-12 | 1984-04-17 | Hitachi Ltd | Cmos integrated circuit device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03278615A (en) * | 1990-03-28 | 1991-12-10 | Nec Corp | Level conversion circuit |
| EP0980144A2 (en) * | 1998-08-11 | 2000-02-16 | Fairchild Semiconductor Corporation | Transceiver driver with programmable edge rate control independent of fabrication process, supply voltage and temperature |
| EP0980144A3 (en) * | 1998-08-11 | 2000-05-24 | Fairchild Semiconductor Corporation | Transceiver driver with programmable edge rate control independent of fabrication process, supply voltage and temperature |
| US6670822B2 (en) | 1998-08-11 | 2003-12-30 | Fairchild Semiconductor Corporation | Transceiver driver with programmable edge rate control independent of fabrication process, supply voltage, and temperature |
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