JPH0774556A - Differential cmos logic circuit - Google Patents

Abstract

PURPOSE:To shorten delay time when a load capacity becomes large by connecting diodes between the high potential power source of a differential amplifier circuit and the common source of plural driving transistors. CONSTITUTION:Input signals Vin are provided with the amplitude of -0.8-1.6V and when the built-in voltage of the diodes D1 and D2 is set at 1.6V, the voltage of the connection point of the common source of nMOSFETs 21 and 22 and a constant current circuit PS is fixed at 1.6V. In this case, when the value of a load element Z is adjusted and the threshold value of the FET 21 is set at 0.8V, it becomes the same as the voltage of the signals Vin, a current is not made flow to the FET 21 and the signals of the bar of the output signals Vout become '0'. Also, when the signals Vin are -1.6V, the signals of the bar of the signals Vout become -0.8V and the high level of the output signals of the differential amplifier circuit coincides with a high potential level. Then, logic can be surely attained in a short time with a small amplitude logical operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of constructing a CMOS logic circuit, and more particularly to a differential type CMOS logic circuit capable of taking a logic with a small amplitude signal.

[0002]

2. Description of the Related Art FIG. 10 shows a CMO using a MOSFET.
It is a figure which shows the prior art example of the CMOS inverter circuit as S logic circuit structure. This conventional example is described by Kayama in "Ultra High Speed MO.
S device ", pp 207, 1986.

[0003]

This conventional inverter circuit realizes the inverting operation by connecting the nMOSFET 11 and the pMOSFET 12 and using both gates as input terminals and each drain as an output terminal. Further, this inverter circuit operates with a large amplitude signal (0
Since it operates with an amplitude between V and the power supply voltage), there is a problem that the delay time increases especially when the load capacitance increases.

To solve this problem, that is, in order to shorten the delay time when the load capacitance becomes large, the differential amplifier circuit shown in FIG. 11 (1) may be used. In this conventional differential amplifier circuit, a load Z is connected between the drain of the nMOSFET 13 and a high potential power source (GND), a constant current source PS is connected to the source of the nMOSFET 13, and a drain of the nMOSFET 14 and a high potential power source (GND).
D) is connected to the load Z, a constant current source PS is connected to the source of the nMOSFET 14, and nMOSFETs 13 and 1 are connected.
The differential input signal is applied to each gate of
An output signal is taken out from each drain of the SFETs 13 and 14.

By using the differential amplifier circuit shown in FIG. 11A, the output signal can be reduced in amplitude.
Even if the load capacity becomes large, the delay time can be shortened. Note that reducing the amplitude of the output signal means EC
L level (High level is -0.8V, low level is -0.8V
It is to take logic at a level of 1.6V).

However, in this case, complete current switching cannot be performed for the high level input signal, that is, the level of the output signal shifts to the low level side as shown in FIG. 11 (2). Will end up. To this end, FIG.
The same circuit as the conventional differential amplifier circuit shown in (1) is shown in FIG.
When connected to the latter stage of the conventional differential amplifier circuit shown in FIG. 1 (1) (that is, when two conventional differential amplifier circuits shown in FIG. 11 (1) are connected in cascade), the level of the input signal seen from the latter stage circuit. Is too low, the latter circuit cannot output a signal corresponding to the input signal of the latter circuit, that is, the latter circuit cannot execute a small amplitude logic operation.

The present invention can reduce the delay time when the load capacitance becomes large, and further, the differential type C
An object of the present invention is to provide a differential CMOS logic circuit in which, when two MOS logic circuits are connected in cascade, the differential CMOS logic circuit in the subsequent stage can surely perform a small amplitude logical operation. .

[0008]

According to a first aspect of the present invention, in a CMOS differential amplifier circuit, a diode is connected between a high potential power source and a common source of a driving transistor or a differential input signal is applied. The first and second diodes are respectively connected between the gate and the source of the second drive transistor.

[0009]

According to the present invention, in a CMOS differential amplifier circuit, a diode is connected between a high potential power source and a common source of a driving transistor, or a first and a second driving transistor for applying a differential input signal. Since the first and second diodes are connected between the gate and source, respectively, the delay time when the load capacitance becomes large can be shortened, and when two differential CMOS logic circuits are connected in cascade, The differential CMOS logic circuit in the subsequent stage can surely perform the small amplitude logic operation.

[0010]

1 is a differential type C which is a first embodiment of the present invention.
It is a circuit diagram which shows MOS logic circuit L1.

The differential CMOS logic circuit L1 is composed of a CMOS differential amplifier circuit having nMOSFETs 21 and 22 which are drive transistors, a load element Z and a constant current source PS, and Schottky diodes D1 and D2. ing.

The drain of the nMOSFET 21 is connected to the high potential source (GND) via the load element Z, and the nMOSF
The source of ET21 is connected to the constant current source PS,
The input signal V _in is supplied to the gate of the FET 21, and nMO
An inverted signal of the input signal V _in (V
_The signal shown by adding a bar to _out ) is output. Also,
The drain of the nMOSFET 22 is connected to the high potential source (GND) through the load element Z, the source of the nMOSFET 22 is connected to the constant current source PS, the inverted signal of the input signal V _in is supplied to the gate of the nMOSFET 22, and the nMOS 22 is supplied.
The same signal as the input signal V _in (V
_The signal indicated by _out ) is output.

The Schottky diodes D1 and D2 are
High-potential power supply (GND) and nMO connected in series with each other
It is connected between the common sources of the SFETs 21 and 22, the anode of the diode D1 is connected to the high potential power source (GND), the cathode of the diode D1 and the anode of the diode D2 are connected, and the cathode of the diode D2 is the common source. It is connected to the.

Next, the operation of the differential CMOS logic circuit L1 will be described.

FIG. 2 shows the differential CMOS logic circuit L1.
5 is a diagram showing a relationship between an input signal waveform and an output signal waveform in FIG.

[0016] When attention is paid to the input signal V _in, the input signal V _in has an amplitude of -0.8V~-1.6V. In addition, the built-in voltage of the diodes D1 and D2 is 1.6V.
Is set to the
The voltage at the connection point between the common source of 2 and the constant current circuit PS is −
It is assumed that the threshold value of the nMOSFET 21 is set to 0.8V by fixing the value of the load element Z and the like at a fixed value of 1.6V.

Here, when the input signal V _in is −0.8 V, the value of the input signal V _{in and} the value of the threshold value are the same, so that no current flows in the nMOSFET 21 and its output signal V _out. The signal of the bar of 0V (GN
On the other hand, when the input signal V _in is −1.6 V, the value of the input signal V _in is larger than the threshold value, so that a current flows through the nMOSFET 21 and its output signal V in
_{The out} bar signal becomes -0.8 as shown in FIG.
These operations are the same for the nMOSFET 22.

In the differential CMOS logic circuit L1, since the high level of the output signal of the differential amplifier circuit coincides with the high potential power supply level, the dynamic CMOS logic circuit L1 has a small amplitude logic operation (ECL level (high level). Is set to -0.8V and a low level is set to -1.6V). Therefore, the differential CMOS logic circuit L1 can be executed.
When two are connected in cascade, the differential CMOS of the subsequent stage
The logic circuit L1 can surely perform the small-amplitude logic operation. Further, since the differential CMOS logic circuit L1 executes the small-amplitude logic operation, the delay time can be shortened even when the load capacitance becomes large.

Although two Schottky diodes (D1, D2) are provided in the differential CMOS logic circuit L1, the Schottky diode D1 or D2 is adjusted to adjust the built-in voltage. -Instead of the diodes D1 and D2, only the Schottky diode D1 may be provided.
That is, in the above-described embodiment, in the differential amplifier circuit configured by the MOSFET, between the high potential power source of the differential amplifier circuit and the common source of the first and second drive transistors to which the differential input signal is applied, It has a diode connected,
Only one diode may be provided, or two or more diodes may be provided.

The threshold values of the nMOSFETs 21 and 22 can be set to arbitrary values as long as they are smaller than the built-in voltage values of the diodes D1 and D2.

FIG. 3 is a diagram showing a configuration example of a series gate type differential logic circuit L2 according to the second embodiment of the present invention.

Series gate type differential logic circuit L2
Is provided with two circuits similar to the differential CMOS logic circuit L1 and the nMOSFET 25 is provided between the common source and the constant current circuit PS in the first differential CMOS logic circuit L1. NMOSFET is provided between the common source and the constant current circuit PS in the differential CMOS logic circuit L1.
28 is provided, a high potential power source (GND) and a constant current circuit P
Schottky diodes D7, D8, D9 between S
A series circuit of is provided.

That is, the Schottky diodes D3 and D4 connected in series are connected to the high potential power source (GND).
And a Schottky diode D connected in series with each other and connected in common to the common sources of the nMOSFETs 23 and 24 which are the driving transistors forming the first-stage gate.
5 and D6 are a high-potential power supply (GND) and an nMOSFET 2 which is a drive transistor forming a second-stage gate.
It is connected between the common source of 6 and 27.

Also in the case of the series gate type differential logic circuit L2, as in the case of the differential type CMOS logic circuit L1,
Since the high level of the output signal of the series gate type differential logic circuit L2 coincides with the high potential power supply level, it is possible to execute a small amplitude logic operation, so that the delay time is reduced even when the load capacitance becomes large. In addition, when two series gate type differential logic circuits L2 are connected in cascade, the series gate type differential logic circuit L2 in the subsequent stage can surely perform a small amplitude logic operation. You can

In the series gate type differential logic circuit L2, when the input signals V _inA and V _inB become "1, 1", only the output signal V _out0 becomes "1" and the other signals. The output signals V _out1 , V _out2 , and V _out3 are “0”, and similarly, the input signals V _inA and V _inB are “1, 0”, “0,
1 "," 0, 0 ", output signals V _out0 , V
_out1 , V _out2 , and V _out3 each become "1", and "1"
Output signals other than the output signal that has become "0" become "0".

The Schottky diodes D7 and D
Instead of 8, D9, one, two or four or more Schottky diodes may be used.

FIG. 4 is a circuit diagram showing the configuration of a differential CMOS logic circuit L3 according to the third embodiment of the present invention.

This differential type CMOS logic circuit L3 is shown in FIG.
After the CMOS differential amplifier circuit L1 shown in FIG.
By adding a source follower circuit composed of T, high load driving of output is enabled. The source follower circuit is composed of an nMOSFET 29 and a constant current source PS, and an nMOSFET 30 and a constant current source PS. ing.

The constant current value flowing in the nMOSFETs 29, 30 in the source follower circuit, or nM.
By adjusting the threshold voltages of the OSFETs 29 and 30, the level shift amount of the output signal can be arbitrarily adjusted. Furthermore, if the input / output level of the differential CMOS logic circuit L3 is matched with the input / output level of the bipolar ECL circuit, the ECL interface (high level: -0.8
V, low level: -1.6 V) is possible.

FIG. 5 is a diagram showing the relationship between the signal amplitude and the delay time of the differential logic circuits L1, L2 and L3 in each of the above embodiments.

Here, the vertical axis represents the differential logic circuit L1,
The conventional CM shown in FIG. 10 is used as the delay time of L2 and L3.
Indicates the value standardized by the delay time of the OS inverter circuit,
The horizontal axis shows the signal amplitude normalized by the power supply voltage.

In FIG. 5, "C _pd " is the delay time in each of the above-mentioned embodiments, and "C _pd (CMOS)" is the delay time in the conventional CMOS inverter circuit shown in FIG. The above "delay time" means that when the input signal changes from "0" to "1", the input signal is "0".
It is the time until the output signal becomes 1/2 between "1" and "0" after becoming 1/2 between "1" and "1".

From FIG. 5, the differential CMOS logic circuit L1,
It is understood that the smaller the signal amplitude of L2 and L3 is, the shorter the delay time of the differential CMOS logic circuits L1, L2 and L3 becomes, and the higher speed operation becomes possible. For example, when the signal amplitude is set to 1/4 of the power supply voltage,
Compared with the conventional CMOS inverter circuit shown in 0, the delay time can be reduced to about 1/2.

FIG. 6 is a diagram showing a configuration example of a differential type CMOS logic circuit L4 which is a fourth embodiment of the present invention.

The differential CMOS logic circuit L4 includes nMOSFETs 31 and 32 which are drive transistors and a load element Z.
And a CMOS differential amplifier circuit having a constant current source PS and Schottky diodes D10 and D11.

The drain of the nMOSFET 31 is connected to the high potential source (GND) via the load element Z, and the nMOSF
The source of ET31 is connected to the constant current source PS,
The input signal V _in is supplied to the gate of the FET 31 and
An inverted signal of the input signal V _in (V
_The signal shown by adding a bar to _out ) is output. Also,
The drain of the nMOSFET 32 is connected to the high potential source (GND) via the load element Z, the source of the nMOSFET 32 is connected to the constant current source PS, the inverted signal of the input signal V _in is supplied to the gate of the nMOSFET 32, and the nMOS 32 is supplied.
The same signal as the input signal V _in (V
_The signal indicated by _out ) is output.

The anode of the Schottky diode D1 is connected to the gate of the nMOSFET 31, the cathode of the Schottky diode D1 is connected to the source of the nMOSFET 31, and the anode of the Schottky diode D2 is connected to the gate of the nMOSFET 32.・ The cathode of diode D2 is nMOSFET
Connected to 32 sources.

Next, the operation of the differential CMOS logic circuit L4 will be described.

In this case as well, the relationship between the input signal and the output signal is assumed to be the same as that shown in FIG. In other words, when attention is paid to the input signal V _in, the input signal V _in is -0.8V
It has an amplitude of ~ -1.6V. However, the built-in voltage of the diodes D10 and D11 is set to 0.8 V, and the nMOS is adjusted by adjusting the values of the load element Z and the like.
Assuming that the thresholds of the FETs 31 and 32 are set to 0V, when the input voltage is -0.8V to -1.6V, the input voltage is -0.8V and the built-in voltage of the diode D10 is -0.8V. Is added to become -1.6V, so
Common source of nMOSFETs 31 and 32 and constant current circuit P
The voltage at the connection point with S is fixed at -1.6V.

Here, when the input signal V _in is −0.8V, the voltage between the source and the gate of the nMOSFET 31 is 0.8V, and the threshold value is 0V.
A current flows through the nMOSFET 21 and its output signal is −
When the input signal V _in is −1.6 V, the voltage between the source and the gate of the nMOSFET 31 is 0 V, which is the same as the threshold value 0 V, and n
No current flows through MOSFET 31 and its output signal is -0
It becomes V (GND). These operations are nMOSFET
The same applies to 32.

Any threshold value can be adopted as the threshold value of the nMOSFETs 31 and 32 as long as it is smaller than the value of the built-in voltage of the diodes D10 and D11.

In the differential CMOS logic circuit L4, since the high level of the output signal of the differential amplifier circuit coincides with the high potential power supply level, the differential CMOS logic circuit L4 has a small amplitude logic operation (ECL level (high level). The operation of taking logic at a level of −0.8V and a low level of −1.6V) can be executed, and therefore, the delay time can be shortened even when the load capacitance becomes large, and When two differential CMOS logic circuits L4 are connected in cascade, the differential CMOS logic circuit L4 at the subsequent stage can surely perform a small amplitude logic operation.

Although one Schottky diode is provided for one nMOSFET in the differential CMOS logic circuit L4, the Schottky diode is adjusted by adjusting the built-in voltage of the Schottky diode D10. Instead of D10
A plurality of Schottky diodes connected in series may be provided.

That is, the differential CMOS logic circuit L4
Is a differential amplifier circuit composed of MOSFETs, in which a first diode is connected between the gate and source of a first drive transistor to which one of the differential input signals of the differential amplifier circuit is applied. Although the second diode is connected between the gate and the source of the second drive transistor for applying the other, only one diode may be provided as the first diode or the second diode,
Moreover, you may make it provide what connected two or more diodes in series.

FIG. 7 is a diagram showing a differential type CMOS logic circuit L5 which is a fifth embodiment of the present invention, and is a CM shown in FIG.
FIG. 11 is a circuit diagram showing a configuration in which a source follower circuit made up of a MOSFET is added after the OS differential amplifier circuit L4.

In the differential CMOS logic circuit L5, the source follower circuit is composed of an nMOSFET 33 and a constant current source PS, and an nMOSFET 34 and a constant current source PS. By adding it to the latter stage of the dynamic amplifier circuit, it becomes possible to drive the output under high load.

Further, the level shift amount of the output signal can be arbitrarily adjusted by adjusting the constant current value flowing in the nMOSFETs 33 and 34 or the threshold voltage of the nMOSFETs 33 and 34 in the source follower circuit of the fifth embodiment. You can Further, if the input / output level of the differential CMOS logic circuit L5 is matched with the input / output level of the bipolar ECL circuit, an ECL interface (high level: -0.8V, low level: -1.6V) becomes possible. .

In the differential CMOS logic circuits L4 and L5, as shown in FIG. 5, the delay time of the differential logic circuit is shortened as the signal amplitude of the differential logic circuit is reduced. Therefore, high speed operation becomes possible. For example, when the signal amplitude is set to 1/4 of the power supply voltage, the delay time can be reduced to about 1/2 of that of the conventional CMOS inverter circuit shown in FIG.

FIG. 8 shows a MOSFET 31 and a Schottky diode D1 in the differential CMOS logic circuit L4.
It is a figure which shows the example which formed 0 and the same insulating substrate.

As compared with the conventional bulk substrate, the Schottky diode can be realized on the insulating substrate in a small area and the parasitic capacitance can be reduced, so that the logical operation can be speeded up.

FIG. 9 shows a MOSFET 31 and a Schottky diode D10 formed on the same silicon active layer 41 on an insulating substrate, which is smaller in area than the device structure of the example shown in FIG. be able to.

In each of the above embodiments, a diode other than the Schottky diode may be used instead of the Schottky diode.

[0053]

According to the present invention, the delay time when the load capacitance becomes large can be shortened, and when two differential type CMOS logic circuits are connected in cascade, the differential type of the subsequent stage is connected. The CMOS logic circuit can reliably perform a small-amplitude logic operation.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a differential CMOS logic circuit L1 which is a first embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between an input signal waveform and an output signal waveform in the differential CMOS logic circuit L1.

FIG. 3 is a diagram showing a configuration example of a series gate type differential logic circuit L2 which is a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a differential type CMOS logic circuit L3 which is a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a differential logic circuit L1 in each of the above embodiments.
It is a figure which shows the relationship of the signal amplitude with respect to the delay time of L2 and L3.

FIG. 6 is a diagram showing a configuration example of a differential CMOS logic circuit L4 which is a fourth embodiment of the present invention.

FIG. 7 is a diagram showing a differential CMOS logic circuit L5 according to a fifth embodiment of the present invention.

FIG. 8 is a MOSF in a differential CMOS logic circuit L4
It is a figure which shows the example which formed ET31 and Schottky diode D10 on the same insulating substrate.

FIG. 9 is a diagram showing an example in which a MOSFET 31 and a Schottky diode D10 are formed in the same silicon active layer 41 on an insulating substrate.

FIG. 10 is a diagram showing a conventional example of a CMOS inverter circuit as a CMOS logic circuit configuration using MOSFETs.

FIG. 11 is a diagram showing a conventional differential amplifier circuit performing a small amplitude operation and a diagram showing a relationship between an input signal and an output signal in the differential amplifier circuit.

[Explanation of symbols]

 L1 to L5 ... Differential type CMOS logic circuit, D1 to D11 ... Schottky diode, 21 to 34 ... nCMOSFET, 41 ... Silicon active layer, PS ... Constant current source, Z ... Load element.

Claims (4)

[Claims] 1. A differential amplifier circuit composed of MOSFETs, wherein a diode is provided between a high potential power source of the differential amplifier circuit and a common source of first and second drive transistors for applying a differential input signal. Differential type CM characterized by connecting
OS logic circuit. 2. A differential amplifier circuit composed of MOSFETs, wherein first one of differential input signals of the differential amplifier circuit is applied.
A first diode is connected between the gate and the source of the driving transistor of the second driving circuit, and the other of the differential input signals is applied to the second diode.
A differential CMOS logic circuit characterized in that a second diode is connected between the gate and the source of the driving transistor. 3. The differential follower circuit according to claim 1, wherein a source follower circuit composed of a MOSFET is connected to each output terminal of the differential amplifier circuit, and an output signal of the source follower circuit is connected to the differential CMOS logic. A differential CMOS logic circuit characterized by being used as an output signal of the circuit. 4. The differential CMOS logic circuit according to claim 2 or 3, wherein the MOSFET and the diode are formed on the same insulating substrate or on the same silicon active region on the insulating substrate. .