JPS62125711A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form a peripheral circuit with a small occupied area by supplying a load current via a conduction channel type MISFET operated at a high current amplification factor without any back gate bias supplied. CONSTITUTION:In outputting the 1st power voltage VPP fed to the input terminal 1 from an output terminal 3, a low voltage is fed to a MISFET Q3 from the 3rd signal terminal 6, the MISFET Q3 is conducted and the input terminal 1 and the output terminal 3 are conducted electrically. A high voltage boosted by a charge pump or the like from the 1st signal terminal 4 is fed to a MISFET Q1, which is conducted. A low voltage is fed to a MISFET Q3 from the 2nd signal terminal 5, the FET Q2 is conducted and a base electrode of the FET Q3 goes to a potential equal to the 1st power voltage VPP. Since the MISFET Q3 is of P-channel type, no back gate bias is fed and the FET Q3 is operated at a high current amplification factor, then the occupied area of the MISFET Q3 is very small.

Description

[Detailed Description of the Invention] r Industrial Application Field] The present invention relates to a semiconductor device, and particularly to a complementary MISF E,
T'''C'''C'' This relates to a semiconductor device around a terminal that is also used as a power source and a power source.

[Conventional technology]

Conventionally, as shown in FIG. 3, a semiconductor device around a dual-purpose input and power supply terminal has an input terminal to which an input signal or a first power supply voltage Vpp having a higher potential than the input signal is applied; An input circuit 2 for receiving a signal, an output terminal 3 for outputting a first power supply voltage Vpp, a drain electrode connected to the input terminal 1'f1, and a gate electrode connected to the first signal terminal 4.
, an N-channel enhancement type M T 5FETQ whose source electrode is connected to the output terminal 3 and whose substrate electrode is connected to the ground terminal.

In FIG. 3, when an input signal is applied to input terminal 1, input circuit 2 receives the input signal, and a low potential is supplied from signal terminal 4 to MISFETQ1, making MISFETQ+ non-active. It becomes conductive and the input terminal
When F1 and the output terminal 3 are electrically cut off, and on the other hand, the first voltage, Ig, and the voltage Vpp are applied to the input terminal 1, a high voltage boosted by a charge pump or the like is output from the signal terminal 4. M L S F E T Q 1 is applied to M
I S F E T Q 1 becomes conductive, the input terminal 1 and the output terminal 3 are electrically connected, and the first power supply voltage Vpp is output from the output terminal 3.

[Problems to be Solved by the Invention] The conventional semiconductor device described above supplies current to the load connected to the output terminal via the MISFET to which a back gate bias is applied, and then the voltage drop across the MISFET is In order to make M I S F as small as possible,
It is necessary to set the channel width of ET to be very large, which causes the problem of increasing the occupied area.
The charge pump for boosting the gate potential of the ISFET also has a problem in that it occupies a very large area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device in which a peripheral circuit including an input terminal and a power supply terminal can be formed in a small area.

[Means for Solving the Problems] The semiconductor device of the invention of Genuine Leather 1 has an input terminal to which either an input signal or a first power supply voltage having a potential different from that of the input signal is applied; an input circuit for receiving a signal, an output terminal for outputting the first power supply voltage, a drain electrode connected to the input terminal, a drain electrode connected to the first signal terminal, and a substrate electrode connected to a ground terminal. an enhancement type first MISFET having a channel of one conductivity type, the drain electrode is connected to the second power supply voltage supply terminal, the goo electrode is connected to the second signal terminal, and the source electrode is connected to the second signal terminal; a depletion type second M I S FE having a channel of the same conductivity type as the first M FET, which is connected to the source electrode of the M T, a drain electrode connected to the output terminal, a gate electrode connected to either the second power supply voltage supply terminal, the second signal terminal, or at least the third signal terminal, and a source electrode; is connected to the input terminal and the substrate electrode is connected to the first MISF.
the first MISFET connected to the source electrode of the ET;
and at least one enhancement type third MISFET having a channel of opposite conductivity type.

The semiconductor device according to the invention of Genuine Leather 2 includes an input terminal to which either an input signal or a first power supply voltage having a potential different from that of the input signal is applied, an input circuit that receives the input signal, and the first power supply voltage. an output terminal for outputting a power supply voltage of 1, a drain electrode, an in electrode connected to the input terminal, a gate electrode connected to the first signal terminal, and a substrate electrode connected to the ground terminal. The first enhancement type with
MISFET, a drain electrode is connected to a second power supply voltage supply terminal, a gate electrode is connected to a second signal terminal, a source electrode is connected to the source electrode of the first MISFET, and a substrate electrode is connected to a ground terminal. said first M
A depletion type second MISFET having a channel of the same conductivity type as I S F E 'T', a drain electrode connected to the output terminal and a gate electrode connected to the second power supply voltage supply terminal or the second MISFET; conductivity opposite to the first MISFET, which is connected to either one of the signal terminal or at least a third signal terminal, whose source electrode is connected to the input terminal, and whose substrate electrode is connected to the source electrode of the first MISFET. at least one enhancement type third MISFET having a type channel, a drain electrode connected to the second power supply voltage supply terminal and a gate electrode connected to the second enhancement type MISFET;
The first MIS is connected to a signal terminal of the first MIS, a source electrode is connected to the output terminal, and a substrate electrode is connected to the ground terminal.
It is configured to include a depletion type fourth MISFET having a channel of the same conductivity type as the FET.

〔Example〕

Next, fruit 11 of the present invention! , an example will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the invention of genuine leather 1.

As shown in FIG. 1, the semiconductor device includes an input terminal 1 to which either an input signal or a first power supply voltage Vpp having a higher potential than the input signal is applied, and an input circuit 2 for receiving the input signal. , an output terminal 3 that outputs a first power supply voltage pP, an N-channel transistor whose drain electrode is connected to the input terminal 1, whose gate electrode is connected to the first signal terminal 4, and whose substrate electrode is connected to the ground terminal. Enhancement 1 - Mento type 1
MIS FET Q1 and the drain electrode is the second
The power supply voltage is 10V, the gate electrode is connected to the second signal terminal 5, and the source electrode is MISFE.
A second N-channel depletion type MIS connected to the source electrode of TQ and whose substrate electrode is connected to the ground terminal.
FE"rQ2 and a P-channel enhanced transistor whose drain electrode is connected to the output terminal 3, whose gate electrode is connected to the third signal terminal 6, whose source electrode is connected to the input terminal 1, and whose substrate electrode is connected to the source electrode of MISFETQl. and a third MIS FET Q 3 of the men-type type.

In FIG. 1, when an input signal is applied to the input terminal 1, the input signal is received at the input circuit Fl@2, and a high potential is applied from the third signal terminal 6 to MISFETQ.
3, the MISFET Q3 becomes non-conductive, and the input terminal 1 and the output terminal 3 are electrically cut off. or,
The low potential from the first signal terminal 4 is M I S F E T
is applied to Qr, the MISFET Q becomes non-conductive, and the signal from the second signal terminal 5 to M E S F E
A high potential is applied to TQ2, and M I S F
E T Q 2 becomes conductive and M I S F E
Even if the substrate electrode of TQ3 has a potential equal to the second power supply voltage +VCC and an input signal varying between the ground potential and the second power supply voltage +Vcc is applied to the input terminal 1, the MISFE
The source electrode (P+diffusion N) of TQ3 is never forward biased.

Next, when outputting the first voltage Jg and voltage Vpp applied to the input terminal 1 from the output terminal 3, the third signal terminal 6
A low potential is applied to MISFETQ3 from
TQ3 becomes conductive, the input terminal 1 and the output terminal 3 are electrically connected, and a high voltage boosted by a charge bomber or the like is transferred from the first signal terminal 4 to M I S F E
MISFETQl is applied to TQl, and MISFETQl becomes conductive, and a low potential is applied from the second signal terminal 5 to MISFETQl.
The voltage is applied to SFETQ2, causing MISFETQ2 to become non-conductive and the substrate electrode of MISFETQ3 to have a potential equal to the first power supply voltage Vpp.

Here, since M T S F E T Q 3 is a P-channel type, no gate bias is applied and it operates at a high current amplification factor.
3 occupies a very small area.

Furthermore, tlS l to which back gate bias is applied
' Since there is no need to supply load current through ETQ +, the area occupied by MTSFETQ can be made very small, and the
``A capacitor for boosting the gate potential of Q can be formed with a small occupied area.

FIG. 2 is a circuit diagram showing an embodiment of the invention of Section 2.

In the embodiment shown in FIG. 2, in the semiconductor device of the first invention described above, the drain electrode is connected to the supply terminal of the second power supply voltage +Vcc, the D- electrode is connected to the second signal terminal 5, and the source electrode is connected to the second signal terminal 5. is connected to the output terminal 3, and a fourth N-channel depletion type MTS FET Q 4 whose poles are connected to the ground terminal on the substrates ',' is additionally connected.

As shown in FIG. 2, by adding MISFET Q4, the period when the input signal is applied to input terminal 1,
A high potential is applied from the second signal terminal 5 to the MISFET Q4, and the MISFETQ becomes conductive, so that the input terminal 1 and the output terminal 3 are electrically cut off, and the second power supply voltage +VCC is applied from the output terminal 3. It can be output.

〔Effect of the invention〕

As explained above, in the semiconductor device of the present invention, in the peripheral circuit of the input and power supply terminal, the load current is supplied through the conductive channel type MISF and ET that operate at a high current amplification factor without applying a back gate bias. This has the effect that the peripheral circuit can be formed with a small occupied area.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the invention of Section 1, FIG. 2 is a circuit diagram of an embodiment of the invention of Section 2, and FIG. 3 is a circuit diagram of an example of a conventional semiconductor device. 1... Input terminal, 2... Input circuit, 3... Output terminal, 4.5.6... Signal terminal. Hair l diagram early 2 concave

Claims (2)

[Claims] (1) An input terminal to which either an input signal or a first power supply voltage having a potential different from that of the input signal is applied, an input circuit that receives the input signal, and outputs the first power supply voltage. an enhancement type first MISFET having an output terminal and a channel of one conductivity type, the drain electrode being connected to the input terminal, the gate electrode being connected to the first signal terminal, and the substrate electrode being connected to the ground terminal; A drain electrode is connected to the second power supply voltage supply terminal, a gate electrode is connected to the second signal terminal, and a source electrode is connected to the first MI
a depletion-type second MISFET having a channel of the same conductivity type as the first MISFET, which is connected to the source electrode of the SFET and whose substrate electrode is connected to a ground terminal;
A drain electrode is connected to the output terminal, a gate electrode is connected to one of the second power supply voltage supply terminal, the second signal terminal, or at least the third signal terminal, and the source electrode is connected to the input terminal. The connected substrate electrode is connected to the first MIS.
the first MISFE connected to the source electrode of the FET;
A semiconductor device comprising at least one enhancement type third MISFET having a channel of a conductivity type opposite to T. (2) an input terminal to which either an input signal or a first power supply voltage having a potential different from that of the input signal is applied; an input circuit that receives the input signal; and an input circuit that outputs the first power supply voltage. an enhancement type first MISFET having an output terminal and a channel of one conductivity type, the drain electrode being connected to the input terminal, the gate electrode being connected to the first signal terminal, and the substrate electrode being connected to the ground terminal; A drain electrode is connected to the second power supply voltage supply terminal, a gate electrode is connected to the second signal terminal, and a source electrode is connected to the first MI
a depletion-type second MISFET having a channel of the same conductivity type as the first MISFET, which is connected to the source electrode of the SFET and whose substrate electrode is connected to a ground terminal;
A drain electrode is connected to the output terminal, a gate electrode is connected to one of the second power supply voltage supply terminal, the second signal terminal, or at least the third signal terminal, and the source electrode is connected to the input terminal. The connected substrate electrode is connected to the first MIS.
the first MISFE connected to the source electrode of the FET;
at least one enhancement type third MISFET having a channel of a conductivity type opposite to T, a drain electrode connected to the second power supply voltage supply terminal, and a gate electrode connected to the second signal terminal; The first electrode has a source electrode connected to the output terminal and a substrate electrode connected to the ground terminal.
A semiconductor device comprising a depletion type fourth MISFET having a channel of the same conductivity type as the MISFET.